[deliverable/linux.git] / arch / arm64 / boot / dts / freescale / fsl-ls1043a.dtsi

/*
 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
 *
 * Copyright 2014-2015, Freescale Semiconductor
 *
 * Mingkai Hu <Mingkai.hu@freescale.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/ {
	compatible = "fsl,ls1043a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		/*
		 * We expect the enable-method for cpu's to be "psci", but this
		 * is dependent on the SoC FW, which will fill this in.
		 *
		 * Currently supported enable-method is psci v0.2
		 */
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			clocks = <&clockgen 1 0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			clocks = <&clockgen 1 0>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x2>;
			clocks = <&clockgen 1 0>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x3>;
			clocks = <&clockgen 1 0>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0 0x80000000>;
		      /* DRAM space 1, size: 2GiB DRAM */
	};

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	reboot {
		compatible ="syscon-reboot";
		regmap = <&dcfg>;
		offset = <0xb0>;
		mask = <0x02>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 0x1>, /* Physical Secure PPI */
			     <1 14 0x1>, /* Physical Non-Secure PPI */
			     <1 11 0x1>, /* Virtual PPI */
			     <1 10 0x1>; /* Hypervisor PPI */
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 106 0x4>,
			     <0 107 0x4>,
			     <0 95 0x4>,
			     <0 97 0x4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
	};

	gic: interrupt-controller@1400000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
		      <0x0 0x1402000 0 0x2000>, /* GICC */
		      <0x0 0x1404000 0 0x2000>, /* GICH */
		      <0x0 0x1406000 0 0x2000>; /* GICV */
		interrupts = <1 9 0xf08>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		clockgen: clocking@1ee1000 {
			compatible = "fsl,ls1043a-clockgen";
			reg = <0x0 0x1ee1000 0x0 0x1000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		scfg: scfg@1570000 {
			compatible = "fsl,ls1043a-scfg", "syscon";
			reg = <0x0 0x1570000 0x0 0x10000>;
			big-endian;
		};

		dcfg: dcfg@1ee0000 {
			compatible = "fsl,ls1043a-dcfg", "syscon";
			reg = <0x0 0x1ee0000 0x0 0x10000>;
			big-endian;
		};

		ifc: ifc@1530000 {
			compatible = "fsl,ifc", "simple-bus";
			reg = <0x0 0x1530000 0x0 0x10000>;
			interrupts = <0 43 0x4>;
		};

		qspi: quadspi@1550000 {
			compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x1550000 0x0 0x10000>,
				<0x0 0x40000000 0x0 0x4000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <0 99 0x4>;
			clock-names = "qspi_en", "qspi";
			clocks = <&clockgen 4 0>, <&clockgen 4 0>;
			big-endian;
			status = "disabled";
		};

		esdhc: esdhc@1560000 {
			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
			reg = <0x0 0x1560000 0x0 0x10000>;
			interrupts = <0 62 0x4>;
			clock-frequency = <0>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			big-endian;
			bus-width = <4>;
		};

		dspi0: dspi@2100000 {
			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <0 64 0x4>;
			clock-names = "dspi";
			clocks = <&clockgen 4 0>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		dspi1: dspi@2110000 {
			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2110000 0x0 0x10000>;
			interrupts = <0 65 0x4>;
			clock-names = "dspi";
			clocks = <&clockgen 4 0>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		i2c0: i2c@2180000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <0 56 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			dmas = <&edma0 1 39>,
			       <&edma0 1 38>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		i2c1: i2c@2190000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <0 57 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		i2c2: i2c@21a0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21a0000 0x0 0x10000>;
			interrupts = <0 58 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		i2c3: i2c@21b0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21b0000 0x0 0x10000>;
			interrupts = <0 59 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0500 0x0 0x100>;
			interrupts = <0 54 0x4>;
			clocks = <&clockgen 4 0>;
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0600 0x0 0x100>;
			interrupts = <0 54 0x4>;
			clocks = <&clockgen 4 0>;
		};

		duart2: serial@21d0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0500 0x0 0x100>;
			interrupts = <0 55 0x4>;
			clocks = <&clockgen 4 0>;
		};

		duart3: serial@21d0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0600 0x0 0x100>;
			interrupts = <0 55 0x4>;
			clocks = <&clockgen 4 0>;
		};

		gpio1: gpio@2300000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <0 66 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2310000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <0 67 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2320000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <0 68 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@2330000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2330000 0x0 0x10000>;
			interrupts = <0 134 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		lpuart0: serial@2950000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2950000 0x0 0x1000>;
			interrupts = <0 48 0x4>;
			clocks = <&clockgen 0 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart1: serial@2960000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2960000 0x0 0x1000>;
			interrupts = <0 49 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart2: serial@2970000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2970000 0x0 0x1000>;
			interrupts = <0 50 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart3: serial@2980000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2980000 0x0 0x1000>;
			interrupts = <0 51 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart4: serial@2990000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2990000 0x0 0x1000>;
			interrupts = <0 52 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart5: serial@29a0000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x29a0000 0x0 0x1000>;
			interrupts = <0 53 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		wdog0: wdog@2ad0000 {
			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
			reg = <0x0 0x2ad0000 0x0 0x10000>;
			interrupts = <0 83 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "wdog";
			big-endian;
		};

		edma0: edma@2c00000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x2c00000 0x0 0x10000>,
			      <0x0 0x2c10000 0x0 0x10000>,
			      <0x0 0x2c20000 0x0 0x10000>;
			interrupts = <0 103 0x4>,
				     <0 103 0x4>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			big-endian;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&clockgen 4 0>,
				 <&clockgen 4 0>;
		};

		usb0: usb3@2f00000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x2f00000 0x0 0x10000>;
			interrupts = <0 60 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
		};

		usb1: usb3@3000000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3000000 0x0 0x10000>;
			interrupts = <0 61 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
		};

		usb2: usb3@3100000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3100000 0x0 0x10000>;
			interrupts = <0 63 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
		};

		sata: sata@3200000 {
			compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci";
			reg = <0x0 0x3200000 0x0 0x10000>;
			interrupts = <0 69 0x4>;
			clocks = <&clockgen 4 0>;
		};

		msi1: msi-controller1@1571000 {
			compatible = "fsl,1s1043a-msi";
			reg = <0x0 0x1571000 0x0 0x8>;
			msi-controller;
			interrupts = <0 116 0x4>;
		};

		msi2: msi-controller2@1572000 {
			compatible = "fsl,1s1043a-msi";
			reg = <0x0 0x1572000 0x0 0x8>;
			msi-controller;
			interrupts = <0 126 0x4>;
		};

		msi3: msi-controller3@1573000 {
			compatible = "fsl,1s1043a-msi";
			reg = <0x0 0x1573000 0x0 0x8>;
			msi-controller;
			interrupts = <0 160 0x4>;
		};

		pcie@3400000 {
			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 118 0x4>, /* controller interrupt */
				     <0 117 0x4>; /* PME interrupt */
			interrupt-names = "intr", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <4>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi1>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
					<0000 0 0 2 &gic 0 111 0x4>,
					<0000 0 0 3 &gic 0 112 0x4>,
					<0000 0 0 4 &gic 0 113 0x4>;
		};

		pcie@3500000 {
			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 128 0x4>,
				     <0 127 0x4>;
			interrupt-names = "intr", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <2>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
					<0000 0 0 2 &gic 0 121 0x4>,
					<0000 0 0 3 &gic 0 122 0x4>,
					<0000 0 0 4 &gic 0 123 0x4>;
		};

		pcie@3600000 {
			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 162 0x4>,
				     <0 161 0x4>;
			interrupt-names = "intr", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <2>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi3>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
					<0000 0 0 2 &gic 0 155 0x4>,
					<0000 0 0 3 &gic 0 156 0x4>,
					<0000 0 0 4 &gic 0 157 0x4>;
		};
	};

};
Commit	Line	Data
6d453cd2 MH	1	/*
	2	* Device Tree Include file for Freescale Layerscape-1043A family SoC.
	3	*
	4	* Copyright 2014-2015, Freescale Semiconductor
	5	*
	6	* Mingkai Hu <Mingkai.hu@freescale.com>
	7	*
	8	* This file is dual-licensed: you can use it either under the terms
	9	* of the GPLv2 or the X11 license, at your option. Note that this dual
	10	* licensing only applies to this file, and not this project as a
	11	* whole.
	12	*
	13	* a) This library is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of the
	16	* License, or (at your option) any later version.
	17	*
	18	* This library is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* Or, alternatively,
	24	*
	25	* b) Permission is hereby granted, free of charge, to any person
	26	* obtaining a copy of this software and associated documentation
	27	* files (the "Software"), to deal in the Software without
	28	* restriction, including without limitation the rights to use,
	29	* copy, modify, merge, publish, distribute, sublicense, and/or
	30	* sell copies of the Software, and to permit persons to whom the
	31	* Software is furnished to do so, subject to the following
	32	* conditions:
	33	*
	34	* The above copyright notice and this permission notice shall be
	35	* included in all copies or substantial portions of the Software.
	36	*
	37	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	38	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	39	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	40	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	41	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	42	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	43	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	44	* OTHER DEALINGS IN THE SOFTWARE.
	45	*/
	46
	47	/ {
	48	compatible = "fsl,ls1043a";
	49	interrupt-parent = <&gic>;
	50	#address-cells = <2>;
	51	#size-cells = <2>;
	52
	53	cpus {
	54	#address-cells = <2>;
	55	#size-cells = <0>;
	56
	57	/*
	58	* We expect the enable-method for cpu's to be "psci", but this
	59	* is dependent on the SoC FW, which will fill this in.
	60	*
	61	* Currently supported enable-method is psci v0.2
	62	*/
	63	cpu0: cpu@0 {
	64	device_type = "cpu";
65	compatible = "arm,cortex-a53";
66	reg = <0x0 0x0>;
67	clocks = <&clockgen 1 0>;
68	};
69
70	cpu1: cpu@1 {
71	device_type = "cpu";
72	compatible = "arm,cortex-a53";
73	reg = <0x0 0x1>;
74	clocks = <&clockgen 1 0>;
75	};
76
77	cpu2: cpu@2 {
78	device_type = "cpu";
79	compatible = "arm,cortex-a53";
80	reg = <0x0 0x2>;
81	clocks = <&clockgen 1 0>;
82	};
83
84	cpu3: cpu@3 {
85	device_type = "cpu";
86	compatible = "arm,cortex-a53";
87	reg = <0x0 0x3>;
88	clocks = <&clockgen 1 0>;
89	};
90	};
91
92	memory@80000000 {
93	device_type = "memory";
94	reg = <0x0 0x80000000 0 0x80000000>;
95	/* DRAM space 1, size: 2GiB DRAM */
96	};
97
98	sysclk: sysclk {
99	compatible = "fixed-clock";
100	#clock-cells = <0>;
101	clock-frequency = <100000000>;
102	clock-output-names = "sysclk";
103	};
104
105	reboot {
106	compatible ="syscon-reboot";
107	regmap = <&dcfg>;
108	offset = <0xb0>;
109	mask = <0x02>;
110	};
111
112	timer {
113	compatible = "arm,armv8-timer";
114	interrupts = <1 13 0x1>, /* Physical Secure PPI */
115	<1 14 0x1>, /* Physical Non-Secure PPI */
116	<1 11 0x1>, /* Virtual PPI */
117	<1 10 0x1>; /* Hypervisor PPI */
118	};
119
120	pmu {
121	compatible = "arm,armv8-pmuv3";
122	interrupts = <0 106 0x4>,
123	<0 107 0x4>,
124	<0 95 0x4>,
125	<0 97 0x4>;
126	interrupt-affinity = <&cpu0>,
127	<&cpu1>,
128	<&cpu2>,
129	<&cpu3>;
130	};
131
132	gic: interrupt-controller@1400000 {
133	compatible = "arm,gic-400";
134	#interrupt-cells = <3>;
135	interrupt-controller;
136	reg = <0x0 0x1401000 0 0x1000>, /* GICD */
137	<0x0 0x1402000 0 0x2000>, /* GICC */
138	<0x0 0x1404000 0 0x2000>, /* GICH */
139	<0x0 0x1406000 0 0x2000>; /* GICV */
140	interrupts = <1 9 0xf08>;
141	};
142
143	soc {
144	compatible = "simple-bus";
145	#address-cells = <2>;
146	#size-cells = <2>;
147	ranges;
148
149	clockgen: clocking@1ee1000 {
150	compatible = "fsl,ls1043a-clockgen";
151	reg = <0x0 0x1ee1000 0x0 0x1000>;
152	#clock-cells = <2>;
153	clocks = <&sysclk>;
154	};
155
156	scfg: scfg@1570000 {
157	compatible = "fsl,ls1043a-scfg", "syscon";
158	reg = <0x0 0x1570000 0x0 0x10000>;
159	big-endian;
160	};
161
162	dcfg: dcfg@1ee0000 {
163	compatible = "fsl,ls1043a-dcfg", "syscon";
164	reg = <0x0 0x1ee0000 0x0 0x10000>;
165	big-endian;
166	};
167
168	ifc: ifc@1530000 {
169	compatible = "fsl,ifc", "simple-bus";
170	reg = <0x0 0x1530000 0x0 0x10000>;
171	interrupts = <0 43 0x4>;
172	};
173
e26e054b YY	174	qspi: quadspi@1550000 {
	175	compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
	176	#address-cells = <1>;
	177	#size-cells = <0>;
	178	reg = <0x0 0x1550000 0x0 0x10000>,
	179	<0x0 0x40000000 0x0 0x4000000>;
	180	reg-names = "QuadSPI", "QuadSPI-memory";
	181	interrupts = <0 99 0x4>;
	182	clock-names = "qspi_en", "qspi";
	183	clocks = <&clockgen 4 0>, <&clockgen 4 0>;
	184	big-endian;
	185	status = "disabled";
	186	};
	187
6d453cd2 MH	188	esdhc: esdhc@1560000 {
	189	compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
	190	reg = <0x0 0x1560000 0x0 0x10000>;
	191	interrupts = <0 62 0x4>;
	192	clock-frequency = <0>;
	193	voltage-ranges = <1800 1800 3300 3300>;
	194	sdhci,auto-cmd12;
	195	big-endian;
	196	bus-width = <4>;
	197	};
	198
	199	dspi0: dspi@2100000 {
	200	compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
	201	#address-cells = <1>;
	202	#size-cells = <0>;
	203	reg = <0x0 0x2100000 0x0 0x10000>;
	204	interrupts = <0 64 0x4>;
	205	clock-names = "dspi";
	206	clocks = <&clockgen 4 0>;
	207	spi-num-chipselects = <5>;
	208	big-endian;
	209	status = "disabled";
	210	};
	211
	212	dspi1: dspi@2110000 {
	213	compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
	214	#address-cells = <1>;
	215	#size-cells = <0>;
	216	reg = <0x0 0x2110000 0x0 0x10000>;
	217	interrupts = <0 65 0x4>;
	218	clock-names = "dspi";
	219	clocks = <&clockgen 4 0>;
	220	spi-num-chipselects = <5>;
	221	big-endian;
	222	status = "disabled";
	223	};
	224
	225	i2c0: i2c@2180000 {
	226	compatible = "fsl,vf610-i2c";
	227	#address-cells = <1>;
	228	#size-cells = <0>;
	229	reg = <0x0 0x2180000 0x0 0x10000>;
	230	interrupts = <0 56 0x4>;
	231	clock-names = "i2c";
	232	clocks = <&clockgen 4 0>;
	233	dmas = <&edma0 1 39>,
	234	<&edma0 1 38>;
	235	dma-names = "tx", "rx";
	236	status = "disabled";
	237	};
	238
	239	i2c1: i2c@2190000 {
	240	compatible = "fsl,vf610-i2c";
	241	#address-cells = <1>;
	242	#size-cells = <0>;
	243	reg = <0x0 0x2190000 0x0 0x10000>;
	244	interrupts = <0 57 0x4>;
	245	clock-names = "i2c";
	246	clocks = <&clockgen 4 0>;
	247	status = "disabled";
	248	};
	249
	250	i2c2: i2c@21a0000 {
	251	compatible = "fsl,vf610-i2c";
252	#address-cells = <1>;
253	#size-cells = <0>;
254	reg = <0x0 0x21a0000 0x0 0x10000>;
255	interrupts = <0 58 0x4>;
256	clock-names = "i2c";
257	clocks = <&clockgen 4 0>;
258	status = "disabled";
259	};
260
261	i2c3: i2c@21b0000 {
262	compatible = "fsl,vf610-i2c";
263	#address-cells = <1>;
264	#size-cells = <0>;
265	reg = <0x0 0x21b0000 0x0 0x10000>;
266	interrupts = <0 59 0x4>;
267	clock-names = "i2c";
268	clocks = <&clockgen 4 0>;
269	status = "disabled";
270	};
271
272	duart0: serial@21c0500 {
273	compatible = "fsl,ns16550", "ns16550a";
274	reg = <0x00 0x21c0500 0x0 0x100>;
275	interrupts = <0 54 0x4>;
276	clocks = <&clockgen 4 0>;
277	};
278
279	duart1: serial@21c0600 {
280	compatible = "fsl,ns16550", "ns16550a";
281	reg = <0x00 0x21c0600 0x0 0x100>;
282	interrupts = <0 54 0x4>;
283	clocks = <&clockgen 4 0>;
284	};
285
286	duart2: serial@21d0500 {
287	compatible = "fsl,ns16550", "ns16550a";
288	reg = <0x0 0x21d0500 0x0 0x100>;
289	interrupts = <0 55 0x4>;
290	clocks = <&clockgen 4 0>;
291	};
292
293	duart3: serial@21d0600 {
294	compatible = "fsl,ns16550", "ns16550a";
295	reg = <0x0 0x21d0600 0x0 0x100>;
296	interrupts = <0 55 0x4>;
297	clocks = <&clockgen 4 0>;
298	};
299
300	gpio1: gpio@2300000 {
c21de87d	301	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
6d453cd2 MH	302	reg = <0x0 0x2300000 0x0 0x10000>;
	303	interrupts = <0 66 0x4>;
	304	gpio-controller;
	305	#gpio-cells = <2>;
	306	interrupt-controller;
	307	#interrupt-cells = <2>;
	308	};
	309
	310	gpio2: gpio@2310000 {
c21de87d	311	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
6d453cd2 MH	312	reg = <0x0 0x2310000 0x0 0x10000>;
	313	interrupts = <0 67 0x4>;
	314	gpio-controller;
	315	#gpio-cells = <2>;
	316	interrupt-controller;
	317	#interrupt-cells = <2>;
	318	};
	319
	320	gpio3: gpio@2320000 {
c21de87d	321	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
6d453cd2 MH	322	reg = <0x0 0x2320000 0x0 0x10000>;
	323	interrupts = <0 68 0x4>;
	324	gpio-controller;
	325	#gpio-cells = <2>;
	326	interrupt-controller;
	327	#interrupt-cells = <2>;
	328	};
	329
	330	gpio4: gpio@2330000 {
c21de87d	331	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
6d453cd2 MH	332	reg = <0x0 0x2330000 0x0 0x10000>;
	333	interrupts = <0 134 0x4>;
	334	gpio-controller;
	335	#gpio-cells = <2>;
	336	interrupt-controller;
	337	#interrupt-cells = <2>;
	338	};
	339
	340	lpuart0: serial@2950000 {
	341	compatible = "fsl,ls1021a-lpuart";
	342	reg = <0x0 0x2950000 0x0 0x1000>;
	343	interrupts = <0 48 0x4>;
	344	clocks = <&clockgen 0 0>;
	345	clock-names = "ipg";
	346	status = "disabled";
	347	};
	348
	349	lpuart1: serial@2960000 {
	350	compatible = "fsl,ls1021a-lpuart";
	351	reg = <0x0 0x2960000 0x0 0x1000>;
	352	interrupts = <0 49 0x4>;
	353	clocks = <&clockgen 4 0>;
	354	clock-names = "ipg";
	355	status = "disabled";
	356	};
	357
	358	lpuart2: serial@2970000 {
	359	compatible = "fsl,ls1021a-lpuart";
	360	reg = <0x0 0x2970000 0x0 0x1000>;
	361	interrupts = <0 50 0x4>;
	362	clocks = <&clockgen 4 0>;
	363	clock-names = "ipg";
	364	status = "disabled";
	365	};
	366
	367	lpuart3: serial@2980000 {
	368	compatible = "fsl,ls1021a-lpuart";
	369	reg = <0x0 0x2980000 0x0 0x1000>;
	370	interrupts = <0 51 0x4>;
	371	clocks = <&clockgen 4 0>;
	372	clock-names = "ipg";
	373	status = "disabled";
	374	};
	375
	376	lpuart4: serial@2990000 {
	377	compatible = "fsl,ls1021a-lpuart";
	378	reg = <0x0 0x2990000 0x0 0x1000>;
	379	interrupts = <0 52 0x4>;
	380	clocks = <&clockgen 4 0>;
	381	clock-names = "ipg";
	382	status = "disabled";
	383	};
	384
	385	lpuart5: serial@29a0000 {
	386	compatible = "fsl,ls1021a-lpuart";
	387	reg = <0x0 0x29a0000 0x0 0x1000>;
	388	interrupts = <0 53 0x4>;
	389	clocks = <&clockgen 4 0>;
	390	clock-names = "ipg";
	391	status = "disabled";
	392	};
	393
	394	wdog0: wdog@2ad0000 {
	395	compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
396	reg = <0x0 0x2ad0000 0x0 0x10000>;
397	interrupts = <0 83 0x4>;
398	clocks = <&clockgen 4 0>;
399	clock-names = "wdog";
400	big-endian;
401	};
402
403	edma0: edma@2c00000 {
404	#dma-cells = <2>;
405	compatible = "fsl,vf610-edma";
406	reg = <0x0 0x2c00000 0x0 0x10000>,
407	<0x0 0x2c10000 0x0 0x10000>,
408	<0x0 0x2c20000 0x0 0x10000>;
409	interrupts = <0 103 0x4>,
410	<0 103 0x4>;
411	interrupt-names = "edma-tx", "edma-err";
412	dma-channels = <32>;
413	big-endian;
414	clock-names = "dmamux0", "dmamux1";
415	clocks = <&clockgen 4 0>,
416	<&clockgen 4 0>;
417	};
418
419	usb0: usb3@2f00000 {
420	compatible = "snps,dwc3";
421	reg = <0x0 0x2f00000 0x0 0x10000>;
422	interrupts = <0 60 0x4>;
423	dr_mode = "host";
4c1d9ea7	424	snps,quirk-frame-length-adjustment = <0x20>;
6d453cd2 MH	425	};
	426
	427	usb1: usb3@3000000 {
	428	compatible = "snps,dwc3";
	429	reg = <0x0 0x3000000 0x0 0x10000>;
	430	interrupts = <0 61 0x4>;
	431	dr_mode = "host";
4c1d9ea7	432	snps,quirk-frame-length-adjustment = <0x20>;
6d453cd2 MH	433	};
	434
	435	usb2: usb3@3100000 {
	436	compatible = "snps,dwc3";
	437	reg = <0x0 0x3100000 0x0 0x10000>;
	438	interrupts = <0 63 0x4>;
	439	dr_mode = "host";
4c1d9ea7	440	snps,quirk-frame-length-adjustment = <0x20>;
6d453cd2 MH	441	};
	442
	443	sata: sata@3200000 {
	444	compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci";
	445	reg = <0x0 0x3200000 0x0 0x10000>;
	446	interrupts = <0 69 0x4>;
	447	clocks = <&clockgen 4 0>;
	448	};
	449
	450	msi1: msi-controller1@1571000 {
	451	compatible = "fsl,1s1043a-msi";
	452	reg = <0x0 0x1571000 0x0 0x8>;
	453	msi-controller;
	454	interrupts = <0 116 0x4>;
	455	};
	456
	457	msi2: msi-controller2@1572000 {
	458	compatible = "fsl,1s1043a-msi";
	459	reg = <0x0 0x1572000 0x0 0x8>;
	460	msi-controller;
	461	interrupts = <0 126 0x4>;
	462	};
	463
	464	msi3: msi-controller3@1573000 {
	465	compatible = "fsl,1s1043a-msi";
	466	reg = <0x0 0x1573000 0x0 0x8>;
	467	msi-controller;
	468	interrupts = <0 160 0x4>;
	469	};
	470
	471	pcie@3400000 {
	472	compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
	473	reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
	474	0x40 0x00000000 0x0 0x00002000>; /* configuration space */
	475	reg-names = "regs", "config";
	476	interrupts = <0 118 0x4>, /* controller interrupt */
	477	<0 117 0x4>; /* PME interrupt */
	478	interrupt-names = "intr", "pme";
	479	#address-cells = <3>;
	480	#size-cells = <2>;
	481	device_type = "pci";
	482	num-lanes = <4>;
	483	bus-range = <0x0 0xff>;
	484	ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
	485	0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	486	msi-parent = <&msi1>;
	487	#interrupt-cells = <1>;
	488	interrupt-map-mask = <0 0 0 7>;
	489	interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
	490	<0000 0 0 2 &gic 0 111 0x4>,
	491	<0000 0 0 3 &gic 0 112 0x4>,
	492	<0000 0 0 4 &gic 0 113 0x4>;
	493	};
	494
	495	pcie@3500000 {
	496	compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
	497	reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
	498	0x48 0x00000000 0x0 0x00002000>; /* configuration space */
	499	reg-names = "regs", "config";
	500	interrupts = <0 128 0x4>,
	501	<0 127 0x4>;
	502	interrupt-names = "intr", "pme";
	503	#address-cells = <3>;
	504	#size-cells = <2>;
505	device_type = "pci";
506	num-lanes = <2>;
507	bus-range = <0x0 0xff>;
508	ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
509	0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
510	msi-parent = <&msi2>;
511	#interrupt-cells = <1>;
512	interrupt-map-mask = <0 0 0 7>;
513	interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
514	<0000 0 0 2 &gic 0 121 0x4>,
515	<0000 0 0 3 &gic 0 122 0x4>,
516	<0000 0 0 4 &gic 0 123 0x4>;
517	};
518
519	pcie@3600000 {
520	compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
521	reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
522	0x50 0x00000000 0x0 0x00002000>; /* configuration space */
523	reg-names = "regs", "config";
524	interrupts = <0 162 0x4>,
525	<0 161 0x4>;
526	interrupt-names = "intr", "pme";
527	#address-cells = <3>;
528	#size-cells = <2>;
529	device_type = "pci";
530	num-lanes = <2>;
531	bus-range = <0x0 0xff>;
532	ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
533	0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
534	msi-parent = <&msi3>;
535	#interrupt-cells = <1>;
536	interrupt-map-mask = <0 0 0 7>;
537	interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
538	<0000 0 0 2 &gic 0 155 0x4>,
539	<0000 0 0 3 &gic 0 156 0x4>,
540	<0000 0 0 4 &gic 0 157 0x4>;
541	};
542	};
543
544	};