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6d453cd2 MH |
1 | /* |
2 | * Device Tree Include file for Freescale Layerscape-1043A family SoC. | |
3 | * | |
4 | * Copyright 2014-2015, Freescale Semiconductor | |
5 | * | |
6 | * Mingkai Hu <Mingkai.hu@freescale.com> | |
7 | * | |
8 | * This file is dual-licensed: you can use it either under the terms | |
9 | * of the GPLv2 or the X11 license, at your option. Note that this dual | |
10 | * licensing only applies to this file, and not this project as a | |
11 | * whole. | |
12 | * | |
13 | * a) This library is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of the | |
16 | * License, or (at your option) any later version. | |
17 | * | |
18 | * This library is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * Or, alternatively, | |
24 | * | |
25 | * b) Permission is hereby granted, free of charge, to any person | |
26 | * obtaining a copy of this software and associated documentation | |
27 | * files (the "Software"), to deal in the Software without | |
28 | * restriction, including without limitation the rights to use, | |
29 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
30 | * sell copies of the Software, and to permit persons to whom the | |
31 | * Software is furnished to do so, subject to the following | |
32 | * conditions: | |
33 | * | |
34 | * The above copyright notice and this permission notice shall be | |
35 | * included in all copies or substantial portions of the Software. | |
36 | * | |
37 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
38 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
39 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
40 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
41 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
42 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
43 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
44 | * OTHER DEALINGS IN THE SOFTWARE. | |
45 | */ | |
46 | ||
47 | / { | |
48 | compatible = "fsl,ls1043a"; | |
49 | interrupt-parent = <&gic>; | |
50 | #address-cells = <2>; | |
51 | #size-cells = <2>; | |
52 | ||
53 | cpus { | |
54 | #address-cells = <2>; | |
55 | #size-cells = <0>; | |
56 | ||
57 | /* | |
58 | * We expect the enable-method for cpu's to be "psci", but this | |
59 | * is dependent on the SoC FW, which will fill this in. | |
60 | * | |
61 | * Currently supported enable-method is psci v0.2 | |
62 | */ | |
63 | cpu0: cpu@0 { | |
64 | device_type = "cpu"; | |
65 | compatible = "arm,cortex-a53"; | |
66 | reg = <0x0 0x0>; | |
67 | clocks = <&clockgen 1 0>; | |
68 | }; | |
69 | ||
70 | cpu1: cpu@1 { | |
71 | device_type = "cpu"; | |
72 | compatible = "arm,cortex-a53"; | |
73 | reg = <0x0 0x1>; | |
74 | clocks = <&clockgen 1 0>; | |
75 | }; | |
76 | ||
77 | cpu2: cpu@2 { | |
78 | device_type = "cpu"; | |
79 | compatible = "arm,cortex-a53"; | |
80 | reg = <0x0 0x2>; | |
81 | clocks = <&clockgen 1 0>; | |
82 | }; | |
83 | ||
84 | cpu3: cpu@3 { | |
85 | device_type = "cpu"; | |
86 | compatible = "arm,cortex-a53"; | |
87 | reg = <0x0 0x3>; | |
88 | clocks = <&clockgen 1 0>; | |
89 | }; | |
90 | }; | |
91 | ||
92 | memory@80000000 { | |
93 | device_type = "memory"; | |
94 | reg = <0x0 0x80000000 0 0x80000000>; | |
95 | /* DRAM space 1, size: 2GiB DRAM */ | |
96 | }; | |
97 | ||
98 | sysclk: sysclk { | |
99 | compatible = "fixed-clock"; | |
100 | #clock-cells = <0>; | |
101 | clock-frequency = <100000000>; | |
102 | clock-output-names = "sysclk"; | |
103 | }; | |
104 | ||
105 | reboot { | |
106 | compatible ="syscon-reboot"; | |
107 | regmap = <&dcfg>; | |
108 | offset = <0xb0>; | |
109 | mask = <0x02>; | |
110 | }; | |
111 | ||
112 | timer { | |
113 | compatible = "arm,armv8-timer"; | |
114 | interrupts = <1 13 0x1>, /* Physical Secure PPI */ | |
115 | <1 14 0x1>, /* Physical Non-Secure PPI */ | |
116 | <1 11 0x1>, /* Virtual PPI */ | |
117 | <1 10 0x1>; /* Hypervisor PPI */ | |
118 | }; | |
119 | ||
120 | pmu { | |
121 | compatible = "arm,armv8-pmuv3"; | |
122 | interrupts = <0 106 0x4>, | |
123 | <0 107 0x4>, | |
124 | <0 95 0x4>, | |
125 | <0 97 0x4>; | |
126 | interrupt-affinity = <&cpu0>, | |
127 | <&cpu1>, | |
128 | <&cpu2>, | |
129 | <&cpu3>; | |
130 | }; | |
131 | ||
132 | gic: interrupt-controller@1400000 { | |
133 | compatible = "arm,gic-400"; | |
134 | #interrupt-cells = <3>; | |
135 | interrupt-controller; | |
136 | reg = <0x0 0x1401000 0 0x1000>, /* GICD */ | |
137 | <0x0 0x1402000 0 0x2000>, /* GICC */ | |
138 | <0x0 0x1404000 0 0x2000>, /* GICH */ | |
139 | <0x0 0x1406000 0 0x2000>; /* GICV */ | |
140 | interrupts = <1 9 0xf08>; | |
141 | }; | |
142 | ||
143 | soc { | |
144 | compatible = "simple-bus"; | |
145 | #address-cells = <2>; | |
146 | #size-cells = <2>; | |
147 | ranges; | |
148 | ||
149 | clockgen: clocking@1ee1000 { | |
150 | compatible = "fsl,ls1043a-clockgen"; | |
151 | reg = <0x0 0x1ee1000 0x0 0x1000>; | |
152 | #clock-cells = <2>; | |
153 | clocks = <&sysclk>; | |
154 | }; | |
155 | ||
156 | scfg: scfg@1570000 { | |
157 | compatible = "fsl,ls1043a-scfg", "syscon"; | |
158 | reg = <0x0 0x1570000 0x0 0x10000>; | |
159 | big-endian; | |
160 | }; | |
161 | ||
162 | dcfg: dcfg@1ee0000 { | |
163 | compatible = "fsl,ls1043a-dcfg", "syscon"; | |
164 | reg = <0x0 0x1ee0000 0x0 0x10000>; | |
165 | big-endian; | |
166 | }; | |
167 | ||
168 | ifc: ifc@1530000 { | |
169 | compatible = "fsl,ifc", "simple-bus"; | |
170 | reg = <0x0 0x1530000 0x0 0x10000>; | |
171 | interrupts = <0 43 0x4>; | |
172 | }; | |
173 | ||
174 | esdhc: esdhc@1560000 { | |
175 | compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; | |
176 | reg = <0x0 0x1560000 0x0 0x10000>; | |
177 | interrupts = <0 62 0x4>; | |
178 | clock-frequency = <0>; | |
179 | voltage-ranges = <1800 1800 3300 3300>; | |
180 | sdhci,auto-cmd12; | |
181 | big-endian; | |
182 | bus-width = <4>; | |
183 | }; | |
184 | ||
185 | dspi0: dspi@2100000 { | |
186 | compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; | |
187 | #address-cells = <1>; | |
188 | #size-cells = <0>; | |
189 | reg = <0x0 0x2100000 0x0 0x10000>; | |
190 | interrupts = <0 64 0x4>; | |
191 | clock-names = "dspi"; | |
192 | clocks = <&clockgen 4 0>; | |
193 | spi-num-chipselects = <5>; | |
194 | big-endian; | |
195 | status = "disabled"; | |
196 | }; | |
197 | ||
198 | dspi1: dspi@2110000 { | |
199 | compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; | |
200 | #address-cells = <1>; | |
201 | #size-cells = <0>; | |
202 | reg = <0x0 0x2110000 0x0 0x10000>; | |
203 | interrupts = <0 65 0x4>; | |
204 | clock-names = "dspi"; | |
205 | clocks = <&clockgen 4 0>; | |
206 | spi-num-chipselects = <5>; | |
207 | big-endian; | |
208 | status = "disabled"; | |
209 | }; | |
210 | ||
211 | i2c0: i2c@2180000 { | |
212 | compatible = "fsl,vf610-i2c"; | |
213 | #address-cells = <1>; | |
214 | #size-cells = <0>; | |
215 | reg = <0x0 0x2180000 0x0 0x10000>; | |
216 | interrupts = <0 56 0x4>; | |
217 | clock-names = "i2c"; | |
218 | clocks = <&clockgen 4 0>; | |
219 | dmas = <&edma0 1 39>, | |
220 | <&edma0 1 38>; | |
221 | dma-names = "tx", "rx"; | |
222 | status = "disabled"; | |
223 | }; | |
224 | ||
225 | i2c1: i2c@2190000 { | |
226 | compatible = "fsl,vf610-i2c"; | |
227 | #address-cells = <1>; | |
228 | #size-cells = <0>; | |
229 | reg = <0x0 0x2190000 0x0 0x10000>; | |
230 | interrupts = <0 57 0x4>; | |
231 | clock-names = "i2c"; | |
232 | clocks = <&clockgen 4 0>; | |
233 | status = "disabled"; | |
234 | }; | |
235 | ||
236 | i2c2: i2c@21a0000 { | |
237 | compatible = "fsl,vf610-i2c"; | |
238 | #address-cells = <1>; | |
239 | #size-cells = <0>; | |
240 | reg = <0x0 0x21a0000 0x0 0x10000>; | |
241 | interrupts = <0 58 0x4>; | |
242 | clock-names = "i2c"; | |
243 | clocks = <&clockgen 4 0>; | |
244 | status = "disabled"; | |
245 | }; | |
246 | ||
247 | i2c3: i2c@21b0000 { | |
248 | compatible = "fsl,vf610-i2c"; | |
249 | #address-cells = <1>; | |
250 | #size-cells = <0>; | |
251 | reg = <0x0 0x21b0000 0x0 0x10000>; | |
252 | interrupts = <0 59 0x4>; | |
253 | clock-names = "i2c"; | |
254 | clocks = <&clockgen 4 0>; | |
255 | status = "disabled"; | |
256 | }; | |
257 | ||
258 | duart0: serial@21c0500 { | |
259 | compatible = "fsl,ns16550", "ns16550a"; | |
260 | reg = <0x00 0x21c0500 0x0 0x100>; | |
261 | interrupts = <0 54 0x4>; | |
262 | clocks = <&clockgen 4 0>; | |
263 | }; | |
264 | ||
265 | duart1: serial@21c0600 { | |
266 | compatible = "fsl,ns16550", "ns16550a"; | |
267 | reg = <0x00 0x21c0600 0x0 0x100>; | |
268 | interrupts = <0 54 0x4>; | |
269 | clocks = <&clockgen 4 0>; | |
270 | }; | |
271 | ||
272 | duart2: serial@21d0500 { | |
273 | compatible = "fsl,ns16550", "ns16550a"; | |
274 | reg = <0x0 0x21d0500 0x0 0x100>; | |
275 | interrupts = <0 55 0x4>; | |
276 | clocks = <&clockgen 4 0>; | |
277 | }; | |
278 | ||
279 | duart3: serial@21d0600 { | |
280 | compatible = "fsl,ns16550", "ns16550a"; | |
281 | reg = <0x0 0x21d0600 0x0 0x100>; | |
282 | interrupts = <0 55 0x4>; | |
283 | clocks = <&clockgen 4 0>; | |
284 | }; | |
285 | ||
286 | gpio1: gpio@2300000 { | |
c21de87d | 287 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
6d453cd2 MH |
288 | reg = <0x0 0x2300000 0x0 0x10000>; |
289 | interrupts = <0 66 0x4>; | |
290 | gpio-controller; | |
291 | #gpio-cells = <2>; | |
292 | interrupt-controller; | |
293 | #interrupt-cells = <2>; | |
294 | }; | |
295 | ||
296 | gpio2: gpio@2310000 { | |
c21de87d | 297 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
6d453cd2 MH |
298 | reg = <0x0 0x2310000 0x0 0x10000>; |
299 | interrupts = <0 67 0x4>; | |
300 | gpio-controller; | |
301 | #gpio-cells = <2>; | |
302 | interrupt-controller; | |
303 | #interrupt-cells = <2>; | |
304 | }; | |
305 | ||
306 | gpio3: gpio@2320000 { | |
c21de87d | 307 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
6d453cd2 MH |
308 | reg = <0x0 0x2320000 0x0 0x10000>; |
309 | interrupts = <0 68 0x4>; | |
310 | gpio-controller; | |
311 | #gpio-cells = <2>; | |
312 | interrupt-controller; | |
313 | #interrupt-cells = <2>; | |
314 | }; | |
315 | ||
316 | gpio4: gpio@2330000 { | |
c21de87d | 317 | compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; |
6d453cd2 MH |
318 | reg = <0x0 0x2330000 0x0 0x10000>; |
319 | interrupts = <0 134 0x4>; | |
320 | gpio-controller; | |
321 | #gpio-cells = <2>; | |
322 | interrupt-controller; | |
323 | #interrupt-cells = <2>; | |
324 | }; | |
325 | ||
326 | lpuart0: serial@2950000 { | |
327 | compatible = "fsl,ls1021a-lpuart"; | |
328 | reg = <0x0 0x2950000 0x0 0x1000>; | |
329 | interrupts = <0 48 0x4>; | |
330 | clocks = <&clockgen 0 0>; | |
331 | clock-names = "ipg"; | |
332 | status = "disabled"; | |
333 | }; | |
334 | ||
335 | lpuart1: serial@2960000 { | |
336 | compatible = "fsl,ls1021a-lpuart"; | |
337 | reg = <0x0 0x2960000 0x0 0x1000>; | |
338 | interrupts = <0 49 0x4>; | |
339 | clocks = <&clockgen 4 0>; | |
340 | clock-names = "ipg"; | |
341 | status = "disabled"; | |
342 | }; | |
343 | ||
344 | lpuart2: serial@2970000 { | |
345 | compatible = "fsl,ls1021a-lpuart"; | |
346 | reg = <0x0 0x2970000 0x0 0x1000>; | |
347 | interrupts = <0 50 0x4>; | |
348 | clocks = <&clockgen 4 0>; | |
349 | clock-names = "ipg"; | |
350 | status = "disabled"; | |
351 | }; | |
352 | ||
353 | lpuart3: serial@2980000 { | |
354 | compatible = "fsl,ls1021a-lpuart"; | |
355 | reg = <0x0 0x2980000 0x0 0x1000>; | |
356 | interrupts = <0 51 0x4>; | |
357 | clocks = <&clockgen 4 0>; | |
358 | clock-names = "ipg"; | |
359 | status = "disabled"; | |
360 | }; | |
361 | ||
362 | lpuart4: serial@2990000 { | |
363 | compatible = "fsl,ls1021a-lpuart"; | |
364 | reg = <0x0 0x2990000 0x0 0x1000>; | |
365 | interrupts = <0 52 0x4>; | |
366 | clocks = <&clockgen 4 0>; | |
367 | clock-names = "ipg"; | |
368 | status = "disabled"; | |
369 | }; | |
370 | ||
371 | lpuart5: serial@29a0000 { | |
372 | compatible = "fsl,ls1021a-lpuart"; | |
373 | reg = <0x0 0x29a0000 0x0 0x1000>; | |
374 | interrupts = <0 53 0x4>; | |
375 | clocks = <&clockgen 4 0>; | |
376 | clock-names = "ipg"; | |
377 | status = "disabled"; | |
378 | }; | |
379 | ||
380 | wdog0: wdog@2ad0000 { | |
381 | compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; | |
382 | reg = <0x0 0x2ad0000 0x0 0x10000>; | |
383 | interrupts = <0 83 0x4>; | |
384 | clocks = <&clockgen 4 0>; | |
385 | clock-names = "wdog"; | |
386 | big-endian; | |
387 | }; | |
388 | ||
389 | edma0: edma@2c00000 { | |
390 | #dma-cells = <2>; | |
391 | compatible = "fsl,vf610-edma"; | |
392 | reg = <0x0 0x2c00000 0x0 0x10000>, | |
393 | <0x0 0x2c10000 0x0 0x10000>, | |
394 | <0x0 0x2c20000 0x0 0x10000>; | |
395 | interrupts = <0 103 0x4>, | |
396 | <0 103 0x4>; | |
397 | interrupt-names = "edma-tx", "edma-err"; | |
398 | dma-channels = <32>; | |
399 | big-endian; | |
400 | clock-names = "dmamux0", "dmamux1"; | |
401 | clocks = <&clockgen 4 0>, | |
402 | <&clockgen 4 0>; | |
403 | }; | |
404 | ||
405 | usb0: usb3@2f00000 { | |
406 | compatible = "snps,dwc3"; | |
407 | reg = <0x0 0x2f00000 0x0 0x10000>; | |
408 | interrupts = <0 60 0x4>; | |
409 | dr_mode = "host"; | |
4c1d9ea7 | 410 | snps,quirk-frame-length-adjustment = <0x20>; |
6d453cd2 MH |
411 | }; |
412 | ||
413 | usb1: usb3@3000000 { | |
414 | compatible = "snps,dwc3"; | |
415 | reg = <0x0 0x3000000 0x0 0x10000>; | |
416 | interrupts = <0 61 0x4>; | |
417 | dr_mode = "host"; | |
4c1d9ea7 | 418 | snps,quirk-frame-length-adjustment = <0x20>; |
6d453cd2 MH |
419 | }; |
420 | ||
421 | usb2: usb3@3100000 { | |
422 | compatible = "snps,dwc3"; | |
423 | reg = <0x0 0x3100000 0x0 0x10000>; | |
424 | interrupts = <0 63 0x4>; | |
425 | dr_mode = "host"; | |
4c1d9ea7 | 426 | snps,quirk-frame-length-adjustment = <0x20>; |
6d453cd2 MH |
427 | }; |
428 | ||
429 | sata: sata@3200000 { | |
430 | compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci"; | |
431 | reg = <0x0 0x3200000 0x0 0x10000>; | |
432 | interrupts = <0 69 0x4>; | |
433 | clocks = <&clockgen 4 0>; | |
434 | }; | |
435 | ||
436 | msi1: msi-controller1@1571000 { | |
437 | compatible = "fsl,1s1043a-msi"; | |
438 | reg = <0x0 0x1571000 0x0 0x8>; | |
439 | msi-controller; | |
440 | interrupts = <0 116 0x4>; | |
441 | }; | |
442 | ||
443 | msi2: msi-controller2@1572000 { | |
444 | compatible = "fsl,1s1043a-msi"; | |
445 | reg = <0x0 0x1572000 0x0 0x8>; | |
446 | msi-controller; | |
447 | interrupts = <0 126 0x4>; | |
448 | }; | |
449 | ||
450 | msi3: msi-controller3@1573000 { | |
451 | compatible = "fsl,1s1043a-msi"; | |
452 | reg = <0x0 0x1573000 0x0 0x8>; | |
453 | msi-controller; | |
454 | interrupts = <0 160 0x4>; | |
455 | }; | |
456 | ||
457 | pcie@3400000 { | |
458 | compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; | |
459 | reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ | |
460 | 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ | |
461 | reg-names = "regs", "config"; | |
462 | interrupts = <0 118 0x4>, /* controller interrupt */ | |
463 | <0 117 0x4>; /* PME interrupt */ | |
464 | interrupt-names = "intr", "pme"; | |
465 | #address-cells = <3>; | |
466 | #size-cells = <2>; | |
467 | device_type = "pci"; | |
468 | num-lanes = <4>; | |
469 | bus-range = <0x0 0xff>; | |
470 | ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
471 | 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
472 | msi-parent = <&msi1>; | |
473 | #interrupt-cells = <1>; | |
474 | interrupt-map-mask = <0 0 0 7>; | |
475 | interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, | |
476 | <0000 0 0 2 &gic 0 111 0x4>, | |
477 | <0000 0 0 3 &gic 0 112 0x4>, | |
478 | <0000 0 0 4 &gic 0 113 0x4>; | |
479 | }; | |
480 | ||
481 | pcie@3500000 { | |
482 | compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; | |
483 | reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ | |
484 | 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ | |
485 | reg-names = "regs", "config"; | |
486 | interrupts = <0 128 0x4>, | |
487 | <0 127 0x4>; | |
488 | interrupt-names = "intr", "pme"; | |
489 | #address-cells = <3>; | |
490 | #size-cells = <2>; | |
491 | device_type = "pci"; | |
492 | num-lanes = <2>; | |
493 | bus-range = <0x0 0xff>; | |
494 | ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
495 | 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
496 | msi-parent = <&msi2>; | |
497 | #interrupt-cells = <1>; | |
498 | interrupt-map-mask = <0 0 0 7>; | |
499 | interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, | |
500 | <0000 0 0 2 &gic 0 121 0x4>, | |
501 | <0000 0 0 3 &gic 0 122 0x4>, | |
502 | <0000 0 0 4 &gic 0 123 0x4>; | |
503 | }; | |
504 | ||
505 | pcie@3600000 { | |
506 | compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; | |
507 | reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ | |
508 | 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ | |
509 | reg-names = "regs", "config"; | |
510 | interrupts = <0 162 0x4>, | |
511 | <0 161 0x4>; | |
512 | interrupt-names = "intr", "pme"; | |
513 | #address-cells = <3>; | |
514 | #size-cells = <2>; | |
515 | device_type = "pci"; | |
516 | num-lanes = <2>; | |
517 | bus-range = <0x0 0xff>; | |
518 | ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
519 | 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
520 | msi-parent = <&msi3>; | |
521 | #interrupt-cells = <1>; | |
522 | interrupt-map-mask = <0 0 0 7>; | |
523 | interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, | |
524 | <0000 0 0 2 &gic 0 155 0x4>, | |
525 | <0000 0 0 3 &gic 0 156 0x4>, | |
526 | <0000 0 0 4 &gic 0 157 0x4>; | |
527 | }; | |
528 | }; | |
529 | ||
530 | }; |