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arm64: dts: hi6220: Add media subsystem reset dts
[deliverable/linux.git] / arch / arm64 / boot / dts / hisilicon / hi6220.dtsi
CommitLineData
86e8f528
BW		 1/*
2 * dts file for Hisilicon Hi6220 SoC
3 *
4 * Copyright (C) 2015, Hisilicon Ltd.
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
339d00cb 8#include <dt-bindings/reset/hisi,hi6220-resets.h>
a362ec8f 9#include <dt-bindings/clock/hi6220-clock.h>
379e9bf5 10#include <dt-bindings/pinctrl/hisi.h>
cd0b69ec 11#include <dt-bindings/thermal/thermal.h>
86e8f528
BW		 12
13/ {
14 compatible = "hisilicon,hi6220";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 psci {
20 compatible = "arm,psci-0.2";
21 method = "smc";
22 };
23
24 cpus {
25 #address-cells = <2>;
26 #size-cells = <0>;
27
28 cpu-map {
29 cluster0 {
30 core0 {
31 cpu = <&cpu0>;
32 };
33 core1 {
34 cpu = <&cpu1>;
35 };
36 core2 {
37 cpu = <&cpu2>;
38 };
39 core3 {
40 cpu = <&cpu3>;
41 };
42 };
43 cluster1 {
44 core0 {
45 cpu = <&cpu4>;
46 };
47 core1 {
48 cpu = <&cpu5>;
49 };
50 core2 {
51 cpu = <&cpu6>;
52 };
53 core3 {
54 cpu = <&cpu7>;
55 };
56 };
57 };
58
58fa29bf
LY		 59 idle-states {
60 entry-method = "psci";
61
62 CPU_SLEEP: cpu-sleep {
63 compatible = "arm,idle-state";
64 local-timer-stop;
65 arm,psci-suspend-param = <0x0010000>;
66 entry-latency-us = <700>;
67 exit-latency-us = <250>;
68 min-residency-us = <1000>;
69 };
70
71 CLUSTER_SLEEP: cluster-sleep {
72 compatible = "arm,idle-state";
73 local-timer-stop;
74 arm,psci-suspend-param = <0x1010000>;
75 entry-latency-us = <1000>;
76 exit-latency-us = <700>;
77 min-residency-us = <2700>;
78 wakeup-latency-us = <1500>;
79 };
80 };
81
86e8f528
BW		 82 cpu0: cpu@0 {
83 compatible = "arm,cortex-a53", "arm,armv8";
84 device_type = "cpu";
85 reg = <0x0 0x0>;
86 enable-method = "psci";
64851603 87 next-level-cache = <&CLUSTER0_L2>;
99860540
LY		 88 clocks = <&stub_clock 0>;
89 operating-points-v2 = <&cpu_opp_table>;
90 cooling-min-level = <4>;
91 cooling-max-level = <0>;
92 #cooling-cells = <2>; /* min followed by max */
58fa29bf 93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
cd0b69ec 94 dynamic-power-coefficient = <311>;
86e8f528
BW		 95 };
96
97 cpu1: cpu@1 {
98 compatible = "arm,cortex-a53", "arm,armv8";
99 device_type = "cpu";
100 reg = <0x0 0x1>;
101 enable-method = "psci";
64851603 102 next-level-cache = <&CLUSTER0_L2>;
99860540 103 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86e8f528
BW		 105 };
106
107 cpu2: cpu@2 {
108 compatible = "arm,cortex-a53", "arm,armv8";
109 device_type = "cpu";
110 reg = <0x0 0x2>;
111 enable-method = "psci";
64851603 112 next-level-cache = <&CLUSTER0_L2>;
99860540 113 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86e8f528
BW		 115 };
116
117 cpu3: cpu@3 {
118 compatible = "arm,cortex-a53", "arm,armv8";
119 device_type = "cpu";
120 reg = <0x0 0x3>;
121 enable-method = "psci";
64851603 122 next-level-cache = <&CLUSTER0_L2>;
99860540 123 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 124 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86e8f528
BW		 125 };
126
127 cpu4: cpu@100 {
128 compatible = "arm,cortex-a53", "arm,armv8";
129 device_type = "cpu";
130 reg = <0x0 0x100>;
131 enable-method = "psci";
64851603 132 next-level-cache = <&CLUSTER1_L2>;
99860540 133 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 134 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86e8f528
BW		 135 };
136
137 cpu5: cpu@101 {
138 compatible = "arm,cortex-a53", "arm,armv8";
139 device_type = "cpu";
140 reg = <0x0 0x101>;
141 enable-method = "psci";
64851603 142 next-level-cache = <&CLUSTER1_L2>;
99860540 143 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86e8f528
BW		 145 };
146
147 cpu6: cpu@102 {
148 compatible = "arm,cortex-a53", "arm,armv8";
149 device_type = "cpu";
150 reg = <0x0 0x102>;
151 enable-method = "psci";
64851603 152 next-level-cache = <&CLUSTER1_L2>;
99860540 153 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 154 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86e8f528
BW		 155 };
156
157 cpu7: cpu@103 {
158 compatible = "arm,cortex-a53", "arm,armv8";
159 device_type = "cpu";
160 reg = <0x0 0x103>;
161 enable-method = "psci";
64851603 162 next-level-cache = <&CLUSTER1_L2>;
99860540 163 operating-points-v2 = <&cpu_opp_table>;
58fa29bf 164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86e8f528 165 };
64851603
LY		 166
167 CLUSTER0_L2: l2-cache0 {
168 compatible = "cache";
169 };
170
171 CLUSTER1_L2: l2-cache1 {
172 compatible = "cache";
173 };
86e8f528
BW		 174 };
175
99860540
LY		 176 cpu_opp_table: cpu_opp_table {
177 compatible = "operating-points-v2";
178 opp-shared;
179
180 opp00 {
181 opp-hz = /bits/ 64 <208000000>;
182 opp-microvolt = <1040000>;
183 clock-latency-ns = <500000>;
184 };
185 opp01 {
186 opp-hz = /bits/ 64 <432000000>;
187 opp-microvolt = <1040000>;
188 clock-latency-ns = <500000>;
189 };
190 opp02 {
191 opp-hz = /bits/ 64 <729000000>;
192 opp-microvolt = <1090000>;
193 clock-latency-ns = <500000>;
194 };
195 opp03 {
196 opp-hz = /bits/ 64 <960000000>;
197 opp-microvolt = <1180000>;
198 clock-latency-ns = <500000>;
199 };
200 opp04 {
201 opp-hz = /bits/ 64 <1200000000>;
202 opp-microvolt = <1330000>;
203 clock-latency-ns = <500000>;
204 };
205 };
206
86e8f528
BW		 207 gic: interrupt-controller@f6801000 {
208 compatible = "arm,gic-400";
209 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
210 <0x0 0xf6802000 0 0x2000>, /* GICC */
211 <0x0 0xf6804000 0 0x2000>, /* GICH */
212 <0x0 0xf6806000 0 0x2000>; /* GICV */
213 #address-cells = <0>;
214 #interrupt-cells = <3>;
215 interrupt-controller;
216 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
217 };
218
219 timer {
220 compatible = "arm,armv8-timer";
221 interrupt-parent = <&gic>;
222 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
223 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
224 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
225 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
226 };
227
228 soc {
229 compatible = "simple-bus";
230 #address-cells = <2>;
231 #size-cells = <2>;
232 ranges;
233
99860540
LY		 234 sram: sram@fff80000 {
235 compatible = "hisilicon,hi6220-sramctrl", "syscon";
236 reg = <0x0 0xfff80000 0x0 0x12000>;
237 };
238
86e8f528
BW		 239 ao_ctrl: ao_ctrl@f7800000 {
240 compatible = "hisilicon,hi6220-aoctrl", "syscon";
241 reg = <0x0 0xf7800000 0x0 0x2000>;
242 #clock-cells = <1>;
243 };
244
245 sys_ctrl: sys_ctrl@f7030000 {
246 compatible = "hisilicon,hi6220-sysctrl", "syscon";
247 reg = <0x0 0xf7030000 0x0 0x2000>;
248 #clock-cells = <1>;
3e14cd4c 249 #reset-cells = <1>;
86e8f528
BW		 250 };
251
252 media_ctrl: media_ctrl@f4410000 {
253 compatible = "hisilicon,hi6220-mediactrl", "syscon";
254 reg = <0x0 0xf4410000 0x0 0x1000>;
255 #clock-cells = <1>;
339d00cb 256 #reset-cells = <1>;
86e8f528
BW		 257 };
258
259 pm_ctrl: pm_ctrl@f7032000 {
260 compatible = "hisilicon,hi6220-pmctrl", "syscon";
261 reg = <0x0 0xf7032000 0x0 0x1000>;
262 #clock-cells = <1>;
263 };
264
99860540
LY		 265 stub_clock: stub_clock {
266 compatible = "hisilicon,hi6220-stub-clk";
267 hisilicon,hi6220-clk-sram = <&sram>;
268 #clock-cells = <1>;
269 mbox-names = "mbox-tx";
270 mboxes = <&mailbox 1 0 11>;
271 };
272
86e8f528
BW		 273 uart0: uart@f8015000 { /* console */
274 compatible = "arm,pl011", "arm,primecell";
275 reg = <0x0 0xf8015000 0x0 0x1000>;
276 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
a362ec8f
TB		 277 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
278 <&ao_ctrl HI6220_UART0_PCLK>;
86e8f528
BW		 279 clock-names = "uartclk", "apb_pclk";
280 };
a362ec8f
TB		 281
282 uart1: uart@f7111000 {
283 compatible = "arm,pl011", "arm,primecell";
284 reg = <0x0 0xf7111000 0x0 0x1000>;
285 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
287 <&sys_ctrl HI6220_UART1_PCLK>;
288 clock-names = "uartclk", "apb_pclk";
c2aad932
GX		 289 pinctrl-names = "default";
290 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
a362ec8f
TB		 291 status = "disabled";
292 };
293
294 uart2: uart@f7112000 {
295 compatible = "arm,pl011", "arm,primecell";
296 reg = <0x0 0xf7112000 0x0 0x1000>;
297 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
299 <&sys_ctrl HI6220_UART2_PCLK>;
300 clock-names = "uartclk", "apb_pclk";
c2aad932
GX		 301 pinctrl-names = "default";
302 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
a362ec8f
TB		 303 status = "disabled";
304 };
305
306 uart3: uart@f7113000 {
307 compatible = "arm,pl011", "arm,primecell";
308 reg = <0x0 0xf7113000 0x0 0x1000>;
309 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
311 <&sys_ctrl HI6220_UART3_PCLK>;
312 clock-names = "uartclk", "apb_pclk";
c2aad932
GX		 313 pinctrl-names = "default";
314 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
315 status = "disabled";
a362ec8f
TB		 316 };
317
318 uart4: uart@f7114000 {
319 compatible = "arm,pl011", "arm,primecell";
320 reg = <0x0 0xf7114000 0x0 0x1000>;
321 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
323 <&sys_ctrl HI6220_UART4_PCLK>;
324 clock-names = "uartclk", "apb_pclk";
c2aad932
GX		 325 pinctrl-names = "default";
326 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
a362ec8f
TB		 327 status = "disabled";
328 };
9e927031
LY		 329
330 dual_timer0: timer@f8008000 {
331 compatible = "arm,sp804", "arm,primecell";
332 reg = <0x0 0xf8008000 0x0 0x1000>;
333 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
336 <&ao_ctrl HI6220_TIMER0_PCLK>,
337 <&ao_ctrl HI6220_TIMER0_PCLK>;
338 clock-names = "timer1", "timer2", "apb_pclk";
339 };
f2bfacf9 340
379e9bf5
ZK		 341 pmx0: pinmux@f7010000 {
342 compatible = "pinctrl-single";
343 reg = <0x0 0xf7010000 0x0 0x27c>;
344 #address-cells = <1>;
345 #size-cells = <1>;
346 #gpio-range-cells = <3>;
347 pinctrl-single,register-width = <32>;
348 pinctrl-single,function-mask = <7>;
349 pinctrl-single,gpio-range = <
350 &range 80 8 MUX_M0 /* gpio 3: [0..7] */
351 &range 88 8 MUX_M0 /* gpio 4: [0..7] */
352 &range 96 8 MUX_M0 /* gpio 5: [0..7] */
353 &range 104 8 MUX_M0 /* gpio 6: [0..7] */
354 &range 112 8 MUX_M0 /* gpio 7: [0..7] */
355 &range 120 2 MUX_M0 /* gpio 8: [0..1] */
356 &range 2 6 MUX_M1 /* gpio 8: [2..7] */
357 &range 8 8 MUX_M1 /* gpio 9: [0..7] */
358 &range 0 1 MUX_M1 /* gpio 10: [0] */
359 &range 16 7 MUX_M1 /* gpio 10: [1..7] */
360 &range 23 3 MUX_M1 /* gpio 11: [0..2] */
361 &range 28 5 MUX_M1 /* gpio 11: [3..7] */
362 &range 33 3 MUX_M1 /* gpio 12: [0..2] */
363 &range 43 5 MUX_M1 /* gpio 12: [3..7] */
364 &range 48 8 MUX_M1 /* gpio 13: [0..7] */
365 &range 56 8 MUX_M1 /* gpio 14: [0..7] */
366 &range 74 6 MUX_M1 /* gpio 15: [0..5] */
367 &range 122 1 MUX_M1 /* gpio 15: [6] */
368 &range 126 1 MUX_M1 /* gpio 15: [7] */
369 &range 127 8 MUX_M1 /* gpio 16: [0..7] */
370 &range 135 8 MUX_M1 /* gpio 17: [0..7] */
371 &range 143 8 MUX_M1 /* gpio 18: [0..7] */
372 &range 151 8 MUX_M1 /* gpio 19: [0..7] */
373 >;
374 range: gpio-range {
375 #pinctrl-single,gpio-range-cells = <3>;
376 };
377 };
378
379 pmx1: pinmux@f7010800 {
380 compatible = "pinconf-single";
381 reg = <0x0 0xf7010800 0x0 0x28c>;
382 #address-cells = <1>;
383 #size-cells = <1>;
384 pinctrl-single,register-width = <32>;
385 };
386
387 pmx2: pinmux@f8001800 {
388 compatible = "pinconf-single";
389 reg = <0x0 0xf8001800 0x0 0x78>;
390 #address-cells = <1>;
391 #size-cells = <1>;
392 pinctrl-single,register-width = <32>;
393 };
394
f2bfacf9
ZK		 395 gpio0: gpio@f8011000 {
396 compatible = "arm,pl061", "arm,primecell";
397 reg = <0x0 0xf8011000 0x0 0x1000>;
398 interrupts = <0 52 0x4>;
399 gpio-controller;
400 #gpio-cells = <2>;
401 interrupt-controller;
402 #interrupt-cells = <2>;
403 clocks = <&ao_ctrl 2>;
404 clock-names = "apb_pclk";
405 };
406
407 gpio1: gpio@f8012000 {
408 compatible = "arm,pl061", "arm,primecell";
409 reg = <0x0 0xf8012000 0x0 0x1000>;
410 interrupts = <0 53 0x4>;
411 gpio-controller;
412 #gpio-cells = <2>;
413 interrupt-controller;
414 #interrupt-cells = <2>;
415 clocks = <&ao_ctrl 2>;
416 clock-names = "apb_pclk";
417 };
418
419 gpio2: gpio@f8013000 {
420 compatible = "arm,pl061", "arm,primecell";
421 reg = <0x0 0xf8013000 0x0 0x1000>;
422 interrupts = <0 54 0x4>;
423 gpio-controller;
424 #gpio-cells = <2>;
425 interrupt-controller;
426 #interrupt-cells = <2>;
427 clocks = <&ao_ctrl 2>;
428 clock-names = "apb_pclk";
429 };
430
431 gpio3: gpio@f8014000 {
432 compatible = "arm,pl061", "arm,primecell";
433 reg = <0x0 0xf8014000 0x0 0x1000>;
434 interrupts = <0 55 0x4>;
435 gpio-controller;
436 #gpio-cells = <2>;
379e9bf5 437 gpio-ranges = <&pmx0 0 80 8>;
f2bfacf9
ZK		 438 interrupt-controller;
439 #interrupt-cells = <2>;
440 clocks = <&ao_ctrl 2>;
441 clock-names = "apb_pclk";
442 };
443
444 gpio4: gpio@f7020000 {
445 compatible = "arm,pl061", "arm,primecell";
446 reg = <0x0 0xf7020000 0x0 0x1000>;
447 interrupts = <0 56 0x4>;
448 gpio-controller;
449 #gpio-cells = <2>;
379e9bf5 450 gpio-ranges = <&pmx0 0 88 8>;
f2bfacf9
ZK		 451 interrupt-controller;
452 #interrupt-cells = <2>;
453 clocks = <&ao_ctrl 2>;
454 clock-names = "apb_pclk";
455 };
456
457 gpio5: gpio@f7021000 {
458 compatible = "arm,pl061", "arm,primecell";
459 reg = <0x0 0xf7021000 0x0 0x1000>;
460 interrupts = <0 57 0x4>;
461 gpio-controller;
462 #gpio-cells = <2>;
379e9bf5 463 gpio-ranges = <&pmx0 0 96 8>;
f2bfacf9
ZK		 464 interrupt-controller;
465 #interrupt-cells = <2>;
466 clocks = <&ao_ctrl 2>;
467 clock-names = "apb_pclk";
468 };
469
470 gpio6: gpio@f7022000 {
471 compatible = "arm,pl061", "arm,primecell";
472 reg = <0x0 0xf7022000 0x0 0x1000>;
473 interrupts = <0 58 0x4>;
474 gpio-controller;
475 #gpio-cells = <2>;
379e9bf5 476 gpio-ranges = <&pmx0 0 104 8>;
f2bfacf9
ZK		 477 interrupt-controller;
478 #interrupt-cells = <2>;
479 clocks = <&ao_ctrl 2>;
480 clock-names = "apb_pclk";
481 };
482
483 gpio7: gpio@f7023000 {
484 compatible = "arm,pl061", "arm,primecell";
485 reg = <0x0 0xf7023000 0x0 0x1000>;
486 interrupts = <0 59 0x4>;
487 gpio-controller;
488 #gpio-cells = <2>;
379e9bf5 489 gpio-ranges = <&pmx0 0 112 8>;
f2bfacf9
ZK		 490 interrupt-controller;
491 #interrupt-cells = <2>;
492 clocks = <&ao_ctrl 2>;
493 clock-names = "apb_pclk";
494 };
495
496 gpio8: gpio@f7024000 {
497 compatible = "arm,pl061", "arm,primecell";
498 reg = <0x0 0xf7024000 0x0 0x1000>;
499 interrupts = <0 60 0x4>;
500 gpio-controller;
501 #gpio-cells = <2>;
379e9bf5 502 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
f2bfacf9
ZK		 503 interrupt-controller;
504 #interrupt-cells = <2>;
505 clocks = <&ao_ctrl 2>;
506 clock-names = "apb_pclk";
507 };
508
509 gpio9: gpio@f7025000 {
510 compatible = "arm,pl061", "arm,primecell";
511 reg = <0x0 0xf7025000 0x0 0x1000>;
512 interrupts = <0 61 0x4>;
513 gpio-controller;
514 #gpio-cells = <2>;
379e9bf5 515 gpio-ranges = <&pmx0 0 8 8>;
f2bfacf9
ZK		 516 interrupt-controller;
517 #interrupt-cells = <2>;
518 clocks = <&ao_ctrl 2>;
519 clock-names = "apb_pclk";
520 };
521
522 gpio10: gpio@f7026000 {
523 compatible = "arm,pl061", "arm,primecell";
524 reg = <0x0 0xf7026000 0x0 0x1000>;
525 interrupts = <0 62 0x4>;
526 gpio-controller;
527 #gpio-cells = <2>;
379e9bf5 528 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
f2bfacf9
ZK		 529 interrupt-controller;
530 #interrupt-cells = <2>;
531 clocks = <&ao_ctrl 2>;
532 clock-names = "apb_pclk";
533 };
534
535 gpio11: gpio@f7027000 {
536 compatible = "arm,pl061", "arm,primecell";
537 reg = <0x0 0xf7027000 0x0 0x1000>;
538 interrupts = <0 63 0x4>;
539 gpio-controller;
540 #gpio-cells = <2>;
379e9bf5 541 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
f2bfacf9
ZK		 542 interrupt-controller;
543 #interrupt-cells = <2>;
544 clocks = <&ao_ctrl 2>;
545 clock-names = "apb_pclk";
546 };
547
548 gpio12: gpio@f7028000 {
549 compatible = "arm,pl061", "arm,primecell";
550 reg = <0x0 0xf7028000 0x0 0x1000>;
551 interrupts = <0 64 0x4>;
552 gpio-controller;
553 #gpio-cells = <2>;
379e9bf5 554 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
f2bfacf9
ZK		 555 interrupt-controller;
556 #interrupt-cells = <2>;
557 clocks = <&ao_ctrl 2>;
558 clock-names = "apb_pclk";
559 };
560
561 gpio13: gpio@f7029000 {
562 compatible = "arm,pl061", "arm,primecell";
563 reg = <0x0 0xf7029000 0x0 0x1000>;
564 interrupts = <0 65 0x4>;
565 gpio-controller;
379e9bf5
ZK		 566 #gpio-cells = <2>;
567 gpio-ranges = <&pmx0 0 48 8>;
f2bfacf9
ZK		 568 interrupt-controller;
569 #interrupt-cells = <2>;
570 clocks = <&ao_ctrl 2>;
571 clock-names = "apb_pclk";
572 };
573
574 gpio14: gpio@f702a000 {
575 compatible = "arm,pl061", "arm,primecell";
576 reg = <0x0 0xf702a000 0x0 0x1000>;
577 interrupts = <0 66 0x4>;
578 gpio-controller;
579 #gpio-cells = <2>;
379e9bf5 580 gpio-ranges = <&pmx0 0 56 8>;
f2bfacf9
ZK		 581 interrupt-controller;
582 #interrupt-cells = <2>;
583 clocks = <&ao_ctrl 2>;
584 clock-names = "apb_pclk";
585 };
586
587 gpio15: gpio@f702b000 {
588 compatible = "arm,pl061", "arm,primecell";
589 reg = <0x0 0xf702b000 0x0 0x1000>;
590 interrupts = <0 67 0x4>;
591 gpio-controller;
592 #gpio-cells = <2>;
379e9bf5
ZK		 593 gpio-ranges = <
594 &pmx0 0 74 6
595 &pmx0 6 122 1
596 &pmx0 7 126 1
597 >;
f2bfacf9
ZK		 598 interrupt-controller;
599 #interrupt-cells = <2>;
600 clocks = <&ao_ctrl 2>;
601 clock-names = "apb_pclk";
602 };
603
604 gpio16: gpio@f702c000 {
605 compatible = "arm,pl061", "arm,primecell";
606 reg = <0x0 0xf702c000 0x0 0x1000>;
607 interrupts = <0 68 0x4>;
608 gpio-controller;
609 #gpio-cells = <2>;
379e9bf5 610 gpio-ranges = <&pmx0 0 127 8>;
f2bfacf9
ZK		 611 interrupt-controller;
612 #interrupt-cells = <2>;
613 clocks = <&ao_ctrl 2>;
614 clock-names = "apb_pclk";
615 };
616
617 gpio17: gpio@f702d000 {
618 compatible = "arm,pl061", "arm,primecell";
619 reg = <0x0 0xf702d000 0x0 0x1000>;
620 interrupts = <0 69 0x4>;
621 gpio-controller;
622 #gpio-cells = <2>;
379e9bf5 623 gpio-ranges = <&pmx0 0 135 8>;
f2bfacf9
ZK		 624 interrupt-controller;
625 #interrupt-cells = <2>;
626 clocks = <&ao_ctrl 2>;
627 clock-names = "apb_pclk";
628 };
629
630 gpio18: gpio@f702e000 {
631 compatible = "arm,pl061", "arm,primecell";
632 reg = <0x0 0xf702e000 0x0 0x1000>;
633 interrupts = <0 70 0x4>;
634 gpio-controller;
635 #gpio-cells = <2>;
379e9bf5 636 gpio-ranges = <&pmx0 0 143 8>;
f2bfacf9
ZK		 637 interrupt-controller;
638 #interrupt-cells = <2>;
639 clocks = <&ao_ctrl 2>;
640 clock-names = "apb_pclk";
641 };
642
643 gpio19: gpio@f702f000 {
644 compatible = "arm,pl061", "arm,primecell";
645 reg = <0x0 0xf702f000 0x0 0x1000>;
646 interrupts = <0 71 0x4>;
647 gpio-controller;
648 #gpio-cells = <2>;
379e9bf5 649 gpio-ranges = <&pmx0 0 151 8>;
f2bfacf9
ZK		 650 interrupt-controller;
651 #interrupt-cells = <2>;
652 clocks = <&ao_ctrl 2>;
653 clock-names = "apb_pclk";
654 };
60dac1b1
ZK		 655
656 spi0: spi@f7106000 {
657 compatible = "arm,pl022", "arm,primecell";
658 reg = <0x0 0xf7106000 0x0 0x1000>;
659 interrupts = <0 50 4>;
660 bus-id = <0>;
661 enable-dma = <0>;
662 clocks = <&sys_ctrl HI6220_SPI_CLK>;
663 clock-names = "apb_pclk";
664 pinctrl-names = "default";
665 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
666 num-cs = <1>;
667 cs-gpios = <&gpio6 2 0>;
668 status = "disabled";
669 };
5ff3a4dd
XK		 670
671 i2c0: i2c@f7100000 {
672 compatible = "snps,designware-i2c";
673 reg = <0x0 0xf7100000 0x0 0x1000>;
674 interrupts = <0 44 4>;
675 clocks = <&sys_ctrl HI6220_I2C0_CLK>;
676 i2c-sda-hold-time-ns = <300>;
677 pinctrl-names = "default";
678 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
679 status = "disabled";
680 };
681
682 i2c1: i2c@f7101000 {
683 compatible = "snps,designware-i2c";
684 reg = <0x0 0xf7101000 0x0 0x1000>;
685 clocks = <&sys_ctrl HI6220_I2C1_CLK>;
686 interrupts = <0 45 4>;
687 i2c-sda-hold-time-ns = <300>;
688 pinctrl-names = "default";
689 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
690 status = "disabled";
691 };
692
693 i2c2: i2c@f7102000 {
694 compatible = "snps,designware-i2c";
695 reg = <0x0 0xf7102000 0x0 0x1000>;
696 clocks = <&sys_ctrl HI6220_I2C2_CLK>;
697 interrupts = <0 46 4>;
698 i2c-sda-hold-time-ns = <300>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
701 status = "disabled";
702 };
b4b31a7c
ZG		 703
704 fixed_5v_hub: regulator@0 {
705 compatible = "regulator-fixed";
706 regulator-name = "fixed_5v_hub";
707 regulator-min-microvolt = <5000000>;
708 regulator-max-microvolt = <5000000>;
709 regulator-boot-on;
710 gpio = <&gpio0 7 0>;
711 regulator-always-on;
712 };
713
714 usb_phy: usbphy {
715 compatible = "hisilicon,hi6220-usb-phy";
716 #phy-cells = <0>;
717 phy-supply = <&fixed_5v_hub>;
718 hisilicon,peripheral-syscon = <&sys_ctrl>;
719 };
720
721 usb: usb@f72c0000 {
722 compatible = "hisilicon,hi6220-usb";
723 reg = <0x0 0xf72c0000 0x0 0x40000>;
724 phys = <&usb_phy>;
725 phy-names = "usb2-phy";
726 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
727 clock-names = "otg";
728 dr_mode = "otg";
729 g-use-dma;
730 g-rx-fifo-size = <512>;
731 g-np-tx-fifo-size = <128>;
732 g-tx-fifo-size = <128 128 128 128 128 128>;
733 interrupts = <0 77 0x4>;
734 };
86073570
LY		 735
736 mailbox: mailbox@f7510000 {
737 compatible = "hisilicon,hi6220-mbox";
738 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
739 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
740 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
741 #mbox-cells = <3>;
742 };
d6b259d4
XK		 743
744 dwmmc_0: dwmmc0@f723d000 {
745 compatible = "hisilicon,hi6220-dw-mshc";
746 num-slots = <0x1>;
747 cap-mmc-highspeed;
748 non-removable;
749 reg = <0x0 0xf723d000 0x0 0x1000>;
750 interrupts = <0x0 0x48 0x4>;
751 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
752 clock-names = "ciu", "biu";
753 bus-width = <0x8>;
754 vmmc-supply = <&ldo19>;
755 pinctrl-names = "default";
756 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
757 &emmc_cfg_func &emmc_rst_cfg_func>;
758 };
759
760 dwmmc_1: dwmmc1@f723e000 {
761 compatible = "hisilicon,hi6220-dw-mshc";
762 num-slots = <0x1>;
763 card-detect-delay = <200>;
764 hisilicon,peripheral-syscon = <&ao_ctrl>;
765 cap-sd-highspeed;
766 reg = <0x0 0xf723e000 0x0 0x1000>;
767 interrupts = <0x0 0x49 0x4>;
768 #address-cells = <0x1>;
769 #size-cells = <0x0>;
770 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
771 clock-names = "ciu", "biu";
772 vqmmc-supply = <&ldo7>;
773 vmmc-supply = <&ldo10>;
774 bus-width = <0x4>;
775 disable-wp;
776 cd-gpios = <&gpio1 0 1>;
777 pinctrl-names = "default", "idle";
778 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
779 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
780 };
781
782 dwmmc_2: dwmmc2@f723f000 {
783 compatible = "hisilicon,hi6220-dw-mshc";
784 num-slots = <0x1>;
785 reg = <0x0 0xf723f000 0x0 0x1000>;
786 interrupts = <0x0 0x4a 0x4>;
787 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
788 clock-names = "ciu", "biu";
789 bus-width = <0x4>;
790 broken-cd;
791 pinctrl-names = "default", "idle";
792 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
793 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
794 };
2158ab08
LY		 795
796 tsensor: tsensor@0,f7030700 {
797 compatible = "hisilicon,tsensor";
798 reg = <0x0 0xf7030700 0x0 0x1000>;
799 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&sys_ctrl 22>;
801 clock-names = "thermal_clk";
802 #thermal-sensor-cells = <1>;
803 };
cd0b69ec
LY		 804
805 thermal-zones {
806
807 cls0: cls0 {
808 polling-delay = <1000>;
809 polling-delay-passive = <100>;
810 sustainable-power = <3326>;
811
812 /* sensor ID */
813 thermal-sensors = <&tsensor 2>;
814
815 trips {
816 threshold: trip-point@0 {
817 temperature = <65000>;
818 hysteresis = <0>;
819 type = "passive";
820 };
821
822 target: trip-point@1 {
823 temperature = <75000>;
824 hysteresis = <0>;
825 type = "passive";
826 };
827 };
828
829 cooling-maps {
830 map0 {
831 trip = <&target>;
832 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
833 };
834 };
835 };
836 };
86e8f528
BW		 837 };
838};
Linux kernel - Deliverables
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