arm64: dts: marvell: Rename armada-37xx USB node
[deliverable/linux.git] / arch / arm64 / boot / dts / marvell / armada-37xx.dtsi
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1/*
2 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
3 *
4 * Copyright (C) 2016 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47#include <dt-bindings/interrupt-controller/arm-gic.h>
48
49/ {
50 model = "Marvell Armada 37xx SoC";
51 compatible = "marvell,armada3700";
52 interrupt-parent = <&gic>;
53 #address-cells = <2>;
54 #size-cells = <2>;
55
56 aliases {
57 serial0 = &uart0;
58 };
59
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 cpu@0 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a53", "arm,armv8";
66 reg = <0>;
67 enable-method = "psci";
68 };
69 };
70
71 psci {
72 compatible = "arm,psci-0.2";
73 method = "smc";
74 };
75
76 timer {
77 compatible = "arm,armv8-timer";
78 interrupts = <GIC_PPI 13
79 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
80 <GIC_PPI 14
81 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
82 <GIC_PPI 11
83 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
84 <GIC_PPI 10
85 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
86 };
87
88 soc {
89 compatible = "simple-bus";
90 #address-cells = <2>;
91 #size-cells = <2>;
92 ranges;
93
94 internal-regs {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 compatible = "simple-bus";
98 /* 32M internal register @ 0xd000_0000 */
99 ranges = <0x0 0x0 0xd0000000 0x2000000>;
100
101 uart0: serial@12000 {
102 compatible = "marvell,armada-3700-uart";
103 reg = <0x12000 0x400>;
104 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
105 status = "disabled";
106 };
107
cc2684c4 108 usb3: usb@58000 {
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109 compatible = "generic-xhci";
110 reg = <0x58000 0x4000>;
111 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
112 status = "disabled";
113 };
114
7b01cff5 115 sata: sata@e0000 {
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116 compatible = "marvell,armada-3700-ahci";
117 reg = <0xe0000 0x2000>;
118 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
119 status = "disabled";
120 };
121
122 gic: interrupt-controller@1d00000 {
123 compatible = "arm,gic-v3";
124 #interrupt-cells = <3>;
125 interrupt-controller;
126 reg = <0x1d00000 0x10000>, /* GICD */
127 <0x1d40000 0x40000>; /* GICR */
128 };
129 };
130 };
131};
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