[deliverable/linux.git] / arch / arm64 / boot / dts / marvell / armada-37xx.dtsi

/*
 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
 *
 * Copyright (C) 2016 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 37xx SoC";
	compatible = "marvell,armada3700";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		internal-regs {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			/* 32M internal register @ 0xd000_0000 */
			ranges = <0x0 0x0 0xd0000000 0x2000000>;

			uart0: serial@12000 {
				compatible = "marvell,armada-3700-uart";
				reg = <0x12000 0x400>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			nb_perih_clk: nb-periph-clk@13000{
				compatible = "marvell,armada-3700-periph-clock-nb";
				reg = <0x13000 0x100>;
				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
				<&tbg 3>, <&xtalclk>;
				#clock-cells = <1>;
			};

			sb_perih_clk: sb-periph-clk@18000{
				compatible = "marvell,armada-3700-periph-clock-sb";
				reg = <0x18000 0x100>;
				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
				<&tbg 3>, <&xtalclk>;
				#clock-cells = <1>;
			};

			tbg: tbg@13200 {
				compatible = "marvell,armada-3700-tbg-clock";
				reg = <0x13200 0x100>;
				clocks = <&xtalclk>;
				#clock-cells = <1>;
			};

			gpio1: gpio@13800 {
				compatible = "marvell,mvebu-gpio-3700",
				"syscon", "simple-mfd";
				reg = <0x13800 0x500>;

				xtalclk: xtal-clk {
					compatible = "marvell,armada-3700-xtal-clock";
					clock-output-names = "xtal";
					#clock-cells = <0>;
				};
			};

			usb3: usb@58000 {
				compatible = "marvell,armada3700-xhci",
				"generic-xhci";
				reg = <0x58000 0x4000>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			xor@60900 {
				compatible = "marvell,armada-3700-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;

				xor10 {
					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				};
				xor11 {
					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			sata: sata@e0000 {
				compatible = "marvell,armada-3700-ahci";
				reg = <0xe0000 0x2000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			gic: interrupt-controller@1d00000 {
				compatible = "arm,gic-v3";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0x1d00000 0x10000>, /* GICD */
				      <0x1d40000 0x40000>; /* GICR */
			};
		};

		pcie0: pcie@d0070000 {
			compatible = "marvell,armada-3700-pcie";
			device_type = "pci";
			status = "disabled";
			reg = <0 0xd0070000 0 0x20000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0x00 0xff>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <1>;
			msi-parent = <&pcie0>;
			msi-controller;
			ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */
				  0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc 0>,
					<0 0 0 2 &pcie_intc 1>,
					<0 0 0 3 &pcie_intc 2>,
					<0 0 0 4 &pcie_intc 3>;
			pcie_intc: interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};
	};
};
Commit	Line	Data
adbc3695 GC	1	/*
	2	* Device Tree Include file for Marvell Armada 37xx family of SoCs.
	3	*
	4	* Copyright (C) 2016 Marvell
	5	*
	6	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	7	*
	8	* This file is dual-licensed: you can use it either under the terms
	9	* of the GPL or the X11 license, at your option. Note that this dual
	10	* licensing only applies to this file, and not this project as a
	11	* whole.
	12	*
	13	* a) This file is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of the
	16	* License, or (at your option) any later version.
	17	*
	18	* This file is distributed in the hope that it will be useful
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* Or, alternatively
	24	*
	25	* b) Permission is hereby granted, free of charge, to any person
	26	* obtaining a copy of this software and associated documentation
	27	* files (the "Software"), to deal in the Software without
	28	* restriction, including without limitation the rights to use
	29	* copy, modify, merge, publish, distribute, sublicense, and/or
	30	* sell copies of the Software, and to permit persons to whom the
	31	* Software is furnished to do so, subject to the following
	32	* conditions:
	33	*
	34	* The above copyright notice and this permission notice shall be
	35	* included in all copies or substantial portions of the Software.
	36	*
	37	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	38	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	39	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	40	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	41	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	42	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	43	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	44	* OTHER DEALINGS IN THE SOFTWARE.
	45	*/
	46
	47	#include <dt-bindings/interrupt-controller/arm-gic.h>
	48
	49	/ {
	50	model = "Marvell Armada 37xx SoC";
	51	compatible = "marvell,armada3700";
	52	interrupt-parent = <&gic>;
	53	#address-cells = <2>;
	54	#size-cells = <2>;
	55
	56	aliases {
	57	serial0 = &uart0;
	58	};
	59
	60	cpus {
	61	#address-cells = <1>;
	62	#size-cells = <0>;
	63	cpu@0 {
	64	device_type = "cpu";
65	compatible = "arm,cortex-a53", "arm,armv8";
66	reg = <0>;
67	enable-method = "psci";
68	};
69	};
70
71	psci {
72	compatible = "arm,psci-0.2";
73	method = "smc";
74	};
75
76	timer {
77	compatible = "arm,armv8-timer";
78	interrupts = <GIC_PPI 13
79	(GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>,
80	<GIC_PPI 14
81	(GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>,
82	<GIC_PPI 11
83	(GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>,
84	<GIC_PPI 10
85	(GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
86	};
87
88	soc {
89	compatible = "simple-bus";
90	#address-cells = <2>;
91	#size-cells = <2>;
92	ranges;
93
94	internal-regs {
95	#address-cells = <1>;
96	#size-cells = <1>;
97	compatible = "simple-bus";
98	/* 32M internal register @ 0xd000_0000 */
99	ranges = <0x0 0x0 0xd0000000 0x2000000>;
100
101	uart0: serial@12000 {
102	compatible = "marvell,armada-3700-uart";
103	reg = <0x12000 0x400>;
104	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
105	status = "disabled";
106	};
107
5f4beef6 GC	108	nb_perih_clk: nb-periph-clk@13000{
	109	compatible = "marvell,armada-3700-periph-clock-nb";
	110	reg = <0x13000 0x100>;
	111	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
	112	<&tbg 3>, <&xtalclk>;
	113	#clock-cells = <1>;
	114	};
	115
	116	sb_perih_clk: sb-periph-clk@18000{
	117	compatible = "marvell,armada-3700-periph-clock-sb";
	118	reg = <0x18000 0x100>;
	119	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
	120	<&tbg 3>, <&xtalclk>;
	121	#clock-cells = <1>;
	122	};
	123
e3e1a55e GC	124	tbg: tbg@13200 {
	125	compatible = "marvell,armada-3700-tbg-clock";
	126	reg = <0x13200 0x100>;
	127	clocks = <&xtalclk>;
	128	#clock-cells = <1>;
	129	};
	130
ddeba40b GC	131	gpio1: gpio@13800 {
	132	compatible = "marvell,mvebu-gpio-3700",
	133	"syscon", "simple-mfd";
	134	reg = <0x13800 0x500>;
	135
	136	xtalclk: xtal-clk {
	137	compatible = "marvell,armada-3700-xtal-clock";
	138	clock-output-names = "xtal";
	139	#clock-cells = <0>;
	140	};
	141	};
	142
cc2684c4	143	usb3: usb@58000 {
150fa112 GC	144	compatible = "marvell,armada3700-xhci",
150fa112 GC	145	"generic-xhci";
adbc3695 GC	146	reg = <0x58000 0x4000>;
	147	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	148	status = "disabled";
	149	};
	150
19b67d5c GC	151	xor@60900 {
	152	compatible = "marvell,armada-3700-xor";
	153	reg = <0x60900 0x100
	154	0x60b00 0x100>;
	155
	156	xor10 {
	157	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	158	};
	159	xor11 {
	160	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	161	};
	162	};
	163
7b01cff5	164	sata: sata@e0000 {
adbc3695 GC	165	compatible = "marvell,armada-3700-ahci";
	166	reg = <0xe0000 0x2000>;
	167	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	168	status = "disabled";
	169	};
	170
	171	gic: interrupt-controller@1d00000 {
	172	compatible = "arm,gic-v3";
	173	#interrupt-cells = <3>;
	174	interrupt-controller;
	175	reg = <0x1d00000 0x10000>, /* GICD */
	176	<0x1d40000 0x40000>; /* GICR */
	177	};
	178	};
76f6386b TP	179
	180	pcie0: pcie@d0070000 {
	181	compatible = "marvell,armada-3700-pcie";
	182	device_type = "pci";
	183	status = "disabled";
	184	reg = <0 0xd0070000 0 0x20000>;
	185	#address-cells = <3>;
	186	#size-cells = <2>;
	187	bus-range = <0x00 0xff>;
	188	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	189	#interrupt-cells = <1>;
	190	msi-parent = <&pcie0>;
	191	msi-controller;
	192	ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
	193	0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
	194	interrupt-map-mask = <0 0 0 7>;
	195	interrupt-map = <0 0 0 1 &pcie_intc 0>,
	196	<0 0 0 2 &pcie_intc 1>,
	197	<0 0 0 3 &pcie_intc 2>,
	198	<0 0 0 4 &pcie_intc 3>;
	199	pcie_intc: interrupt-controller {
	200	interrupt-controller;
	201	#interrupt-cells = <1>;
	202	};
	203	};
adbc3695 GC	204	};
adbc3695 GC	205	};