Commit | Line | Data |
---|---|---|
0e91ba42 LD |
1 | #include <dt-bindings/input/input.h> |
2 | ||
2e634057 TR |
3 | / { |
4 | model = "NVIDIA Tegra210 P2597 I/O board"; | |
5 | compatible = "nvidia,p2597", "nvidia,tegra210"; | |
6 | ||
34993594 TR |
7 | host1x@50000000 { |
8 | dpaux@54040000 { | |
9 | status = "okay"; | |
10 | }; | |
11 | ||
12 | sor@54580000 { | |
13 | status = "okay"; | |
14 | ||
15 | avdd-io-supply = <&avdd_1v05>; | |
16 | vdd-pll-supply = <&vdd_1v8>; | |
17 | hdmi-supply = <&vdd_hdmi>; | |
18 | ||
19 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
20 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) | |
21 | GPIO_ACTIVE_LOW>; | |
22 | }; | |
23 | }; | |
24 | ||
be70771d | 25 | pinmux: pinmux@700008d4 { |
2e634057 TR |
26 | pinctrl-names = "boot"; |
27 | pinctrl-0 = <&state_boot>; | |
28 | ||
29 | state_boot: pinmux { | |
30 | pex_l0_rst_n_pa0 { | |
31 | nvidia,pins = "pex_l0_rst_n_pa0"; | |
32 | nvidia,function = "pe0"; | |
33 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
34 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
35 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
36 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
37 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; | |
38 | }; | |
39 | pex_l0_clkreq_n_pa1 { | |
40 | nvidia,pins = "pex_l0_clkreq_n_pa1"; | |
41 | nvidia,function = "pe0"; | |
42 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
43 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
44 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
45 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
46 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; | |
47 | }; | |
48 | pex_wake_n_pa2 { | |
49 | nvidia,pins = "pex_wake_n_pa2"; | |
50 | nvidia,function = "pe"; | |
51 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
52 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
53 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
54 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
55 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; | |
56 | }; | |
57 | pex_l1_rst_n_pa3 { | |
58 | nvidia,pins = "pex_l1_rst_n_pa3"; | |
59 | nvidia,function = "pe1"; | |
60 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
61 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
62 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
63 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
64 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; | |
65 | }; | |
66 | pex_l1_clkreq_n_pa4 { | |
67 | nvidia,pins = "pex_l1_clkreq_n_pa4"; | |
68 | nvidia,function = "pe1"; | |
69 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
70 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
71 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
72 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
73 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; | |
74 | }; | |
75 | sata_led_active_pa5 { | |
76 | nvidia,pins = "sata_led_active_pa5"; | |
77 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
78 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
79 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
80 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
81 | }; | |
82 | pa6 { | |
83 | nvidia,pins = "pa6"; | |
84 | nvidia,function = "sata"; | |
85 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
86 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
87 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
88 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
89 | }; | |
90 | dap1_fs_pb0 { | |
91 | nvidia,pins = "dap1_fs_pb0"; | |
92 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
93 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
94 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
95 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
96 | }; | |
97 | dap1_din_pb1 { | |
98 | nvidia,pins = "dap1_din_pb1"; | |
99 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
100 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
101 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
102 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
103 | }; | |
104 | dap1_dout_pb2 { | |
105 | nvidia,pins = "dap1_dout_pb2"; | |
106 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
107 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
108 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
109 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
110 | }; | |
111 | dap1_sclk_pb3 { | |
112 | nvidia,pins = "dap1_sclk_pb3"; | |
113 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
114 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
115 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
116 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
117 | }; | |
118 | spi2_mosi_pb4 { | |
119 | nvidia,pins = "spi2_mosi_pb4"; | |
120 | nvidia,function = "spi2"; | |
121 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
122 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
123 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
124 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
125 | }; | |
126 | spi2_miso_pb5 { | |
127 | nvidia,pins = "spi2_miso_pb5"; | |
128 | nvidia,function = "spi2"; | |
129 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
130 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
131 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
132 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
133 | }; | |
134 | spi2_sck_pb6 { | |
135 | nvidia,pins = "spi2_sck_pb6"; | |
136 | nvidia,function = "spi2"; | |
137 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
138 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
139 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
140 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
141 | }; | |
142 | spi2_cs0_pb7 { | |
143 | nvidia,pins = "spi2_cs0_pb7"; | |
144 | nvidia,function = "spi2"; | |
145 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
146 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
147 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
148 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
149 | }; | |
150 | spi1_mosi_pc0 { | |
151 | nvidia,pins = "spi1_mosi_pc0"; | |
152 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
153 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
154 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
155 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
156 | }; | |
157 | spi1_miso_pc1 { | |
158 | nvidia,pins = "spi1_miso_pc1"; | |
159 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
160 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
161 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
162 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
163 | }; | |
164 | spi1_sck_pc2 { | |
165 | nvidia,pins = "spi1_sck_pc2"; | |
166 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
167 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
168 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
169 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
170 | }; | |
171 | spi1_cs0_pc3 { | |
172 | nvidia,pins = "spi1_cs0_pc3"; | |
173 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
174 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
175 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
176 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
177 | }; | |
178 | spi1_cs1_pc4 { | |
179 | nvidia,pins = "spi1_cs1_pc4"; | |
180 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
181 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
182 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
183 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
184 | }; | |
185 | spi4_sck_pc5 { | |
186 | nvidia,pins = "spi4_sck_pc5"; | |
187 | nvidia,function = "spi4"; | |
188 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
190 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
191 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
192 | }; | |
193 | spi4_cs0_pc6 { | |
194 | nvidia,pins = "spi4_cs0_pc6"; | |
195 | nvidia,function = "spi4"; | |
196 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
197 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
198 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
199 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
200 | }; | |
201 | spi4_mosi_pc7 { | |
202 | nvidia,pins = "spi4_mosi_pc7"; | |
203 | nvidia,function = "spi4"; | |
204 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
205 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
206 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
207 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
208 | }; | |
209 | spi4_miso_pd0 { | |
210 | nvidia,pins = "spi4_miso_pd0"; | |
211 | nvidia,function = "spi4"; | |
212 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
213 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
214 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
215 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
216 | }; | |
217 | uart3_tx_pd1 { | |
218 | nvidia,pins = "uart3_tx_pd1"; | |
219 | nvidia,function = "uartc"; | |
220 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
221 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
222 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
223 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
224 | }; | |
225 | uart3_rx_pd2 { | |
226 | nvidia,pins = "uart3_rx_pd2"; | |
227 | nvidia,function = "uartc"; | |
228 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
229 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
230 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
231 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
232 | }; | |
233 | uart3_rts_pd3 { | |
234 | nvidia,pins = "uart3_rts_pd3"; | |
235 | nvidia,function = "uartc"; | |
236 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
237 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
238 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
239 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
240 | }; | |
241 | uart3_cts_pd4 { | |
242 | nvidia,pins = "uart3_cts_pd4"; | |
243 | nvidia,function = "uartc"; | |
244 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
245 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
246 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
247 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
248 | }; | |
249 | dmic1_clk_pe0 { | |
250 | nvidia,pins = "dmic1_clk_pe0"; | |
251 | nvidia,function = "i2s3"; | |
252 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
253 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
254 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
255 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
256 | }; | |
257 | dmic1_dat_pe1 { | |
258 | nvidia,pins = "dmic1_dat_pe1"; | |
259 | nvidia,function = "i2s3"; | |
260 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
261 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
262 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
263 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
264 | }; | |
265 | dmic2_clk_pe2 { | |
266 | nvidia,pins = "dmic2_clk_pe2"; | |
267 | nvidia,function = "i2s3"; | |
268 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
269 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
270 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
271 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
272 | }; | |
273 | dmic2_dat_pe3 { | |
274 | nvidia,pins = "dmic2_dat_pe3"; | |
275 | nvidia,function = "i2s3"; | |
276 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
277 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
278 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
279 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
280 | }; | |
281 | dmic3_clk_pe4 { | |
282 | nvidia,pins = "dmic3_clk_pe4"; | |
283 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
284 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
285 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
286 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
287 | }; | |
288 | dmic3_dat_pe5 { | |
289 | nvidia,pins = "dmic3_dat_pe5"; | |
290 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
291 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
292 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
293 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
294 | }; | |
295 | pe6 { | |
296 | nvidia,pins = "pe6"; | |
297 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
298 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
299 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
300 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
301 | }; | |
302 | pe7 { | |
303 | nvidia,pins = "pe7"; | |
304 | nvidia,function = "pwm3"; | |
305 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
306 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
307 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
308 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
309 | }; | |
310 | gen3_i2c_scl_pf0 { | |
311 | nvidia,pins = "gen3_i2c_scl_pf0"; | |
312 | nvidia,function = "i2c3"; | |
313 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
314 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
315 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
316 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
317 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
318 | }; | |
319 | gen3_i2c_sda_pf1 { | |
320 | nvidia,pins = "gen3_i2c_sda_pf1"; | |
321 | nvidia,function = "i2c3"; | |
322 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
323 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
324 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
325 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
326 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
327 | }; | |
328 | uart2_tx_pg0 { | |
329 | nvidia,pins = "uart2_tx_pg0"; | |
330 | nvidia,function = "uartb"; | |
331 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
332 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
333 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
334 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
335 | }; | |
336 | uart2_rx_pg1 { | |
337 | nvidia,pins = "uart2_rx_pg1"; | |
338 | nvidia,function = "uartb"; | |
339 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
340 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
341 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
342 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
343 | }; | |
344 | uart2_rts_pg2 { | |
345 | nvidia,pins = "uart2_rts_pg2"; | |
346 | nvidia,function = "uartb"; | |
347 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
348 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
349 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
350 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
351 | }; | |
352 | uart2_cts_pg3 { | |
353 | nvidia,pins = "uart2_cts_pg3"; | |
354 | nvidia,function = "uartb"; | |
355 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
356 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
357 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
358 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
359 | }; | |
360 | wifi_en_ph0 { | |
361 | nvidia,pins = "wifi_en_ph0"; | |
362 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
363 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
364 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
365 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
366 | }; | |
367 | wifi_rst_ph1 { | |
368 | nvidia,pins = "wifi_rst_ph1"; | |
369 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
370 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
371 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
372 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
373 | }; | |
374 | wifi_wake_ap_ph2 { | |
375 | nvidia,pins = "wifi_wake_ap_ph2"; | |
376 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
377 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
378 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
379 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
380 | }; | |
381 | ap_wake_bt_ph3 { | |
382 | nvidia,pins = "ap_wake_bt_ph3"; | |
383 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
384 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
385 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
386 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
387 | }; | |
388 | bt_rst_ph4 { | |
389 | nvidia,pins = "bt_rst_ph4"; | |
390 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
391 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
392 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
393 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
394 | }; | |
395 | bt_wake_ap_ph5 { | |
396 | nvidia,pins = "bt_wake_ap_ph5"; | |
397 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
398 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
399 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
400 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
401 | }; | |
402 | ph6 { | |
403 | nvidia,pins = "ph6"; | |
404 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
405 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
406 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
407 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
408 | }; | |
409 | ap_wake_nfc_ph7 { | |
410 | nvidia,pins = "ap_wake_nfc_ph7"; | |
411 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
412 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
413 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
414 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
415 | }; | |
416 | nfc_en_pi0 { | |
417 | nvidia,pins = "nfc_en_pi0"; | |
418 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
419 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
420 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
421 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
422 | }; | |
423 | nfc_int_pi1 { | |
424 | nvidia,pins = "nfc_int_pi1"; | |
425 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
426 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
427 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
428 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
429 | }; | |
430 | gps_en_pi2 { | |
431 | nvidia,pins = "gps_en_pi2"; | |
432 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
433 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
434 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
435 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
436 | }; | |
437 | gps_rst_pi3 { | |
438 | nvidia,pins = "gps_rst_pi3"; | |
439 | nvidia,function = "rsvd0"; | |
440 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
441 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
442 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
443 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
444 | }; | |
445 | uart4_tx_pi4 { | |
446 | nvidia,pins = "uart4_tx_pi4"; | |
447 | nvidia,function = "uartd"; | |
448 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
449 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
450 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
451 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
452 | }; | |
453 | uart4_rx_pi5 { | |
454 | nvidia,pins = "uart4_rx_pi5"; | |
455 | nvidia,function = "uartd"; | |
456 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
457 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
458 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
459 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
460 | }; | |
461 | uart4_rts_pi6 { | |
462 | nvidia,pins = "uart4_rts_pi6"; | |
463 | nvidia,function = "uartd"; | |
464 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
465 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
466 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
467 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
468 | }; | |
469 | uart4_cts_pi7 { | |
470 | nvidia,pins = "uart4_cts_pi7"; | |
471 | nvidia,function = "uartd"; | |
472 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
473 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
474 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
475 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
476 | }; | |
477 | gen1_i2c_sda_pj0 { | |
478 | nvidia,pins = "gen1_i2c_sda_pj0"; | |
479 | nvidia,function = "i2c1"; | |
480 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
481 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
482 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
483 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
484 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
485 | }; | |
486 | gen1_i2c_scl_pj1 { | |
487 | nvidia,pins = "gen1_i2c_scl_pj1"; | |
488 | nvidia,function = "i2c1"; | |
489 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
490 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
491 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
492 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
493 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
494 | }; | |
495 | gen2_i2c_scl_pj2 { | |
496 | nvidia,pins = "gen2_i2c_scl_pj2"; | |
497 | nvidia,function = "i2c2"; | |
498 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
499 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
500 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
501 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
502 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; | |
503 | }; | |
504 | gen2_i2c_sda_pj3 { | |
505 | nvidia,pins = "gen2_i2c_sda_pj3"; | |
506 | nvidia,function = "i2c2"; | |
507 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
508 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
509 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
510 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
511 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; | |
512 | }; | |
513 | dap4_fs_pj4 { | |
514 | nvidia,pins = "dap4_fs_pj4"; | |
515 | nvidia,function = "i2s4b"; | |
516 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
517 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
518 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
519 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
520 | }; | |
521 | dap4_din_pj5 { | |
522 | nvidia,pins = "dap4_din_pj5"; | |
523 | nvidia,function = "i2s4b"; | |
524 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
525 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
526 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
527 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
528 | }; | |
529 | dap4_dout_pj6 { | |
530 | nvidia,pins = "dap4_dout_pj6"; | |
531 | nvidia,function = "i2s4b"; | |
532 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
533 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
534 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
535 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
536 | }; | |
537 | dap4_sclk_pj7 { | |
538 | nvidia,pins = "dap4_sclk_pj7"; | |
539 | nvidia,function = "i2s4b"; | |
540 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
541 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
542 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
543 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
544 | }; | |
545 | pk0 { | |
546 | nvidia,pins = "pk0"; | |
547 | nvidia,function = "i2s5b"; | |
548 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
549 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
550 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
551 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
552 | }; | |
553 | pk1 { | |
554 | nvidia,pins = "pk1"; | |
555 | nvidia,function = "i2s5b"; | |
556 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
557 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
558 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
559 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
560 | }; | |
561 | pk2 { | |
562 | nvidia,pins = "pk2"; | |
563 | nvidia,function = "i2s5b"; | |
564 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
565 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
566 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
567 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
568 | }; | |
569 | pk3 { | |
570 | nvidia,pins = "pk3"; | |
571 | nvidia,function = "i2s5b"; | |
572 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
573 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
574 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
575 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
576 | }; | |
577 | pk4 { | |
578 | nvidia,pins = "pk4"; | |
579 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
580 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
581 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
582 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
583 | }; | |
584 | pk5 { | |
585 | nvidia,pins = "pk5"; | |
586 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
587 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
588 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
589 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
590 | }; | |
591 | pk6 { | |
592 | nvidia,pins = "pk6"; | |
593 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
594 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
595 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
596 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
597 | }; | |
598 | pk7 { | |
599 | nvidia,pins = "pk7"; | |
600 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
601 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
602 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
603 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
604 | }; | |
605 | pl0 { | |
606 | nvidia,pins = "pl0"; | |
607 | nvidia,function = "rsvd0"; | |
608 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
609 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
610 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
611 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
612 | }; | |
613 | pl1 { | |
614 | nvidia,pins = "pl1"; | |
615 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
616 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
617 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
618 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
619 | }; | |
620 | sdmmc1_clk_pm0 { | |
621 | nvidia,pins = "sdmmc1_clk_pm0"; | |
622 | nvidia,function = "sdmmc1"; | |
623 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
624 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
625 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
626 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
627 | }; | |
628 | sdmmc1_cmd_pm1 { | |
629 | nvidia,pins = "sdmmc1_cmd_pm1"; | |
630 | nvidia,function = "sdmmc1"; | |
631 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
632 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
633 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
634 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
635 | }; | |
636 | sdmmc1_dat3_pm2 { | |
637 | nvidia,pins = "sdmmc1_dat3_pm2"; | |
638 | nvidia,function = "sdmmc1"; | |
639 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
640 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
641 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
642 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
643 | }; | |
644 | sdmmc1_dat2_pm3 { | |
645 | nvidia,pins = "sdmmc1_dat2_pm3"; | |
646 | nvidia,function = "sdmmc1"; | |
647 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
648 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
649 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
650 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
651 | }; | |
652 | sdmmc1_dat1_pm4 { | |
653 | nvidia,pins = "sdmmc1_dat1_pm4"; | |
654 | nvidia,function = "sdmmc1"; | |
655 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
656 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
657 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
658 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
659 | }; | |
660 | sdmmc1_dat0_pm5 { | |
661 | nvidia,pins = "sdmmc1_dat0_pm5"; | |
662 | nvidia,function = "sdmmc1"; | |
663 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
664 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
665 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
666 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
667 | }; | |
668 | sdmmc3_clk_pp0 { | |
669 | nvidia,pins = "sdmmc3_clk_pp0"; | |
670 | nvidia,function = "sdmmc3"; | |
671 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
672 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
673 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
674 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
675 | }; | |
676 | sdmmc3_cmd_pp1 { | |
677 | nvidia,pins = "sdmmc3_cmd_pp1"; | |
678 | nvidia,function = "sdmmc3"; | |
679 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
680 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
681 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
682 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
683 | }; | |
684 | sdmmc3_dat3_pp2 { | |
685 | nvidia,pins = "sdmmc3_dat3_pp2"; | |
686 | nvidia,function = "sdmmc3"; | |
687 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
688 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
689 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
690 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
691 | }; | |
692 | sdmmc3_dat2_pp3 { | |
693 | nvidia,pins = "sdmmc3_dat2_pp3"; | |
694 | nvidia,function = "sdmmc3"; | |
695 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
696 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
697 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
698 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
699 | }; | |
700 | sdmmc3_dat1_pp4 { | |
701 | nvidia,pins = "sdmmc3_dat1_pp4"; | |
702 | nvidia,function = "sdmmc3"; | |
703 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
704 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
705 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
706 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
707 | }; | |
708 | sdmmc3_dat0_pp5 { | |
709 | nvidia,pins = "sdmmc3_dat0_pp5"; | |
710 | nvidia,function = "sdmmc3"; | |
711 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
712 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
713 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
714 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
715 | }; | |
716 | cam1_mclk_ps0 { | |
717 | nvidia,pins = "cam1_mclk_ps0"; | |
718 | nvidia,function = "extperiph3"; | |
719 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
720 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
721 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
722 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
723 | }; | |
724 | cam2_mclk_ps1 { | |
725 | nvidia,pins = "cam2_mclk_ps1"; | |
726 | nvidia,function = "extperiph3"; | |
727 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
728 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
729 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
730 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
731 | }; | |
732 | cam_i2c_scl_ps2 { | |
733 | nvidia,pins = "cam_i2c_scl_ps2"; | |
734 | nvidia,function = "i2cvi"; | |
735 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
736 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
737 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
738 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
739 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
740 | }; | |
741 | cam_i2c_sda_ps3 { | |
742 | nvidia,pins = "cam_i2c_sda_ps3"; | |
743 | nvidia,function = "i2cvi"; | |
744 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
745 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
746 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
747 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
748 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
749 | }; | |
750 | cam_rst_ps4 { | |
751 | nvidia,pins = "cam_rst_ps4"; | |
752 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
753 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
754 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
755 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
756 | }; | |
757 | cam_af_en_ps5 { | |
758 | nvidia,pins = "cam_af_en_ps5"; | |
759 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
760 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
761 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
762 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
763 | }; | |
764 | cam_flash_en_ps6 { | |
765 | nvidia,pins = "cam_flash_en_ps6"; | |
766 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
767 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
768 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
769 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
770 | }; | |
771 | cam1_pwdn_ps7 { | |
772 | nvidia,pins = "cam1_pwdn_ps7"; | |
773 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
774 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
775 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
776 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
777 | }; | |
778 | cam2_pwdn_pt0 { | |
779 | nvidia,pins = "cam2_pwdn_pt0"; | |
780 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
781 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
782 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
783 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
784 | }; | |
785 | cam1_strobe_pt1 { | |
786 | nvidia,pins = "cam1_strobe_pt1"; | |
787 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
788 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
789 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
790 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
791 | }; | |
792 | uart1_tx_pu0 { | |
793 | nvidia,pins = "uart1_tx_pu0"; | |
794 | nvidia,function = "uarta"; | |
795 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
796 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
797 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
798 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
799 | }; | |
800 | uart1_rx_pu1 { | |
801 | nvidia,pins = "uart1_rx_pu1"; | |
802 | nvidia,function = "uarta"; | |
803 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
804 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
805 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
806 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
807 | }; | |
808 | uart1_rts_pu2 { | |
809 | nvidia,pins = "uart1_rts_pu2"; | |
810 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
811 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
812 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
813 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
814 | }; | |
815 | uart1_cts_pu3 { | |
816 | nvidia,pins = "uart1_cts_pu3"; | |
817 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
818 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
819 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
820 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
821 | }; | |
822 | lcd_bl_pwm_pv0 { | |
823 | nvidia,pins = "lcd_bl_pwm_pv0"; | |
824 | nvidia,function = "pwm0"; | |
825 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
826 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
827 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
828 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
829 | }; | |
830 | lcd_bl_en_pv1 { | |
831 | nvidia,pins = "lcd_bl_en_pv1"; | |
832 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
833 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
834 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
835 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
836 | }; | |
837 | lcd_rst_pv2 { | |
838 | nvidia,pins = "lcd_rst_pv2"; | |
839 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
840 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
841 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
842 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
843 | }; | |
844 | lcd_gpio1_pv3 { | |
845 | nvidia,pins = "lcd_gpio1_pv3"; | |
846 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
847 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
848 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
849 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
850 | }; | |
851 | lcd_gpio2_pv4 { | |
852 | nvidia,pins = "lcd_gpio2_pv4"; | |
853 | nvidia,function = "pwm1"; | |
854 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
855 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
856 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
857 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
858 | }; | |
859 | ap_ready_pv5 { | |
860 | nvidia,pins = "ap_ready_pv5"; | |
861 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
862 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
863 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
864 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
865 | }; | |
866 | touch_rst_pv6 { | |
867 | nvidia,pins = "touch_rst_pv6"; | |
868 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
869 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
870 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
871 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
872 | }; | |
873 | touch_clk_pv7 { | |
874 | nvidia,pins = "touch_clk_pv7"; | |
875 | nvidia,function = "touch"; | |
876 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
877 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
878 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
879 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
880 | }; | |
881 | modem_wake_ap_px0 { | |
882 | nvidia,pins = "modem_wake_ap_px0"; | |
883 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
884 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
885 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
886 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
887 | }; | |
888 | touch_int_px1 { | |
889 | nvidia,pins = "touch_int_px1"; | |
890 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
891 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
892 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
893 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
894 | }; | |
895 | motion_int_px2 { | |
896 | nvidia,pins = "motion_int_px2"; | |
897 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
898 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
899 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
900 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
901 | }; | |
902 | als_prox_int_px3 { | |
903 | nvidia,pins = "als_prox_int_px3"; | |
904 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
905 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
906 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
907 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
908 | }; | |
909 | temp_alert_px4 { | |
910 | nvidia,pins = "temp_alert_px4"; | |
911 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
912 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
913 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
914 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
915 | }; | |
916 | button_power_on_px5 { | |
917 | nvidia,pins = "button_power_on_px5"; | |
918 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
919 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
920 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
921 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
922 | }; | |
923 | button_vol_up_px6 { | |
924 | nvidia,pins = "button_vol_up_px6"; | |
925 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
926 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
927 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
928 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
929 | }; | |
930 | button_vol_down_px7 { | |
931 | nvidia,pins = "button_vol_down_px7"; | |
932 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
933 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
934 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
935 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
936 | }; | |
937 | button_slide_sw_py0 { | |
938 | nvidia,pins = "button_slide_sw_py0"; | |
939 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
940 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
941 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
942 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
943 | }; | |
944 | button_home_py1 { | |
945 | nvidia,pins = "button_home_py1"; | |
946 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
947 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
948 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
949 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
950 | }; | |
951 | lcd_te_py2 { | |
952 | nvidia,pins = "lcd_te_py2"; | |
953 | nvidia,function = "displaya"; | |
954 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
955 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
956 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
957 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
958 | }; | |
959 | pwr_i2c_scl_py3 { | |
960 | nvidia,pins = "pwr_i2c_scl_py3"; | |
961 | nvidia,function = "i2cpmu"; | |
962 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
963 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
964 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
965 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
966 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
967 | }; | |
968 | pwr_i2c_sda_py4 { | |
969 | nvidia,pins = "pwr_i2c_sda_py4"; | |
970 | nvidia,function = "i2cpmu"; | |
971 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
972 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
973 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
974 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
975 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
976 | }; | |
977 | clk_32k_out_py5 { | |
978 | nvidia,pins = "clk_32k_out_py5"; | |
979 | nvidia,function = "soc"; | |
980 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
981 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
982 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
983 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
984 | }; | |
985 | pz0 { | |
986 | nvidia,pins = "pz0"; | |
987 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
988 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
989 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
990 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
991 | }; | |
992 | pz1 { | |
993 | nvidia,pins = "pz1"; | |
994 | nvidia,function = "sdmmc1"; | |
995 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
996 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
997 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
998 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
999 | }; | |
1000 | pz2 { | |
1001 | nvidia,pins = "pz2"; | |
1002 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1003 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1004 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1005 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1006 | }; | |
1007 | pz3 { | |
1008 | nvidia,pins = "pz3"; | |
1009 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1010 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1011 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1012 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1013 | }; | |
1014 | pz4 { | |
1015 | nvidia,pins = "pz4"; | |
1016 | nvidia,function = "sdmmc1"; | |
1017 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1018 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1019 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1020 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1021 | }; | |
1022 | pz5 { | |
1023 | nvidia,pins = "pz5"; | |
1024 | nvidia,function = "soc"; | |
1025 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1026 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1027 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1028 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1029 | }; | |
1030 | dap2_fs_paa0 { | |
1031 | nvidia,pins = "dap2_fs_paa0"; | |
1032 | nvidia,function = "i2s2"; | |
1033 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1034 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1035 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1036 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1037 | }; | |
1038 | dap2_sclk_paa1 { | |
1039 | nvidia,pins = "dap2_sclk_paa1"; | |
1040 | nvidia,function = "i2s2"; | |
1041 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1042 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1043 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1044 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1045 | }; | |
1046 | dap2_din_paa2 { | |
1047 | nvidia,pins = "dap2_din_paa2"; | |
1048 | nvidia,function = "i2s2"; | |
1049 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1050 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1051 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1052 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1053 | }; | |
1054 | dap2_dout_paa3 { | |
1055 | nvidia,pins = "dap2_dout_paa3"; | |
1056 | nvidia,function = "i2s2"; | |
1057 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1058 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1059 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1060 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1061 | }; | |
1062 | aud_mclk_pbb0 { | |
1063 | nvidia,pins = "aud_mclk_pbb0"; | |
1064 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1065 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1066 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1067 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1068 | }; | |
1069 | dvfs_pwm_pbb1 { | |
1070 | nvidia,pins = "dvfs_pwm_pbb1"; | |
1071 | nvidia,function = "cldvfs"; | |
1072 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1073 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1074 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1075 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1076 | }; | |
1077 | dvfs_clk_pbb2 { | |
1078 | nvidia,pins = "dvfs_clk_pbb2"; | |
1079 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1080 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1081 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1082 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1083 | }; | |
1084 | gpio_x1_aud_pbb3 { | |
1085 | nvidia,pins = "gpio_x1_aud_pbb3"; | |
1086 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1087 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1088 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1089 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1090 | }; | |
1091 | gpio_x3_aud_pbb4 { | |
1092 | nvidia,pins = "gpio_x3_aud_pbb4"; | |
1093 | nvidia,function = "rsvd0"; | |
1094 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1095 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1096 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1097 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1098 | }; | |
1099 | hdmi_cec_pcc0 { | |
1100 | nvidia,pins = "hdmi_cec_pcc0"; | |
1101 | nvidia,function = "cec"; | |
1102 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1103 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1104 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1105 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1106 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; | |
1107 | }; | |
1108 | hdmi_int_dp_hpd_pcc1 { | |
1109 | nvidia,pins = "hdmi_int_dp_hpd_pcc1"; | |
1110 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1111 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1112 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1113 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1114 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
1115 | }; | |
1116 | spdif_out_pcc2 { | |
1117 | nvidia,pins = "spdif_out_pcc2"; | |
1118 | nvidia,function = "rsvd1"; | |
1119 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1120 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1121 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1122 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1123 | }; | |
1124 | spdif_in_pcc3 { | |
1125 | nvidia,pins = "spdif_in_pcc3"; | |
1126 | nvidia,function = "rsvd1"; | |
1127 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1128 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1129 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1130 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1131 | }; | |
1132 | usb_vbus_en0_pcc4 { | |
1133 | nvidia,pins = "usb_vbus_en0_pcc4"; | |
1134 | nvidia,function = "usb"; | |
1135 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1136 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1137 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1138 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1139 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; | |
1140 | }; | |
1141 | usb_vbus_en1_pcc5 { | |
1142 | nvidia,pins = "usb_vbus_en1_pcc5"; | |
1143 | nvidia,function = "usb"; | |
1144 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1145 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1146 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1147 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1148 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; | |
1149 | }; | |
1150 | dp_hpd0_pcc6 { | |
1151 | nvidia,pins = "dp_hpd0_pcc6"; | |
1152 | nvidia,function = "dp"; | |
1153 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1154 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1155 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1156 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1157 | }; | |
1158 | pcc7 { | |
1159 | nvidia,pins = "pcc7"; | |
1160 | nvidia,function = "rsvd0"; | |
1161 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1162 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1163 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1164 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1165 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
1166 | }; | |
1167 | spi2_cs1_pdd0 { | |
1168 | nvidia,pins = "spi2_cs1_pdd0"; | |
1169 | nvidia,function = "spi2"; | |
1170 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1171 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1172 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1173 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1174 | }; | |
1175 | qspi_sck_pee0 { | |
1176 | nvidia,pins = "qspi_sck_pee0"; | |
1177 | nvidia,function = "rsvd1"; | |
1178 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1179 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1180 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1181 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1182 | }; | |
1183 | qspi_cs_n_pee1 { | |
1184 | nvidia,pins = "qspi_cs_n_pee1"; | |
1185 | nvidia,function = "rsvd1"; | |
1186 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1187 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1188 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1189 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1190 | }; | |
1191 | qspi_io0_pee2 { | |
1192 | nvidia,pins = "qspi_io0_pee2"; | |
1193 | nvidia,function = "rsvd1"; | |
1194 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1195 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1196 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1197 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1198 | }; | |
1199 | qspi_io1_pee3 { | |
1200 | nvidia,pins = "qspi_io1_pee3"; | |
1201 | nvidia,function = "rsvd1"; | |
1202 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1203 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1204 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1205 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1206 | }; | |
1207 | qspi_io2_pee4 { | |
1208 | nvidia,pins = "qspi_io2_pee4"; | |
1209 | nvidia,function = "rsvd1"; | |
1210 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1211 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1212 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1213 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1214 | }; | |
1215 | qspi_io3_pee5 { | |
1216 | nvidia,pins = "qspi_io3_pee5"; | |
1217 | nvidia,function = "rsvd1"; | |
1218 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1219 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1220 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1221 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1222 | }; | |
1223 | core_pwr_req { | |
1224 | nvidia,pins = "core_pwr_req"; | |
1225 | nvidia,function = "core"; | |
1226 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1227 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1228 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1229 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1230 | }; | |
1231 | cpu_pwr_req { | |
1232 | nvidia,pins = "cpu_pwr_req"; | |
1233 | nvidia,function = "cpu"; | |
1234 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1235 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1236 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1237 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1238 | }; | |
1239 | pwr_int_n { | |
1240 | nvidia,pins = "pwr_int_n"; | |
1241 | nvidia,function = "pmi"; | |
1242 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1243 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1244 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1245 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1246 | }; | |
1247 | clk_32k_in { | |
1248 | nvidia,pins = "clk_32k_in"; | |
1249 | nvidia,function = "clk"; | |
1250 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1251 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1252 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1253 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1254 | }; | |
1255 | jtag_rtck { | |
1256 | nvidia,pins = "jtag_rtck"; | |
1257 | nvidia,function = "jtag"; | |
1258 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1259 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1260 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1261 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1262 | }; | |
1263 | clk_req { | |
1264 | nvidia,pins = "clk_req"; | |
1265 | nvidia,function = "rsvd1"; | |
1266 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1267 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1268 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1269 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1270 | }; | |
1271 | shutdown { | |
1272 | nvidia,pins = "shutdown"; | |
1273 | nvidia,function = "shutdown"; | |
1274 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1275 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1276 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1277 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1278 | }; | |
1279 | }; | |
1280 | }; | |
1281 | ||
7596723e TR |
1282 | pwm@7000a000 { |
1283 | status = "okay"; | |
1284 | }; | |
1285 | ||
1286 | i2c@7000c400 { | |
1287 | status = "okay"; | |
1288 | clock-frequency = <100000>; | |
1289 | ||
1290 | exp1: gpio@74 { | |
1291 | compatible = "ti,tca9539"; | |
1292 | reg = <0x74>; | |
1293 | ||
1294 | #gpio-cells = <2>; | |
1295 | gpio-controller; | |
1296 | }; | |
1297 | }; | |
1298 | ||
34993594 TR |
1299 | /* HDMI DDC */ |
1300 | hdmi_ddc: i2c@7000c700 { | |
1301 | status = "okay"; | |
1302 | clock-frequency = <100000>; | |
1303 | }; | |
1304 | ||
d23e054c TR |
1305 | usb@70090000 { |
1306 | phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, | |
1307 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, | |
1308 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, | |
1309 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>, | |
1310 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>, | |
1311 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>; | |
1312 | phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0", | |
1313 | "usb3-1"; | |
1314 | ||
1315 | dvddio-pex-supply = <&vdd_pex_1v05>; | |
1316 | hvddio-pex-supply = <&vdd_1v8>; | |
1317 | avdd-usb-supply = <&vdd_3v3_sys>; | |
1318 | /* XXX what are these? */ | |
1319 | avdd-pll-utmip-supply = <&vdd_1v8>; | |
1320 | avdd-pll-uerefe-supply = <&vdd_pex_1v05>; | |
1321 | dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>; | |
1322 | hvdd-usb-ss-pll-e-supply = <&vdd_1v8>; | |
1323 | ||
1324 | status = "okay"; | |
1325 | }; | |
1326 | ||
1327 | padctl@7009f000 { | |
1328 | status = "okay"; | |
1329 | ||
1330 | pads { | |
1331 | usb2 { | |
1332 | status = "okay"; | |
1333 | ||
1334 | lanes { | |
1335 | usb2-0 { | |
1336 | nvidia,function = "xusb"; | |
1337 | status = "okay"; | |
1338 | }; | |
1339 | ||
1340 | usb2-1 { | |
1341 | nvidia,function = "xusb"; | |
1342 | status = "okay"; | |
1343 | }; | |
1344 | ||
1345 | usb2-2 { | |
1346 | nvidia,function = "xusb"; | |
1347 | status = "okay"; | |
1348 | }; | |
1349 | ||
1350 | usb2-3 { | |
1351 | nvidia,function = "xusb"; | |
1352 | status = "okay"; | |
1353 | }; | |
1354 | }; | |
1355 | }; | |
1356 | ||
1357 | pcie { | |
1358 | status = "okay"; | |
1359 | ||
1360 | lanes { | |
1361 | pcie-0 { | |
1362 | nvidia,function = "pcie-x1"; | |
1363 | status = "okay"; | |
1364 | }; | |
1365 | ||
1366 | pcie-1 { | |
1367 | nvidia,function = "pcie-x4"; | |
1368 | status = "okay"; | |
1369 | }; | |
1370 | ||
1371 | pcie-2 { | |
1372 | nvidia,function = "pcie-x4"; | |
1373 | status = "okay"; | |
1374 | }; | |
1375 | ||
1376 | pcie-3 { | |
1377 | nvidia,function = "pcie-x4"; | |
1378 | status = "okay"; | |
1379 | }; | |
1380 | ||
1381 | pcie-4 { | |
1382 | nvidia,function = "pcie-x4"; | |
1383 | status = "okay"; | |
1384 | }; | |
1385 | ||
1386 | pcie-5 { | |
1387 | nvidia,function = "usb3-ss"; | |
1388 | status = "okay"; | |
1389 | }; | |
1390 | ||
1391 | pcie-6 { | |
1392 | nvidia,function = "usb3-ss"; | |
1393 | status = "okay"; | |
1394 | }; | |
1395 | }; | |
1396 | }; | |
1397 | ||
1398 | sata { | |
1399 | status = "okay"; | |
1400 | ||
1401 | lanes { | |
1402 | sata-0 { | |
1403 | nvidia,function = "sata"; | |
1404 | status = "okay"; | |
1405 | }; | |
1406 | }; | |
1407 | }; | |
1408 | }; | |
1409 | ||
1410 | ports { | |
1411 | usb2-0 { | |
1412 | status = "okay"; | |
1413 | mode = "otg"; | |
1414 | }; | |
1415 | ||
1416 | usb2-1 { | |
1417 | status = "okay"; | |
1418 | vbus-supply = <&vdd_5v0_rtl>; | |
1419 | mode = "host"; | |
1420 | }; | |
1421 | ||
1422 | usb2-2 { | |
1423 | status = "okay"; | |
1424 | vbus-supply = <&vdd_usb_vbus>; | |
1425 | mode = "host"; | |
1426 | }; | |
1427 | ||
1428 | usb2-3 { | |
1429 | status = "okay"; | |
1430 | mode = "host"; | |
1431 | }; | |
1432 | ||
1433 | usb3-0 { | |
1434 | nvidia,usb2-companion = <1>; | |
1435 | status = "okay"; | |
1436 | }; | |
1437 | ||
1438 | usb3-1 { | |
1439 | nvidia,usb2-companion = <2>; | |
1440 | status = "okay"; | |
1441 | }; | |
1442 | }; | |
1443 | }; | |
1444 | ||
2e634057 | 1445 | /* MMC/SD */ |
be70771d | 1446 | sdhci@700b0000 { |
2e634057 TR |
1447 | status = "okay"; |
1448 | bus-width = <4>; | |
1449 | no-1-8-v; | |
1450 | ||
1451 | cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; | |
6d5aef5b TR |
1452 | |
1453 | vqmmc-supply = <&vddio_sdmmc>; | |
1454 | vmmc-supply = <&vdd_3v3_sd>; | |
2e634057 | 1455 | }; |
0e91ba42 | 1456 | |
77934269 TR |
1457 | regulators { |
1458 | compatible = "simple-bus"; | |
1459 | #address-cells = <1>; | |
1460 | #size-cells = <0>; | |
1461 | ||
1462 | vdd_sys_mux: regulator@0 { | |
1463 | compatible = "regulator-fixed"; | |
1464 | reg = <0>; | |
1465 | regulator-name = "VDD_SYS_MUX"; | |
1466 | regulator-min-microvolt = <5000000>; | |
1467 | regulator-max-microvolt = <5000000>; | |
1468 | regulator-always-on; | |
1469 | regulator-boot-on; | |
1470 | }; | |
1471 | ||
1472 | vdd_5v0_sys: regulator@1 { | |
1473 | compatible = "regulator-fixed"; | |
1474 | reg = <1>; | |
1475 | regulator-name = "VDD_5V0_SYS"; | |
1476 | regulator-min-microvolt = <5000000>; | |
1477 | regulator-max-microvolt = <5000000>; | |
1478 | regulator-always-on; | |
1479 | regulator-boot-on; | |
1480 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; | |
1481 | enable-active-high; | |
1482 | vin-supply = <&vdd_sys_mux>; | |
1483 | }; | |
1484 | ||
1485 | vdd_3v3_sys: regulator@2 { | |
1486 | compatible = "regulator-fixed"; | |
1487 | reg = <2>; | |
1488 | regulator-name = "VDD_3V3_SYS"; | |
1489 | regulator-min-microvolt = <3300000>; | |
1490 | regulator-max-microvolt = <3300000>; | |
1491 | regulator-always-on; | |
1492 | regulator-boot-on; | |
1493 | gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; | |
1494 | enable-active-high; | |
1495 | vin-supply = <&vdd_sys_mux>; | |
1496 | ||
1497 | regulator-enable-ramp-delay = <160>; | |
1498 | regulator-disable-ramp-delay = <10000>; | |
1499 | }; | |
1500 | ||
1501 | vdd_5v0_io: regulator@3 { | |
1502 | compatible = "regulator-fixed"; | |
1503 | reg = <3>; | |
1504 | regulator-name = "VDD_5V0_IO_SYS"; | |
1505 | regulator-min-microvolt = <5000000>; | |
1506 | regulator-max-microvolt = <5000000>; | |
1507 | regulator-always-on; | |
1508 | regulator-boot-on; | |
1509 | }; | |
6d5aef5b TR |
1510 | |
1511 | vdd_3v3_sd: regulator@4 { | |
1512 | compatible = "regulator-fixed"; | |
1513 | reg = <4>; | |
1514 | regulator-name = "VDD_3V3_SD"; | |
1515 | regulator-min-microvolt = <3300000>; | |
1516 | regulator-max-microvolt = <3300000>; | |
1517 | gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; | |
1518 | enable-active-high; | |
1519 | vin-supply = <&vdd_3v3_sys>; | |
1520 | ||
1521 | regulator-enable-ramp-delay = <472>; | |
1522 | regulator-disable-ramp-delay = <4880>; | |
1523 | }; | |
7596723e TR |
1524 | |
1525 | vdd_dsi_csi: regulator@5 { | |
1526 | compatible = "regulator-fixed"; | |
1527 | reg = <5>; | |
1528 | regulator-name = "AVDD_DSI_CSI_1V2"; | |
1529 | regulator-min-microvolt = <1200000>; | |
1530 | regulator-max-microvolt = <1200000>; | |
1531 | vin-supply = <&vdd_sys_1v2>; | |
1532 | }; | |
1533 | ||
1534 | vdd_3v3_dis: regulator@6 { | |
1535 | compatible = "regulator-fixed"; | |
1536 | reg = <6>; | |
1537 | regulator-name = "VDD_DIS_3V3_LCD"; | |
1538 | regulator-min-microvolt = <3300000>; | |
1539 | regulator-max-microvolt = <3300000>; | |
1540 | regulator-always-on; | |
1541 | gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; | |
1542 | enable-active-high; | |
1543 | vin-supply = <&vdd_3v3_sys>; | |
1544 | }; | |
1545 | ||
1546 | vdd_1v8_dis: regulator@7 { | |
1547 | compatible = "regulator-fixed"; | |
1548 | reg = <7>; | |
1549 | regulator-name = "VDD_LCD_1V8_DIS"; | |
1550 | regulator-min-microvolt = <1800000>; | |
1551 | regulator-max-microvolt = <1800000>; | |
1552 | regulator-always-on; | |
1553 | gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; | |
1554 | enable-active-high; | |
1555 | vin-supply = <&vdd_1v8>; | |
1556 | }; | |
d23e054c TR |
1557 | |
1558 | vdd_5v0_rtl: regulator@8 { | |
1559 | compatible = "regulator-fixed"; | |
1560 | reg = <8>; | |
1561 | regulator-name = "RTL_5V"; | |
1562 | regulator-min-microvolt = <5000000>; | |
1563 | regulator-max-microvolt = <5000000>; | |
1564 | gpio = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; | |
1565 | enable-active-high; | |
1566 | vin-supply = <&vdd_5v0_sys>; | |
1567 | }; | |
1568 | ||
1569 | vdd_usb_vbus: regulator@9 { | |
1570 | compatible = "regulator-fixed"; | |
1571 | reg = <9>; | |
1572 | regulator-name = "USB_VBUS_EN1"; | |
1573 | regulator-min-microvolt = <5000000>; | |
1574 | regulator-max-microvolt = <5000000>; | |
1575 | gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; | |
1576 | enable-active-high; | |
1577 | vin-supply = <&vdd_5v0_sys>; | |
1578 | }; | |
34993594 TR |
1579 | |
1580 | vdd_hdmi: regulator@10 { | |
1581 | compatible = "regulator-fixed"; | |
1582 | reg = <10>; | |
1583 | regulator-name = "VDD_HDMI_5V0"; | |
1584 | regulator-min-microvolt = <5000000>; | |
1585 | regulator-max-microvolt = <5000000>; | |
1586 | gpio = <&exp1 12 GPIO_ACTIVE_LOW>; | |
1587 | enable-active-high; | |
1588 | vin-supply = <&vdd_5v0_sys>; | |
1589 | }; | |
77934269 TR |
1590 | }; |
1591 | ||
0e91ba42 LD |
1592 | gpio-keys { |
1593 | compatible = "gpio-keys"; | |
1594 | label = "gpio-keys"; | |
1595 | ||
1596 | power { | |
1597 | label = "Power"; | |
1598 | gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; | |
1599 | linux,code = <KEY_POWER>; | |
1600 | wakeup-source; | |
1601 | }; | |
1602 | ||
1603 | volume_down { | |
1604 | label = "Volume Down"; | |
1605 | gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_LOW>; | |
1606 | linux,code = <KEY_VOLUMEDOWN>; | |
1607 | }; | |
1608 | ||
1609 | volume_up { | |
1610 | label = "Volume Up"; | |
1611 | gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; | |
1612 | linux,code = <KEY_VOLUMEUP>; | |
1613 | }; | |
1614 | }; | |
2e634057 | 1615 | }; |