[deliverable/linux.git] / arch / arm64 / boot / dts / qcom / msm8996.dtsi

/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>

/ {
	model = "Qualcomm Technologies, Inc. MSM8996";

	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	memory {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0 0 0>;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
		};

		CPU2: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
			L2_1: l2-cache {
			      compatible = "cache";
			      cache-level = <2>;
			};
		};

		CPU3: cpu@101 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU2>;
				};

				core1 {
					cpu = <&CPU3>;
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
		xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
			clock-output-names = "xo_board";
		};

		sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
			clock-output-names = "sleep_clk";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		intc: interrupt-controller@9bc0000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-controller;
			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x40000>;
			reg = <0x09bc0000 0x10000>,
			      <0x09c00000 0x100000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		gcc: clock-controller@300000 {
			compatible = "qcom,gcc-msm8996";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x300000 0x90000>;
		};

		blsp2_i2c0: i2c@075b5000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x075b5000 0x1000>;
			interrupts = <GIC_SPI 101 0>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
				<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_i2c0_default>;
			pinctrl-1 = <&blsp2_i2c0_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp2_uart1: serial@75b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x75b0000 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp2_i2c1: i2c@075b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x075b6000 0x1000>;
			interrupts = <GIC_SPI 102 0>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
				<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_i2c1_default>;
			pinctrl-1 = <&blsp2_i2c1_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp2_uart2: serial@75b1000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x075b1000 0x1000>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
				 <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_i2c2: i2c@07577000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x07577000 0x1000>;
			interrupts = <GIC_SPI 97 0>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_i2c2_default>;
			pinctrl-1 = <&blsp1_i2c2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		msmgpio: pinctrl@1010000 {
			compatible = "qcom,msm8996-pinctrl";
			reg = <0x01010000 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		timer@09840000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x09840000 0x1000>;
			clock-frequency = <19200000>;

			frame@9850000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x09850000 0x1000>,
				      <0x09860000 0x1000>;
			};

			frame@9870000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x09870000 0x1000>;
				status = "disabled";
			};

			frame@9880000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x09880000 0x1000>;
				status = "disabled";
			};

			frame@9890000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x09890000 0x1000>;
				status = "disabled";
			};

			frame@98a0000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x098a0000 0x1000>;
				status = "disabled";
			};

			frame@98b0000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x098b0000 0x1000>;
				status = "disabled";
			};

			frame@98c0000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x098c0000 0x1000>;
				status = "disabled";
			};
		};

		spmi_bus: qcom,spmi@400f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x400f000 0x1000>,
			      <0x4400000 0x800000>,
			      <0x4c00000 0x800000>,
			      <0x5800000 0x200000>,
			      <0x400a000 0x002100>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		mmcc: clock-controller@8c0000 {
			compatible = "qcom,mmcc-msm8996";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x8c0000 0x40000>;
			assigned-clocks = <&mmcc MMPLL9_PLL>,
					  <&mmcc MMPLL1_PLL>,
					  <&mmcc MMPLL3_PLL>,
					  <&mmcc MMPLL4_PLL>,
					  <&mmcc MMPLL5_PLL>;
			assigned-clock-rates = <624000000>,
					       <810000000>,
					       <980000000>,
					       <960000000>,
					       <825000000>;
		};
	};
};
#include "msm8996-pins.dtsi"
Commit	Line	Data
4558e9b3 SB	1	/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*/
	12
	13	#include <dt-bindings/interrupt-controller/arm-gic.h>
	14	#include <dt-bindings/clock/qcom,gcc-msm8996.h>
	15	#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
	16
	17	/ {
	18	model = "Qualcomm Technologies, Inc. MSM8996";
	19
	20	interrupt-parent = <&intc>;
	21
	22	#address-cells = <2>;
	23	#size-cells = <2>;
	24
	25	chosen { };
	26
	27	memory {
	28	device_type = "memory";
	29	/* We expect the bootloader to fill in the reg */
	30	reg = <0 0 0 0>;
	31	};
	32
	33	cpus {
	34	#address-cells = <2>;
	35	#size-cells = <0>;
	36
	37	CPU0: cpu@0 {
	38	device_type = "cpu";
	39	compatible = "qcom,kryo";
	40	reg = <0x0 0x0>;
	41	enable-method = "psci";
	42	next-level-cache = <&L2_0>;
	43	L2_0: l2-cache {
	44	compatible = "cache";
	45	cache-level = <2>;
	46	};
	47	};
	48
	49	CPU1: cpu@1 {
	50	device_type = "cpu";
	51	compatible = "qcom,kryo";
	52	reg = <0x0 0x1>;
	53	enable-method = "psci";
	54	next-level-cache = <&L2_0>;
	55	};
	56
	57	CPU2: cpu@100 {
	58	device_type = "cpu";
	59	compatible = "qcom,kryo";
	60	reg = <0x0 0x100>;
	61	enable-method = "psci";
	62	next-level-cache = <&L2_1>;
	63	L2_1: l2-cache {
	64	compatible = "cache";
65	cache-level = <2>;
66	};
67	};
68
69	CPU3: cpu@101 {
70	device_type = "cpu";
71	compatible = "qcom,kryo";
72	reg = <0x0 0x101>;
73	enable-method = "psci";
74	next-level-cache = <&L2_1>;
75	};
76
77	cpu-map {
78	cluster0 {
79	core0 {
80	cpu = <&CPU0>;
81	};
82
83	core1 {
84	cpu = <&CPU1>;
85	};
86	};
87
88	cluster1 {
89	core0 {
90	cpu = <&CPU2>;
91	};
92
93	core1 {
94	cpu = <&CPU3>;
95	};
96	};
97	};
98	};
99
100	timer {
101	compatible = "arm,armv8-timer";
102	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
103	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
104	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
105	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
106	};
107
108	clocks {
109	xo_board {
110	compatible = "fixed-clock";
111	#clock-cells = <0>;
112	clock-frequency = <19200000>;
113	clock-output-names = "xo_board";
114	};
115
116	sleep_clk {
117	compatible = "fixed-clock";
118	#clock-cells = <0>;
119	clock-frequency = <32764>;
120	clock-output-names = "sleep_clk";
121	};
122	};
123
124	psci {
125	compatible = "arm,psci-1.0";
126	method = "smc";
127	};
128
129	soc: soc {
130	#address-cells = <1>;
131	#size-cells = <1>;
132	ranges = <0 0 0 0xffffffff>;
133	compatible = "simple-bus";
134
135	intc: interrupt-controller@9bc0000 {
136	compatible = "arm,gic-v3";
137	#interrupt-cells = <3>;
138	interrupt-controller;
139	#redistributor-regions = <1>;
140	redistributor-stride = <0x0 0x40000>;
141	reg = <0x09bc0000 0x10000>,
142	<0x09c00000 0x100000>;
143	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
144	};
145
146	gcc: clock-controller@300000 {
147	compatible = "qcom,gcc-msm8996";
148	#clock-cells = <1>;
149	#reset-cells = <1>;
a70d7449	150	#power-domain-cells = <1>;
4558e9b3 SB	151	reg = <0x300000 0x90000>;
	152	};
	153
bf5443bc SK	154	blsp2_i2c0: i2c@075b5000 {
	155	compatible = "qcom,i2c-qup-v2.2.1";
	156	reg = <0x075b5000 0x1000>;
	157	interrupts = <GIC_SPI 101 0>;
	158	clocks = <&gcc GCC_BLSP2_AHB_CLK>,
	159	<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
	160	clock-names = "iface", "core";
	161	pinctrl-names = "default", "sleep";
	162	pinctrl-0 = <&blsp2_i2c0_default>;
	163	pinctrl-1 = <&blsp2_i2c0_sleep>;
	164	#address-cells = <1>;
	165	#size-cells = <0>;
	166	status = "disabled";
	167	};
	168
4558e9b3 SB	169	blsp2_uart1: serial@75b0000 {
	170	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	171	reg = <0x75b0000 0x1000>;
	172	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	173	clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
	174	<&gcc GCC_BLSP2_AHB_CLK>;
	175	clock-names = "core", "iface";
	176	status = "disabled";
	177	};
	178
d41d0cee SK	179	blsp2_i2c1: i2c@075b6000 {
	180	compatible = "qcom,i2c-qup-v2.2.1";
	181	reg = <0x075b6000 0x1000>;
	182	interrupts = <GIC_SPI 102 0>;
	183	clocks = <&gcc GCC_BLSP2_AHB_CLK>,
	184	<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
	185	clock-names = "iface", "core";
	186	pinctrl-names = "default", "sleep";
	187	pinctrl-0 = <&blsp2_i2c1_default>;
	188	pinctrl-1 = <&blsp2_i2c1_sleep>;
	189	#address-cells = <1>;
	190	#size-cells = <0>;
	191	status = "disabled";
	192	};
	193
fda48e61 SK	194	blsp2_uart2: serial@75b1000 {
	195	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	196	reg = <0x075b1000 0x1000>;
	197	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	198	clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
	199	<&gcc GCC_BLSP2_AHB_CLK>;
	200	clock-names = "core", "iface";
	201	status = "disabled";
	202	};
	203
21a40384 SK	204	blsp1_i2c2: i2c@07577000 {
	205	compatible = "qcom,i2c-qup-v2.2.1";
	206	reg = <0x07577000 0x1000>;
	207	interrupts = <GIC_SPI 97 0>;
	208	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	209	<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
	210	clock-names = "iface", "core";
	211	pinctrl-names = "default", "sleep";
	212	pinctrl-0 = <&blsp1_i2c2_default>;
	213	pinctrl-1 = <&blsp1_i2c2_sleep>;
	214	#address-cells = <1>;
	215	#size-cells = <0>;
	216	status = "disabled";
	217	};
	218
84361086	219	msmgpio: pinctrl@1010000 {
4558e9b3 SB	220	compatible = "qcom,msm8996-pinctrl";
	221	reg = <0x01010000 0x300000>;
	222	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	223	gpio-controller;
	224	#gpio-cells = <2>;
	225	interrupt-controller;
	226	#interrupt-cells = <2>;
	227	};
	228
	229	timer@09840000 {
	230	#address-cells = <1>;
	231	#size-cells = <1>;
	232	ranges;
	233	compatible = "arm,armv7-timer-mem";
	234	reg = <0x09840000 0x1000>;
	235	clock-frequency = <19200000>;
	236
	237	frame@9850000 {
	238	frame-number = <0>;
	239	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
	240	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	241	reg = <0x09850000 0x1000>,
	242	<0x09860000 0x1000>;
	243	};
	244
	245	frame@9870000 {
	246	frame-number = <1>;
	247	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	248	reg = <0x09870000 0x1000>;
	249	status = "disabled";
	250	};
	251
	252	frame@9880000 {
	253	frame-number = <2>;
	254	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	255	reg = <0x09880000 0x1000>;
	256	status = "disabled";
	257	};
	258
	259	frame@9890000 {
	260	frame-number = <3>;
	261	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	262	reg = <0x09890000 0x1000>;
	263	status = "disabled";
	264	};
	265
	266	frame@98a0000 {
	267	frame-number = <4>;
	268	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	269	reg = <0x098a0000 0x1000>;
	270	status = "disabled";
	271	};
	272
	273	frame@98b0000 {
	274	frame-number = <5>;
	275	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	276	reg = <0x098b0000 0x1000>;
	277	status = "disabled";
	278	};
	279
	280	frame@98c0000 {
	281	frame-number = <6>;
	282	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	283	reg = <0x098c0000 0x1000>;
284	status = "disabled";
285	};
286	};
287
288	spmi_bus: qcom,spmi@400f000 {
289	compatible = "qcom,spmi-pmic-arb";
290	reg = <0x400f000 0x1000>,
291	<0x4400000 0x800000>,
292	<0x4c00000 0x800000>,
293	<0x5800000 0x200000>,
294	<0x400a000 0x002100>;
295	reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
296	interrupt-names = "periph_irq";
297	interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
298	qcom,ee = <0>;
299	qcom,channel = <0>;
300	#address-cells = <2>;
301	#size-cells = <0>;
302	interrupt-controller;
303	#interrupt-cells = <4>;
304	};
305
306	mmcc: clock-controller@8c0000 {
307	compatible = "qcom,mmcc-msm8996";
308	#clock-cells = <1>;
309	#reset-cells = <1>;
a70d7449	310	#power-domain-cells = <1>;
4558e9b3 SB	311	reg = <0x8c0000 0x40000>;
	312	assigned-clocks = <&mmcc MMPLL9_PLL>,
	313	<&mmcc MMPLL1_PLL>,
	314	<&mmcc MMPLL3_PLL>,
	315	<&mmcc MMPLL4_PLL>,
	316	<&mmcc MMPLL5_PLL>;
	317	assigned-clock-rates = <624000000>,
	318	<810000000>,
	319	<980000000>,
	320	<960000000>,
	321	<825000000>;
	322	};
	323	};
	324	};
22e6789f	325	#include "msm8996-pins.dtsi"