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4558e9b3 SB |
1 | /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | */ | |
12 | ||
13 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
14 | #include <dt-bindings/clock/qcom,gcc-msm8996.h> | |
15 | #include <dt-bindings/clock/qcom,mmcc-msm8996.h> | |
16 | ||
17 | / { | |
18 | model = "Qualcomm Technologies, Inc. MSM8996"; | |
19 | ||
20 | interrupt-parent = <&intc>; | |
21 | ||
22 | #address-cells = <2>; | |
23 | #size-cells = <2>; | |
24 | ||
25 | chosen { }; | |
26 | ||
27 | memory { | |
28 | device_type = "memory"; | |
29 | /* We expect the bootloader to fill in the reg */ | |
30 | reg = <0 0 0 0>; | |
31 | }; | |
32 | ||
33 | cpus { | |
34 | #address-cells = <2>; | |
35 | #size-cells = <0>; | |
36 | ||
37 | CPU0: cpu@0 { | |
38 | device_type = "cpu"; | |
39 | compatible = "qcom,kryo"; | |
40 | reg = <0x0 0x0>; | |
41 | enable-method = "psci"; | |
42 | next-level-cache = <&L2_0>; | |
43 | L2_0: l2-cache { | |
44 | compatible = "cache"; | |
45 | cache-level = <2>; | |
46 | }; | |
47 | }; | |
48 | ||
49 | CPU1: cpu@1 { | |
50 | device_type = "cpu"; | |
51 | compatible = "qcom,kryo"; | |
52 | reg = <0x0 0x1>; | |
53 | enable-method = "psci"; | |
54 | next-level-cache = <&L2_0>; | |
55 | }; | |
56 | ||
57 | CPU2: cpu@100 { | |
58 | device_type = "cpu"; | |
59 | compatible = "qcom,kryo"; | |
60 | reg = <0x0 0x100>; | |
61 | enable-method = "psci"; | |
62 | next-level-cache = <&L2_1>; | |
63 | L2_1: l2-cache { | |
64 | compatible = "cache"; | |
65 | cache-level = <2>; | |
66 | }; | |
67 | }; | |
68 | ||
69 | CPU3: cpu@101 { | |
70 | device_type = "cpu"; | |
71 | compatible = "qcom,kryo"; | |
72 | reg = <0x0 0x101>; | |
73 | enable-method = "psci"; | |
74 | next-level-cache = <&L2_1>; | |
75 | }; | |
76 | ||
77 | cpu-map { | |
78 | cluster0 { | |
79 | core0 { | |
80 | cpu = <&CPU0>; | |
81 | }; | |
82 | ||
83 | core1 { | |
84 | cpu = <&CPU1>; | |
85 | }; | |
86 | }; | |
87 | ||
88 | cluster1 { | |
89 | core0 { | |
90 | cpu = <&CPU2>; | |
91 | }; | |
92 | ||
93 | core1 { | |
94 | cpu = <&CPU3>; | |
95 | }; | |
96 | }; | |
97 | }; | |
98 | }; | |
99 | ||
100 | timer { | |
101 | compatible = "arm,armv8-timer"; | |
102 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
103 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
104 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
105 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
106 | }; | |
107 | ||
108 | clocks { | |
109 | xo_board { | |
110 | compatible = "fixed-clock"; | |
111 | #clock-cells = <0>; | |
112 | clock-frequency = <19200000>; | |
113 | clock-output-names = "xo_board"; | |
114 | }; | |
115 | ||
116 | sleep_clk { | |
117 | compatible = "fixed-clock"; | |
118 | #clock-cells = <0>; | |
119 | clock-frequency = <32764>; | |
120 | clock-output-names = "sleep_clk"; | |
121 | }; | |
122 | }; | |
123 | ||
124 | psci { | |
125 | compatible = "arm,psci-1.0"; | |
126 | method = "smc"; | |
127 | }; | |
128 | ||
129 | soc: soc { | |
130 | #address-cells = <1>; | |
131 | #size-cells = <1>; | |
132 | ranges = <0 0 0 0xffffffff>; | |
133 | compatible = "simple-bus"; | |
134 | ||
135 | intc: interrupt-controller@9bc0000 { | |
136 | compatible = "arm,gic-v3"; | |
137 | #interrupt-cells = <3>; | |
138 | interrupt-controller; | |
139 | #redistributor-regions = <1>; | |
140 | redistributor-stride = <0x0 0x40000>; | |
141 | reg = <0x09bc0000 0x10000>, | |
142 | <0x09c00000 0x100000>; | |
143 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
144 | }; | |
145 | ||
146 | gcc: clock-controller@300000 { | |
147 | compatible = "qcom,gcc-msm8996"; | |
148 | #clock-cells = <1>; | |
149 | #reset-cells = <1>; | |
a70d7449 | 150 | #power-domain-cells = <1>; |
4558e9b3 SB |
151 | reg = <0x300000 0x90000>; |
152 | }; | |
153 | ||
604677b4 SK |
154 | blsp1_spi0: spi@07575000 { |
155 | compatible = "qcom,spi-qup-v2.2.1"; | |
156 | reg = <0x07575000 0x600>; | |
157 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
158 | clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, | |
159 | <&gcc GCC_BLSP1_AHB_CLK>; | |
160 | clock-names = "core", "iface"; | |
161 | pinctrl-names = "default", "sleep"; | |
162 | pinctrl-0 = <&blsp1_spi0_default>; | |
163 | pinctrl-1 = <&blsp1_spi0_sleep>; | |
164 | #address-cells = <1>; | |
165 | #size-cells = <0>; | |
166 | status = "disabled"; | |
167 | }; | |
168 | ||
bf5443bc SK |
169 | blsp2_i2c0: i2c@075b5000 { |
170 | compatible = "qcom,i2c-qup-v2.2.1"; | |
171 | reg = <0x075b5000 0x1000>; | |
172 | interrupts = <GIC_SPI 101 0>; | |
173 | clocks = <&gcc GCC_BLSP2_AHB_CLK>, | |
174 | <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; | |
175 | clock-names = "iface", "core"; | |
176 | pinctrl-names = "default", "sleep"; | |
177 | pinctrl-0 = <&blsp2_i2c0_default>; | |
178 | pinctrl-1 = <&blsp2_i2c0_sleep>; | |
179 | #address-cells = <1>; | |
180 | #size-cells = <0>; | |
181 | status = "disabled"; | |
182 | }; | |
183 | ||
4558e9b3 SB |
184 | blsp2_uart1: serial@75b0000 { |
185 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
186 | reg = <0x75b0000 0x1000>; | |
187 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
188 | clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, | |
189 | <&gcc GCC_BLSP2_AHB_CLK>; | |
190 | clock-names = "core", "iface"; | |
191 | status = "disabled"; | |
192 | }; | |
193 | ||
d41d0cee SK |
194 | blsp2_i2c1: i2c@075b6000 { |
195 | compatible = "qcom,i2c-qup-v2.2.1"; | |
196 | reg = <0x075b6000 0x1000>; | |
197 | interrupts = <GIC_SPI 102 0>; | |
198 | clocks = <&gcc GCC_BLSP2_AHB_CLK>, | |
199 | <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; | |
200 | clock-names = "iface", "core"; | |
201 | pinctrl-names = "default", "sleep"; | |
202 | pinctrl-0 = <&blsp2_i2c1_default>; | |
203 | pinctrl-1 = <&blsp2_i2c1_sleep>; | |
204 | #address-cells = <1>; | |
205 | #size-cells = <0>; | |
206 | status = "disabled"; | |
207 | }; | |
208 | ||
fda48e61 SK |
209 | blsp2_uart2: serial@75b1000 { |
210 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
211 | reg = <0x075b1000 0x1000>; | |
212 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
213 | clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, | |
214 | <&gcc GCC_BLSP2_AHB_CLK>; | |
215 | clock-names = "core", "iface"; | |
216 | status = "disabled"; | |
217 | }; | |
218 | ||
21a40384 SK |
219 | blsp1_i2c2: i2c@07577000 { |
220 | compatible = "qcom,i2c-qup-v2.2.1"; | |
221 | reg = <0x07577000 0x1000>; | |
222 | interrupts = <GIC_SPI 97 0>; | |
223 | clocks = <&gcc GCC_BLSP1_AHB_CLK>, | |
224 | <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; | |
225 | clock-names = "iface", "core"; | |
226 | pinctrl-names = "default", "sleep"; | |
227 | pinctrl-0 = <&blsp1_i2c2_default>; | |
228 | pinctrl-1 = <&blsp1_i2c2_sleep>; | |
229 | #address-cells = <1>; | |
230 | #size-cells = <0>; | |
231 | status = "disabled"; | |
232 | }; | |
233 | ||
db6c8c83 SK |
234 | blsp2_spi5: spi@075ba000{ |
235 | compatible = "qcom,spi-qup-v2.2.1"; | |
236 | reg = <0x075ba000 0x600>; | |
237 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
238 | clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, | |
239 | <&gcc GCC_BLSP2_AHB_CLK>; | |
240 | clock-names = "core", "iface"; | |
241 | pinctrl-names = "default", "sleep"; | |
242 | pinctrl-0 = <&blsp2_spi5_default>; | |
243 | pinctrl-1 = <&blsp2_spi5_sleep>; | |
244 | #address-cells = <1>; | |
245 | #size-cells = <0>; | |
246 | status = "disabled"; | |
247 | }; | |
248 | ||
a6702798 SK |
249 | sdhc2: sdhci@74a4900 { |
250 | status = "disabled"; | |
251 | compatible = "qcom,sdhci-msm-v4"; | |
252 | reg = <0x74a4900 0x314>, <0x74a4000 0x800>; | |
253 | reg-names = "hc_mem", "core_mem"; | |
254 | ||
255 | interrupts = <0 125 0>, <0 221 0>; | |
256 | interrupt-names = "hc_irq", "pwr_irq"; | |
257 | ||
258 | clock-names = "iface", "core"; | |
259 | clocks = <&gcc GCC_SDCC2_AHB_CLK>, | |
260 | <&gcc GCC_SDCC2_APPS_CLK>; | |
261 | bus-width = <4>; | |
262 | }; | |
263 | ||
84361086 | 264 | msmgpio: pinctrl@1010000 { |
4558e9b3 SB |
265 | compatible = "qcom,msm8996-pinctrl"; |
266 | reg = <0x01010000 0x300000>; | |
267 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
268 | gpio-controller; | |
269 | #gpio-cells = <2>; | |
270 | interrupt-controller; | |
271 | #interrupt-cells = <2>; | |
272 | }; | |
273 | ||
274 | timer@09840000 { | |
275 | #address-cells = <1>; | |
276 | #size-cells = <1>; | |
277 | ranges; | |
278 | compatible = "arm,armv7-timer-mem"; | |
279 | reg = <0x09840000 0x1000>; | |
280 | clock-frequency = <19200000>; | |
281 | ||
282 | frame@9850000 { | |
283 | frame-number = <0>; | |
284 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, | |
285 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
286 | reg = <0x09850000 0x1000>, | |
287 | <0x09860000 0x1000>; | |
288 | }; | |
289 | ||
290 | frame@9870000 { | |
291 | frame-number = <1>; | |
292 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
293 | reg = <0x09870000 0x1000>; | |
294 | status = "disabled"; | |
295 | }; | |
296 | ||
297 | frame@9880000 { | |
298 | frame-number = <2>; | |
299 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
300 | reg = <0x09880000 0x1000>; | |
301 | status = "disabled"; | |
302 | }; | |
303 | ||
304 | frame@9890000 { | |
305 | frame-number = <3>; | |
306 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
307 | reg = <0x09890000 0x1000>; | |
308 | status = "disabled"; | |
309 | }; | |
310 | ||
311 | frame@98a0000 { | |
312 | frame-number = <4>; | |
313 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
314 | reg = <0x098a0000 0x1000>; | |
315 | status = "disabled"; | |
316 | }; | |
317 | ||
318 | frame@98b0000 { | |
319 | frame-number = <5>; | |
320 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
321 | reg = <0x098b0000 0x1000>; | |
322 | status = "disabled"; | |
323 | }; | |
324 | ||
325 | frame@98c0000 { | |
326 | frame-number = <6>; | |
327 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
328 | reg = <0x098c0000 0x1000>; | |
329 | status = "disabled"; | |
330 | }; | |
331 | }; | |
332 | ||
333 | spmi_bus: qcom,spmi@400f000 { | |
334 | compatible = "qcom,spmi-pmic-arb"; | |
335 | reg = <0x400f000 0x1000>, | |
336 | <0x4400000 0x800000>, | |
337 | <0x4c00000 0x800000>, | |
338 | <0x5800000 0x200000>, | |
339 | <0x400a000 0x002100>; | |
340 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; | |
341 | interrupt-names = "periph_irq"; | |
342 | interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>; | |
343 | qcom,ee = <0>; | |
344 | qcom,channel = <0>; | |
345 | #address-cells = <2>; | |
346 | #size-cells = <0>; | |
347 | interrupt-controller; | |
348 | #interrupt-cells = <4>; | |
349 | }; | |
350 | ||
351 | mmcc: clock-controller@8c0000 { | |
352 | compatible = "qcom,mmcc-msm8996"; | |
353 | #clock-cells = <1>; | |
354 | #reset-cells = <1>; | |
a70d7449 | 355 | #power-domain-cells = <1>; |
4558e9b3 SB |
356 | reg = <0x8c0000 0x40000>; |
357 | assigned-clocks = <&mmcc MMPLL9_PLL>, | |
358 | <&mmcc MMPLL1_PLL>, | |
359 | <&mmcc MMPLL3_PLL>, | |
360 | <&mmcc MMPLL4_PLL>, | |
361 | <&mmcc MMPLL5_PLL>; | |
362 | assigned-clock-rates = <624000000>, | |
363 | <810000000>, | |
364 | <980000000>, | |
365 | <960000000>, | |
366 | <825000000>; | |
367 | }; | |
368 | }; | |
369 | }; | |
22e6789f | 370 | #include "msm8996-pins.dtsi" |