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1561f207 SH |
1 | /* |
2 | * Device Tree Source for the r8a7796 SoC | |
3 | * | |
4 | * Copyright (C) 2016 Renesas Electronics Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <dt-bindings/clock/r8a7796-cpg-mssr.h> | |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
56aebae0 | 13 | #include <dt-bindings/power/r8a7796-sysc.h> |
1561f207 SH |
14 | |
15 | / { | |
16 | compatible = "renesas,r8a7796"; | |
17 | #address-cells = <2>; | |
18 | #size-cells = <2>; | |
19 | ||
20 | psci { | |
21 | compatible = "arm,psci-0.2"; | |
22 | method = "smc"; | |
23 | }; | |
24 | ||
25 | cpus { | |
26 | #address-cells = <1>; | |
27 | #size-cells = <0>; | |
28 | ||
29 | /* 1 core only at this point */ | |
30 | a57_0: cpu@0 { | |
31 | compatible = "arm,cortex-a57", "arm,armv8"; | |
32 | reg = <0x0>; | |
33 | device_type = "cpu"; | |
56aebae0 | 34 | power-domains = <&sysc R8A7796_PD_CA57_CPU0>; |
1561f207 SH |
35 | next-level-cache = <&L2_CA57>; |
36 | enable-method = "psci"; | |
37 | }; | |
38 | ||
39 | L2_CA57: cache-controller@0 { | |
40 | compatible = "cache"; | |
41 | reg = <0>; | |
56aebae0 | 42 | power-domains = <&sysc R8A7796_PD_CA57_SCU>; |
1561f207 SH |
43 | cache-unified; |
44 | cache-level = <2>; | |
45 | }; | |
46 | }; | |
47 | ||
48 | extal_clk: extal { | |
49 | compatible = "fixed-clock"; | |
50 | #clock-cells = <0>; | |
51 | /* This value must be overridden by the board */ | |
52 | clock-frequency = <0>; | |
53 | }; | |
54 | ||
55 | extalr_clk: extalr { | |
56 | compatible = "fixed-clock"; | |
57 | #clock-cells = <0>; | |
58 | /* This value must be overridden by the board */ | |
59 | clock-frequency = <0>; | |
60 | }; | |
61 | ||
62 | /* External SCIF clock - to be overridden by boards that provide it */ | |
63 | scif_clk: scif { | |
64 | compatible = "fixed-clock"; | |
65 | #clock-cells = <0>; | |
66 | clock-frequency = <0>; | |
67 | }; | |
68 | ||
69 | soc { | |
70 | compatible = "simple-bus"; | |
71 | interrupt-parent = <&gic>; | |
72 | #address-cells = <2>; | |
73 | #size-cells = <2>; | |
74 | ranges; | |
75 | ||
76 | gic: interrupt-controller@f1010000 { | |
77 | compatible = "arm,gic-400"; | |
78 | #interrupt-cells = <3>; | |
79 | #address-cells = <0>; | |
80 | interrupt-controller; | |
81 | reg = <0x0 0xf1010000 0 0x1000>, | |
82 | <0x0 0xf1020000 0 0x20000>, | |
83 | <0x0 0xf1040000 0 0x20000>, | |
84 | <0x0 0xf1060000 0 0x20000>; | |
85 | interrupts = <GIC_PPI 9 | |
86 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; | |
87 | }; | |
88 | ||
89 | timer { | |
90 | compatible = "arm,armv8-timer"; | |
91 | interrupts = <GIC_PPI 13 | |
92 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
93 | <GIC_PPI 14 | |
94 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
95 | <GIC_PPI 11 | |
96 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
97 | <GIC_PPI 10 | |
98 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; | |
99 | }; | |
100 | ||
c8ce8007 GU |
101 | wdt0: watchdog@e6020000 { |
102 | compatible = "renesas,r8a7796-wdt", | |
103 | "renesas,rcar-gen3-wdt"; | |
104 | reg = <0 0xe6020000 0 0x0c>; | |
105 | clocks = <&cpg CPG_MOD 402>; | |
106 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; | |
107 | status = "disabled"; | |
108 | }; | |
109 | ||
1561f207 SH |
110 | cpg: clock-controller@e6150000 { |
111 | compatible = "renesas,r8a7796-cpg-mssr"; | |
112 | reg = <0 0xe6150000 0 0x1000>; | |
113 | clocks = <&extal_clk>, <&extalr_clk>; | |
114 | clock-names = "extal", "extalr"; | |
115 | #clock-cells = <2>; | |
116 | #power-domain-cells = <0>; | |
117 | }; | |
118 | ||
56aebae0 GU |
119 | sysc: system-controller@e6180000 { |
120 | compatible = "renesas,r8a7796-sysc"; | |
121 | reg = <0 0xe6180000 0 0x0400>; | |
122 | #power-domain-cells = <1>; | |
123 | }; | |
124 | ||
1561f207 SH |
125 | scif2: serial@e6e88000 { |
126 | compatible = "renesas,scif-r8a7796", | |
127 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
128 | reg = <0 0xe6e88000 0 64>; | |
129 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
130 | clocks = <&cpg CPG_MOD 310>, | |
131 | <&cpg CPG_CORE R8A7796_CLK_S3D1>, | |
132 | <&scif_clk>; | |
133 | clock-names = "fck", "brg_int", "scif_clk"; | |
a9003187 | 134 | power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
1561f207 SH |
135 | status = "disabled"; |
136 | }; | |
137 | }; | |
138 | }; |