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arm64: dts: rockchip: fix i2c resource error of rk3368
[deliverable/linux.git] / arch / arm64 / boot / dts / rockchip / rk3368.dtsi
CommitLineData
b790c2ca
HS		 1/*
2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/clock/rk3368-cru.h>
44#include <dt-bindings/gpio/gpio.h>
45#include <dt-bindings/interrupt-controller/irq.h>
46#include <dt-bindings/interrupt-controller/arm-gic.h>
47#include <dt-bindings/pinctrl/rockchip.h>
2e9e2863 48#include <dt-bindings/soc/rockchip,boot-mode.h>
f990238f 49#include <dt-bindings/thermal/thermal.h>
b790c2ca
HS		 50
51/ {
52 compatible = "rockchip,rk3368";
53 interrupt-parent = <&gic>;
54 #address-cells = <2>;
55 #size-cells = <2>;
56
57 aliases {
ff08868e 58 ethernet0 = &gmac;
b790c2ca
HS		 59 i2c0 = &i2c0;
60 i2c1 = &i2c1;
61 i2c2 = &i2c2;
62 i2c3 = &i2c3;
63 i2c4 = &i2c4;
64 i2c5 = &i2c5;
65 serial0 = &uart0;
66 serial1 = &uart1;
67 serial2 = &uart2;
68 serial3 = &uart3;
69 serial4 = &uart4;
70 spi0 = &spi0;
71 spi1 = &spi1;
72 spi2 = &spi2;
73 };
74
75 cpus {
76 #address-cells = <0x2>;
77 #size-cells = <0x0>;
78
79 cpu-map {
80 cluster0 {
81 core0 {
82 cpu = <&cpu_b0>;
83 };
84 core1 {
85 cpu = <&cpu_b1>;
86 };
87 core2 {
88 cpu = <&cpu_b2>;
89 };
90 core3 {
91 cpu = <&cpu_b3>;
92 };
93 };
94
95 cluster1 {
96 core0 {
97 cpu = <&cpu_l0>;
98 };
99 core1 {
100 cpu = <&cpu_l1>;
101 };
102 core2 {
103 cpu = <&cpu_l2>;
104 };
105 core3 {
106 cpu = <&cpu_l3>;
107 };
108 };
109 };
110
111 idle-states {
a13f18f5 112 entry-method = "psci";
b790c2ca
HS		 113
114 cpu_sleep: cpu-sleep-0 {
115 compatible = "arm,idle-state";
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
120 };
121 };
122
123 cpu_l0: cpu@0 {
124 device_type = "cpu";
125 compatible = "arm,cortex-a53", "arm,armv8";
126 reg = <0x0 0x0>;
127 cpu-idle-states = <&cpu_sleep>;
128 enable-method = "psci";
f990238f
CW		 129
130 #cooling-cells = <2>; /* min followed by max */
b790c2ca
HS		 131 };
132
133 cpu_l1: cpu@1 {
134 device_type = "cpu";
135 compatible = "arm,cortex-a53", "arm,armv8";
136 reg = <0x0 0x1>;
137 cpu-idle-states = <&cpu_sleep>;
138 enable-method = "psci";
139 };
140
141 cpu_l2: cpu@2 {
142 device_type = "cpu";
143 compatible = "arm,cortex-a53", "arm,armv8";
144 reg = <0x0 0x2>;
145 cpu-idle-states = <&cpu_sleep>;
146 enable-method = "psci";
147 };
148
149 cpu_l3: cpu@3 {
150 device_type = "cpu";
151 compatible = "arm,cortex-a53", "arm,armv8";
152 reg = <0x0 0x3>;
153 cpu-idle-states = <&cpu_sleep>;
154 enable-method = "psci";
155 };
156
157 cpu_b0: cpu@100 {
158 device_type = "cpu";
159 compatible = "arm,cortex-a53", "arm,armv8";
160 reg = <0x0 0x100>;
161 cpu-idle-states = <&cpu_sleep>;
162 enable-method = "psci";
f990238f
CW		 163
164 #cooling-cells = <2>; /* min followed by max */
b790c2ca
HS		 165 };
166
167 cpu_b1: cpu@101 {
168 device_type = "cpu";
169 compatible = "arm,cortex-a53", "arm,armv8";
170 reg = <0x0 0x101>;
171 cpu-idle-states = <&cpu_sleep>;
172 enable-method = "psci";
173 };
174
175 cpu_b2: cpu@102 {
176 device_type = "cpu";
177 compatible = "arm,cortex-a53", "arm,armv8";
178 reg = <0x0 0x102>;
179 cpu-idle-states = <&cpu_sleep>;
180 enable-method = "psci";
181 };
182
183 cpu_b3: cpu@103 {
184 device_type = "cpu";
185 compatible = "arm,cortex-a53", "arm,armv8";
186 reg = <0x0 0x103>;
187 cpu-idle-states = <&cpu_sleep>;
188 enable-method = "psci";
189 };
190 };
191
192 arm-pmu {
193 compatible = "arm,armv8-pmuv3";
194 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
203 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
204 <&cpu_b2>, <&cpu_b3>;
205 };
206
207 psci {
208 compatible = "arm,psci-0.2";
209 method = "smc";
210 };
211
212 timer {
213 compatible = "arm,armv8-timer";
214 interrupts = <GIC_PPI 13
215 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
216 <GIC_PPI 14
217 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
218 <GIC_PPI 11
219 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
220 <GIC_PPI 10
221 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
222 };
223
224 xin24m: oscillator {
225 compatible = "fixed-clock";
226 clock-frequency = <24000000>;
227 clock-output-names = "xin24m";
228 #clock-cells = <0>;
229 };
230
231 sdmmc: dwmmc@ff0c0000 {
232 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
233 reg = <0x0 0xff0c0000 0x0 0x4000>;
234 clock-freq-min-max = <400000 150000000>;
90191625
SL		 235 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
236 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
237 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
b790c2ca
HS		 238 fifo-depth = <0x100>;
239 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
240 status = "disabled";
241 };
242
243 sdio0: dwmmc@ff0d0000 {
244 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
245 reg = <0x0 0xff0d0000 0x0 0x4000>;
246 clock-freq-min-max = <400000 150000000>;
247 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
248 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
249 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
250 fifo-depth = <0x100>;
251 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
252 status = "disabled";
253 };
254
255 emmc: dwmmc@ff0f0000 {
256 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
257 reg = <0x0 0xff0f0000 0x0 0x4000>;
258 clock-freq-min-max = <400000 150000000>;
90191625
SL		 259 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
260 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
261 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
b790c2ca
HS		 262 fifo-depth = <0x100>;
263 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
264 status = "disabled";
265 };
266
267 saradc: saradc@ff100000 {
268 compatible = "rockchip,saradc";
269 reg = <0x0 0xff100000 0x0 0x100>;
270 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
271 #io-channel-cells = <1>;
272 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
273 clock-names = "saradc", "apb_pclk";
274 status = "disabled";
275 };
276
277 spi0: spi@ff110000 {
278 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
279 reg = <0x0 0xff110000 0x0 0x1000>;
280 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
281 clock-names = "spiclk", "apb_pclk";
282 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
285 #address-cells = <1>;
286 #size-cells = <0>;
287 status = "disabled";
288 };
289
290 spi1: spi@ff120000 {
291 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
292 reg = <0x0 0xff120000 0x0 0x1000>;
293 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
294 clock-names = "spiclk", "apb_pclk";
295 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
298 #address-cells = <1>;
299 #size-cells = <0>;
300 status = "disabled";
301 };
302
303 spi2: spi@ff130000 {
304 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
305 reg = <0x0 0xff130000 0x0 0x1000>;
306 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
307 clock-names = "spiclk", "apb_pclk";
308 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 status = "disabled";
314 };
315
45380475 316 i2c2: i2c@ff140000 {
b790c2ca
HS		 317 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
318 reg = <0x0 0xff140000 0x0 0x1000>;
319 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
321 #size-cells = <0>;
322 clock-names = "i2c";
45380475 323 clocks = <&cru PCLK_I2C2>;
b790c2ca 324 pinctrl-names = "default";
45380475 325 pinctrl-0 = <&i2c2_xfer>;
b790c2ca
HS		 326 status = "disabled";
327 };
328
329 i2c3: i2c@ff150000 {
330 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
331 reg = <0x0 0xff150000 0x0 0x1000>;
332 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
333 #address-cells = <1>;
334 #size-cells = <0>;
335 clock-names = "i2c";
336 clocks = <&cru PCLK_I2C3>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2c3_xfer>;
339 status = "disabled";
340 };
341
342 i2c4: i2c@ff160000 {
343 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
344 reg = <0x0 0xff160000 0x0 0x1000>;
345 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
347 #size-cells = <0>;
348 clock-names = "i2c";
349 clocks = <&cru PCLK_I2C4>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&i2c4_xfer>;
352 status = "disabled";
353 };
354
355 i2c5: i2c@ff170000 {
356 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
357 reg = <0x0 0xff170000 0x0 0x1000>;
358 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
360 #size-cells = <0>;
361 clock-names = "i2c";
362 clocks = <&cru PCLK_I2C5>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&i2c5_xfer>;
365 status = "disabled";
366 };
367
368 uart0: serial@ff180000 {
369 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
370 reg = <0x0 0xff180000 0x0 0x100>;
371 clock-frequency = <24000000>;
372 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
373 clock-names = "baudclk", "apb_pclk";
374 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
375 reg-shift = <2>;
376 reg-io-width = <4>;
377 status = "disabled";
378 };
379
380 uart1: serial@ff190000 {
381 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
382 reg = <0x0 0xff190000 0x0 0x100>;
383 clock-frequency = <24000000>;
384 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
385 clock-names = "baudclk", "apb_pclk";
386 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
387 reg-shift = <2>;
388 reg-io-width = <4>;
389 status = "disabled";
390 };
391
392 uart3: serial@ff1b0000 {
393 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
394 reg = <0x0 0xff1b0000 0x0 0x100>;
395 clock-frequency = <24000000>;
396 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
397 clock-names = "baudclk", "apb_pclk";
398 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
399 reg-shift = <2>;
400 reg-io-width = <4>;
401 status = "disabled";
402 };
403
404 uart4: serial@ff1c0000 {
405 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
406 reg = <0x0 0xff1c0000 0x0 0x100>;
407 clock-frequency = <24000000>;
408 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
409 clock-names = "baudclk", "apb_pclk";
410 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
411 reg-shift = <2>;
412 reg-io-width = <4>;
413 status = "disabled";
414 };
415
f990238f 416 thermal-zones {
6ddf93e0
CW		 417 cpu {
418 polling-delay-passive = <100>; /* milliseconds */
419 polling-delay = <5000>; /* milliseconds */
420
421 thermal-sensors = <&tsadc 0>;
422
423 trips {
424 cpu_alert0: cpu_alert0 {
425 temperature = <75000>; /* millicelsius */
426 hysteresis = <2000>; /* millicelsius */
427 type = "passive";
428 };
429 cpu_alert1: cpu_alert1 {
430 temperature = <80000>; /* millicelsius */
431 hysteresis = <2000>; /* millicelsius */
432 type = "passive";
433 };
434 cpu_crit: cpu_crit {
435 temperature = <95000>; /* millicelsius */
436 hysteresis = <2000>; /* millicelsius */
437 type = "critical";
438 };
439 };
440
441 cooling-maps {
442 map0 {
443 trip = <&cpu_alert0>;
444 cooling-device =
445 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
446 };
447 map1 {
448 trip = <&cpu_alert1>;
449 cooling-device =
450 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
451 };
452 };
453 };
454
455 gpu {
456 polling-delay-passive = <100>; /* milliseconds */
457 polling-delay = <5000>; /* milliseconds */
458
459 thermal-sensors = <&tsadc 1>;
460
461 trips {
462 gpu_alert0: gpu_alert0 {
463 temperature = <80000>; /* millicelsius */
464 hysteresis = <2000>; /* millicelsius */
465 type = "passive";
466 };
467 gpu_crit: gpu_crit {
468 temperature = <115000>; /* millicelsius */
469 hysteresis = <2000>; /* millicelsius */
470 type = "critical";
471 };
472 };
473
474 cooling-maps {
475 map0 {
476 trip = <&gpu_alert0>;
477 cooling-device =
478 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
479 };
480 };
481 };
f990238f
CW		 482 };
483
484 tsadc: tsadc@ff280000 {
485 compatible = "rockchip,rk3368-tsadc";
486 reg = <0x0 0xff280000 0x0 0x100>;
487 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
489 clock-names = "tsadc", "apb_pclk";
490 resets = <&cru SRST_TSADC>;
491 reset-names = "tsadc-apb";
492 pinctrl-names = "init", "default", "sleep";
493 pinctrl-0 = <&otp_gpio>;
494 pinctrl-1 = <&otp_out>;
495 pinctrl-2 = <&otp_gpio>;
496 #thermal-sensor-cells = <1>;
497 rockchip,hw-tshut-temp = <95000>;
498 status = "disabled";
499 };
500
b790c2ca
HS		 501 gmac: ethernet@ff290000 {
502 compatible = "rockchip,rk3368-gmac";
503 reg = <0x0 0xff290000 0x0 0x10000>;
504 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
505 interrupt-names = "macirq";
506 rockchip,grf = <&grf>;
507 clocks = <&cru SCLK_MAC>,
508 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
509 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
510 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
511 clock-names = "stmmaceth",
512 "mac_clk_rx", "mac_clk_tx",
513 "clk_mac_ref", "clk_mac_refout",
514 "aclk_mac", "pclk_mac";
515 status = "disabled";
516 };
517
518 usb_host0_ehci: usb@ff500000 {
519 compatible = "generic-ehci";
520 reg = <0x0 0xff500000 0x0 0x100>;
521 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&cru HCLK_HOST0>;
523 clock-names = "usbhost";
524 status = "disabled";
525 };
526
527 usb_otg: usb@ff580000 {
528 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
529 "snps,dwc2";
530 reg = <0x0 0xff580000 0x0 0x40000>;
531 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cru HCLK_OTG0>;
533 clock-names = "otg";
534 dr_mode = "otg";
535 g-np-tx-fifo-size = <16>;
536 g-rx-fifo-size = <275>;
537 g-tx-fifo-size = <256 128 128 64 64 32>;
538 g-use-dma;
539 status = "disabled";
540 };
541
542 i2c0: i2c@ff650000 {
543 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
544 reg = <0x0 0xff650000 0x0 0x1000>;
545 clocks = <&cru PCLK_I2C0>;
546 clock-names = "i2c";
547 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&i2c0_xfer>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 status = "disabled";
553 };
554
45380475 555 i2c1: i2c@ff660000 {
b790c2ca
HS		 556 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
557 reg = <0x0 0xff660000 0x0 0x1000>;
558 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
559 #address-cells = <1>;
560 #size-cells = <0>;
561 clock-names = "i2c";
45380475 562 clocks = <&cru PCLK_I2C1>;
b790c2ca 563 pinctrl-names = "default";
45380475 564 pinctrl-0 = <&i2c1_xfer>;
b790c2ca
HS		 565 status = "disabled";
566 };
567
fa54322a
CW		 568 pwm0: pwm@ff680000 {
569 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
570 reg = <0x0 0xff680000 0x0 0x10>;
571 #pwm-cells = <3>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&pwm0_pin>;
574 clocks = <&cru PCLK_PWM1>;
575 clock-names = "pwm";
576 status = "disabled";
577 };
578
579 pwm1: pwm@ff680010 {
580 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
581 reg = <0x0 0xff680010 0x0 0x10>;
582 #pwm-cells = <3>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&pwm1_pin>;
585 clocks = <&cru PCLK_PWM1>;
586 clock-names = "pwm";
587 status = "disabled";
588 };
589
590 pwm2: pwm@ff680020 {
591 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
592 reg = <0x0 0xff680020 0x0 0x10>;
593 #pwm-cells = <3>;
594 clocks = <&cru PCLK_PWM1>;
595 clock-names = "pwm";
596 status = "disabled";
597 };
598
599 pwm3: pwm@ff680030 {
600 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
601 reg = <0x0 0xff680030 0x0 0x10>;
602 #pwm-cells = <3>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&pwm3_pin>;
605 clocks = <&cru PCLK_PWM1>;
606 clock-names = "pwm";
607 status = "disabled";
608 };
609
b790c2ca
HS		 610 uart2: serial@ff690000 {
611 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
612 reg = <0x0 0xff690000 0x0 0x100>;
613 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
614 clock-names = "baudclk", "apb_pclk";
615 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&uart2_xfer>;
618 reg-shift = <2>;
619 reg-io-width = <4>;
620 status = "disabled";
621 };
622
6e7f9f5a
CW		 623 mbox: mbox@ff6b0000 {
624 compatible = "rockchip,rk3368-mailbox";
625 reg = <0x0 0xff6b0000 0x0 0x1000>;
626 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cru PCLK_MAILBOX>;
631 clock-names = "pclk_mailbox";
632 #mbox-cells = <1>;
633 };
634
b790c2ca 635 pmugrf: syscon@ff738000 {
4cca3d94 636 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
b790c2ca 637 reg = <0x0 0xff738000 0x0 0x1000>;
d1ab05ab
HS		 638
639 pmu_io_domains: io-domains {
640 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
641 status = "disabled";
642 };
2e9e2863
AY		 643
644 reboot-mode {
645 compatible = "syscon-reboot-mode";
646 offset = <0x200>;
647 mode-normal = <BOOT_NORMAL>;
648 mode-recovery = <BOOT_RECOVERY>;
649 mode-bootloader = <BOOT_FASTBOOT>;
650 mode-loader = <BOOT_BL_DOWNLOAD>;
651 };
b790c2ca
HS		 652 };
653
654 cru: clock-controller@ff760000 {
655 compatible = "rockchip,rk3368-cru";
656 reg = <0x0 0xff760000 0x0 0x1000>;
657 rockchip,grf = <&grf>;
658 #clock-cells = <1>;
659 #reset-cells = <1>;
660 };
661
662 grf: syscon@ff770000 {
4cca3d94 663 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
b790c2ca 664 reg = <0x0 0xff770000 0x0 0x1000>;
d1ab05ab
HS		 665
666 io_domains: io-domains {
667 compatible = "rockchip,rk3368-io-voltage-domain";
668 status = "disabled";
669 };
b790c2ca
HS		 670 };
671
672 wdt: watchdog@ff800000 {
673 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
674 reg = <0x0 0xff800000 0x0 0x100>;
675 clocks = <&cru PCLK_WDT>;
676 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
677 status = "disabled";
678 };
679
b8084e5b
CW		 680 timer@ff810000 {
681 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
682 reg = <0x0 0xff810000 0x0 0x20>;
683 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
684 };
685
b790c2ca
HS		 686 gic: interrupt-controller@ffb71000 {
687 compatible = "arm,gic-400";
688 interrupt-controller;
689 #interrupt-cells = <3>;
690 #address-cells = <0>;
691
692 reg = <0x0 0xffb71000 0x0 0x1000>,
ad1cfdf5 693 <0x0 0xffb72000 0x0 0x2000>,
b790c2ca
HS		 694 <0x0 0xffb74000 0x0 0x2000>,
695 <0x0 0xffb76000 0x0 0x2000>;
696 interrupts = <GIC_PPI 9
697 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
698 };
699
700 pinctrl: pinctrl {
701 compatible = "rockchip,rk3368-pinctrl";
702 rockchip,grf = <&grf>;
703 rockchip,pmu = <&pmugrf>;
704 #address-cells = <0x2>;
705 #size-cells = <0x2>;
706 ranges;
707
708 gpio0: gpio0@ff750000 {
709 compatible = "rockchip,gpio-bank";
710 reg = <0x0 0xff750000 0x0 0x100>;
711 clocks = <&cru PCLK_GPIO0>;
712 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
713
714 gpio-controller;
715 #gpio-cells = <0x2>;
716
717 interrupt-controller;
718 #interrupt-cells = <0x2>;
719 };
720
721 gpio1: gpio1@ff780000 {
722 compatible = "rockchip,gpio-bank";
723 reg = <0x0 0xff780000 0x0 0x100>;
724 clocks = <&cru PCLK_GPIO1>;
725 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
726
727 gpio-controller;
728 #gpio-cells = <0x2>;
729
730 interrupt-controller;
731 #interrupt-cells = <0x2>;
732 };
733
734 gpio2: gpio2@ff790000 {
735 compatible = "rockchip,gpio-bank";
736 reg = <0x0 0xff790000 0x0 0x100>;
737 clocks = <&cru PCLK_GPIO2>;
738 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
739
740 gpio-controller;
741 #gpio-cells = <0x2>;
742
743 interrupt-controller;
744 #interrupt-cells = <0x2>;
745 };
746
747 gpio3: gpio3@ff7a0000 {
748 compatible = "rockchip,gpio-bank";
749 reg = <0x0 0xff7a0000 0x0 0x100>;
750 clocks = <&cru PCLK_GPIO3>;
751 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
752
753 gpio-controller;
754 #gpio-cells = <0x2>;
755
756 interrupt-controller;
757 #interrupt-cells = <0x2>;
758 };
759
760 pcfg_pull_up: pcfg-pull-up {
761 bias-pull-up;
762 };
763
764 pcfg_pull_down: pcfg-pull-down {
765 bias-pull-down;
766 };
767
768 pcfg_pull_none: pcfg-pull-none {
769 bias-disable;
770 };
771
772 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
773 bias-disable;
774 drive-strength = <12>;
775 };
776
777 emmc {
778 emmc_clk: emmc-clk {
779 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
780 };
781
782 emmc_cmd: emmc-cmd {
783 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
784 };
785
786 emmc_pwr: emmc-pwr {
787 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
788 };
789
790 emmc_bus1: emmc-bus1 {
791 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
792 };
793
794 emmc_bus4: emmc-bus4 {
795 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
796 <1 19 RK_FUNC_2 &pcfg_pull_up>,
797 <1 20 RK_FUNC_2 &pcfg_pull_up>,
798 <1 21 RK_FUNC_2 &pcfg_pull_up>;
799 };
800
801 emmc_bus8: emmc-bus8 {
802 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
803 <1 19 RK_FUNC_2 &pcfg_pull_up>,
804 <1 20 RK_FUNC_2 &pcfg_pull_up>,
805 <1 21 RK_FUNC_2 &pcfg_pull_up>,
806 <1 22 RK_FUNC_2 &pcfg_pull_up>,
807 <1 23 RK_FUNC_2 &pcfg_pull_up>,
808 <1 24 RK_FUNC_2 &pcfg_pull_up>,
809 <1 25 RK_FUNC_2 &pcfg_pull_up>;
810 };
811 };
812
813 gmac {
814 rgmii_pins: rgmii-pins {
815 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
816 <3 24 RK_FUNC_1 &pcfg_pull_none>,
817 <3 19 RK_FUNC_1 &pcfg_pull_none>,
818 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
819 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
820 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
821 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
822 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
823 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
824 <3 15 RK_FUNC_1 &pcfg_pull_none>,
825 <3 16 RK_FUNC_1 &pcfg_pull_none>,
826 <3 17 RK_FUNC_1 &pcfg_pull_none>,
827 <3 18 RK_FUNC_1 &pcfg_pull_none>,
828 <3 25 RK_FUNC_1 &pcfg_pull_none>,
829 <3 20 RK_FUNC_1 &pcfg_pull_none>;
830 };
831
832 rmii_pins: rmii-pins {
833 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
834 <3 24 RK_FUNC_1 &pcfg_pull_none>,
835 <3 19 RK_FUNC_1 &pcfg_pull_none>,
836 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
837 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
838 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
839 <3 15 RK_FUNC_1 &pcfg_pull_none>,
840 <3 16 RK_FUNC_1 &pcfg_pull_none>,
841 <3 20 RK_FUNC_1 &pcfg_pull_none>,
842 <3 21 RK_FUNC_1 &pcfg_pull_none>;
843 };
844 };
845
846 i2c0 {
847 i2c0_xfer: i2c0-xfer {
848 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
849 <0 7 RK_FUNC_1 &pcfg_pull_none>;
850 };
851 };
852
853 i2c1 {
854 i2c1_xfer: i2c1-xfer {
855 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
856 <2 22 RK_FUNC_1 &pcfg_pull_none>;
857 };
858 };
859
860 i2c2 {
861 i2c2_xfer: i2c2-xfer {
862 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
863 <3 31 RK_FUNC_2 &pcfg_pull_none>;
864 };
865 };
866
867 i2c3 {
868 i2c3_xfer: i2c3-xfer {
869 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
870 <1 17 RK_FUNC_1 &pcfg_pull_none>;
871 };
872 };
873
874 i2c4 {
875 i2c4_xfer: i2c4-xfer {
876 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
877 <3 25 RK_FUNC_2 &pcfg_pull_none>;
878 };
879 };
880
881 i2c5 {
882 i2c5_xfer: i2c5-xfer {
883 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
884 <3 27 RK_FUNC_2 &pcfg_pull_none>;
885 };
886 };
887
fa54322a
CW		 888 pwm0 {
889 pwm0_pin: pwm0-pin {
890 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
891 };
892 };
893
894 pwm1 {
895 pwm1_pin: pwm1-pin {
896 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
897 };
898 };
899
900 pwm3 {
901 pwm3_pin: pwm3-pin {
902 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
903 };
904 };
905
b790c2ca
HS		 906 sdio0 {
907 sdio0_bus1: sdio0-bus1 {
908 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
909 };
910
911 sdio0_bus4: sdio0-bus4 {
912 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
913 <2 29 RK_FUNC_1 &pcfg_pull_up>,
914 <2 30 RK_FUNC_1 &pcfg_pull_up>,
915 <2 31 RK_FUNC_1 &pcfg_pull_up>;
916 };
917
918 sdio0_cmd: sdio0-cmd {
919 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
920 };
921
922 sdio0_clk: sdio0-clk {
923 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
924 };
925
926 sdio0_cd: sdio0-cd {
927 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
928 };
929
930 sdio0_wp: sdio0-wp {
931 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
932 };
933
934 sdio0_pwr: sdio0-pwr {
935 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
936 };
937
938 sdio0_bkpwr: sdio0-bkpwr {
939 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
940 };
941
942 sdio0_int: sdio0-int {
943 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
944 };
945 };
946
947 sdmmc {
948 sdmmc_clk: sdmmc-clk {
949 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
950 };
951
952 sdmmc_cmd: sdmmc-cmd {
953 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
954 };
955
8fc5abd4 956 sdmmc_cd: sdmmc-cd {
b790c2ca
HS		 957 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
958 };
959
960 sdmmc_bus1: sdmmc-bus1 {
961 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
962 };
963
964 sdmmc_bus4: sdmmc-bus4 {
965 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
966 <2 6 RK_FUNC_1 &pcfg_pull_up>,
967 <2 7 RK_FUNC_1 &pcfg_pull_up>,
968 <2 8 RK_FUNC_1 &pcfg_pull_up>;
969 };
970 };
971
972 spi0 {
973 spi0_clk: spi0-clk {
974 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
975 };
976 spi0_cs0: spi0-cs0 {
977 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
978 };
979 spi0_cs1: spi0-cs1 {
980 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
981 };
982 spi0_tx: spi0-tx {
983 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
984 };
985 spi0_rx: spi0-rx {
986 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
987 };
988 };
989
990 spi1 {
991 spi1_clk: spi1-clk {
992 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
993 };
994 spi1_cs0: spi1-cs0 {
995 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
996 };
997 spi1_cs1: spi1-cs1 {
998 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
999 };
1000 spi1_rx: spi1-rx {
1001 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1002 };
1003 spi1_tx: spi1-tx {
1004 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1005 };
1006 };
1007
1008 spi2 {
1009 spi2_clk: spi2-clk {
1010 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1011 };
1012 spi2_cs0: spi2-cs0 {
1013 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1014 };
1015 spi2_rx: spi2-rx {
1016 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1017 };
1018 spi2_tx: spi2-tx {
1019 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1020 };
1021 };
1022
f990238f
CW		 1023 tsadc {
1024 otp_gpio: otp-gpio {
04317584 1025 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
f990238f
CW		 1026 };
1027
1028 otp_out: otp-out {
04317584 1029 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
f990238f
CW		 1030 };
1031 };
1032
b790c2ca
HS		 1033 uart0 {
1034 uart0_xfer: uart0-xfer {
1035 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1036 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1037 };
1038
1039 uart0_cts: uart0-cts {
1040 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1041 };
1042
1043 uart0_rts: uart0-rts {
1044 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1045 };
1046 };
1047
1048 uart1 {
1049 uart1_xfer: uart1-xfer {
1050 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1051 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1052 };
1053
1054 uart1_cts: uart1-cts {
1055 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1056 };
1057
1058 uart1_rts: uart1-rts {
1059 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1060 };
1061 };
1062
1063 uart2 {
1064 uart2_xfer: uart2-xfer {
1065 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1066 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1067 };
1068 /* no rts / cts for uart2 */
1069 };
1070
1071 uart3 {
1072 uart3_xfer: uart3-xfer {
1073 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1074 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1075 };
1076
1077 uart3_cts: uart3-cts {
1078 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1079 };
1080
1081 uart3_rts: uart3-rts {
1082 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1083 };
1084 };
1085
1086 uart4 {
1087 uart4_xfer: uart4-xfer {
1088 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1089 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1090 };
1091
1092 uart4_cts: uart4-cts {
1093 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1094 };
1095
1096 uart4_rts: uart4-rts {
1097 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1098 };
1099 };
1100 };
1101};
Linux kernel - Deliverables
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