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arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399
[deliverable/linux.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
CommitLineData
f048b9a4
JX		 1/*
2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/clock/rk3399-cru.h>
44#include <dt-bindings/gpio/gpio.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/interrupt-controller/irq.h>
47#include <dt-bindings/pinctrl/rockchip.h>
95c27ba7 48#include <dt-bindings/thermal/thermal.h>
f048b9a4
JX		 49
50/ {
51 compatible = "rockchip,rk3399";
52
53 interrupt-parent = <&gic>;
54 #address-cells = <2>;
55 #size-cells = <2>;
56
57 aliases {
69e5a8fe
DW		 58 i2c0 = &i2c0;
59 i2c1 = &i2c1;
60 i2c2 = &i2c2;
61 i2c3 = &i2c3;
62 i2c4 = &i2c4;
63 i2c5 = &i2c5;
64 i2c6 = &i2c6;
65 i2c7 = &i2c7;
66 i2c8 = &i2c8;
f048b9a4
JX		 67 serial0 = &uart0;
68 serial1 = &uart1;
69 serial2 = &uart2;
70 serial3 = &uart3;
71 serial4 = &uart4;
72 };
73
74 cpus {
75 #address-cells = <2>;
76 #size-cells = <0>;
77
78 cpu-map {
79 cluster0 {
80 core0 {
81 cpu = <&cpu_l0>;
82 };
83 core1 {
84 cpu = <&cpu_l1>;
85 };
86 core2 {
87 cpu = <&cpu_l2>;
88 };
89 core3 {
90 cpu = <&cpu_l3>;
91 };
92 };
93
94 cluster1 {
95 core0 {
96 cpu = <&cpu_b0>;
97 };
98 core1 {
99 cpu = <&cpu_b1>;
100 };
101 };
102 };
103
104 cpu_l0: cpu@0 {
105 device_type = "cpu";
106 compatible = "arm,cortex-a53", "arm,armv8";
107 reg = <0x0 0x0>;
108 enable-method = "psci";
109 #cooling-cells = <2>; /* min followed by max */
110 clocks = <&cru ARMCLKL>;
111 };
112
113 cpu_l1: cpu@1 {
114 device_type = "cpu";
115 compatible = "arm,cortex-a53", "arm,armv8";
116 reg = <0x0 0x1>;
117 enable-method = "psci";
118 clocks = <&cru ARMCLKL>;
119 };
120
121 cpu_l2: cpu@2 {
122 device_type = "cpu";
123 compatible = "arm,cortex-a53", "arm,armv8";
124 reg = <0x0 0x2>;
125 enable-method = "psci";
126 clocks = <&cru ARMCLKL>;
127 };
128
129 cpu_l3: cpu@3 {
130 device_type = "cpu";
131 compatible = "arm,cortex-a53", "arm,armv8";
132 reg = <0x0 0x3>;
133 enable-method = "psci";
134 clocks = <&cru ARMCLKL>;
135 };
136
137 cpu_b0: cpu@100 {
138 device_type = "cpu";
139 compatible = "arm,cortex-a72", "arm,armv8";
140 reg = <0x0 0x100>;
141 enable-method = "psci";
142 #cooling-cells = <2>; /* min followed by max */
143 clocks = <&cru ARMCLKB>;
144 };
145
146 cpu_b1: cpu@101 {
147 device_type = "cpu";
148 compatible = "arm,cortex-a72", "arm,armv8";
149 reg = <0x0 0x101>;
150 enable-method = "psci";
151 clocks = <&cru ARMCLKB>;
152 };
153 };
154
155 psci {
156 compatible = "arm,psci-1.0";
157 method = "smc";
158 };
159
160 timer {
161 compatible = "arm,armv8-timer";
162 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
163 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
164 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
165 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
166 };
167
168 xin24m: xin24m {
169 compatible = "fixed-clock";
170 clock-frequency = <24000000>;
171 clock-output-names = "xin24m";
172 #clock-cells = <0>;
173 };
174
175 amba {
176 compatible = "arm,amba-bus";
177 #address-cells = <2>;
178 #size-cells = <2>;
179 ranges;
180
181 dmac_bus: dma-controller@ff6d0000 {
182 compatible = "arm,pl330", "arm,primecell";
183 reg = <0x0 0xff6d0000 0x0 0x4000>;
184 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
186 #dma-cells = <1>;
187 clocks = <&cru ACLK_DMAC0_PERILP>;
188 clock-names = "apb_pclk";
189 };
190
191 dmac_peri: dma-controller@ff6e0000 {
192 compatible = "arm,pl330", "arm,primecell";
193 reg = <0x0 0xff6e0000 0x0 0x4000>;
194 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
196 #dma-cells = <1>;
197 clocks = <&cru ACLK_DMAC1_PERILP>;
198 clock-names = "apb_pclk";
199 };
200 };
201
202 sdio0: dwmmc@fe310000 {
203 compatible = "rockchip,rk3399-dw-mshc",
204 "rockchip,rk3288-dw-mshc";
205 reg = <0x0 0xfe310000 0x0 0x4000>;
206 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
207 clock-freq-min-max = <400000 150000000>;
208 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
209 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
210 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
211 fifo-depth = <0x100>;
212 status = "disabled";
213 };
214
215 sdmmc: dwmmc@fe320000 {
216 compatible = "rockchip,rk3399-dw-mshc",
217 "rockchip,rk3288-dw-mshc";
218 reg = <0x0 0xfe320000 0x0 0x4000>;
219 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
220 clock-freq-min-max = <400000 150000000>;
221 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
222 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
223 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
224 fifo-depth = <0x100>;
225 status = "disabled";
226 };
227
b4e87c09
BN		 228 sdhci: sdhci@fe330000 {
229 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
230 reg = <0x0 0xfe330000 0x0 0x10000>;
231 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
64e3481c 232 arasan,soc-ctl-syscon = <&grf>;
b4e87c09
BN		 233 assigned-clocks = <&cru SCLK_EMMC>;
234 assigned-clock-rates = <200000000>;
235 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
236 clock-names = "clk_xin", "clk_ahb";
237 phys = <&emmc_phy>;
238 phy-names = "phy_arasan";
239 status = "disabled";
240 };
241
f048b9a4
JX		 242 usb_host0_ehci: usb@fe380000 {
243 compatible = "generic-ehci";
244 reg = <0x0 0xfe380000 0x0 0x20000>;
245 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
247 clock-names = "hclk_host0", "hclk_host0_arb";
248 status = "disabled";
249 };
250
251 usb_host0_ohci: usb@fe3a0000 {
252 compatible = "generic-ohci";
253 reg = <0x0 0xfe3a0000 0x0 0x20000>;
254 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
256 clock-names = "hclk_host0", "hclk_host0_arb";
257 status = "disabled";
258 };
259
260 usb_host1_ehci: usb@fe3c0000 {
261 compatible = "generic-ehci";
262 reg = <0x0 0xfe3c0000 0x0 0x20000>;
263 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
265 clock-names = "hclk_host1", "hclk_host1_arb";
266 status = "disabled";
267 };
268
269 usb_host1_ohci: usb@fe3e0000 {
270 compatible = "generic-ohci";
271 reg = <0x0 0xfe3e0000 0x0 0x20000>;
272 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
274 clock-names = "hclk_host1", "hclk_host1_arb";
275 status = "disabled";
276 };
277
278 gic: interrupt-controller@fee00000 {
279 compatible = "arm,gic-v3";
280 #interrupt-cells = <3>;
281 #address-cells = <2>;
282 #size-cells = <2>;
283 ranges;
284 interrupt-controller;
285
286 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
287 <0x0 0xfef00000 0 0xc0000>, /* GICR */
288 <0x0 0xfff00000 0 0x10000>, /* GICC */
289 <0x0 0xfff10000 0 0x10000>, /* GICH */
290 <0x0 0xfff20000 0 0x10000>; /* GICV */
291 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
292 its: interrupt-controller@fee20000 {
293 compatible = "arm,gic-v3-its";
294 msi-controller;
295 reg = <0x0 0xfee20000 0x0 0x20000>;
296 };
297 };
298
69e5a8fe
DW		 299 i2c1: i2c@ff110000 {
300 compatible = "rockchip,rk3399-i2c";
301 reg = <0x0 0xff110000 0x0 0x1000>;
302 assigned-clocks = <&cru SCLK_I2C1>;
303 assigned-clock-rates = <200000000>;
304 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
305 clock-names = "i2c", "pclk";
306 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2c1_xfer>;
309 #address-cells = <1>;
310 #size-cells = <0>;
311 status = "disabled";
312 };
313
314 i2c2: i2c@ff120000 {
315 compatible = "rockchip,rk3399-i2c";
316 reg = <0x0 0xff120000 0x0 0x1000>;
317 assigned-clocks = <&cru SCLK_I2C2>;
318 assigned-clock-rates = <200000000>;
319 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
320 clock-names = "i2c", "pclk";
321 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&i2c2_xfer>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 status = "disabled";
327 };
328
329 i2c3: i2c@ff130000 {
330 compatible = "rockchip,rk3399-i2c";
331 reg = <0x0 0xff130000 0x0 0x1000>;
332 assigned-clocks = <&cru SCLK_I2C3>;
333 assigned-clock-rates = <200000000>;
334 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
335 clock-names = "i2c", "pclk";
336 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2c3_xfer>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 status = "disabled";
342 };
343
344 i2c5: i2c@ff140000 {
345 compatible = "rockchip,rk3399-i2c";
346 reg = <0x0 0xff140000 0x0 0x1000>;
347 assigned-clocks = <&cru SCLK_I2C5>;
348 assigned-clock-rates = <200000000>;
349 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
350 clock-names = "i2c", "pclk";
351 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2c5_xfer>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356 status = "disabled";
357 };
358
359 i2c6: i2c@ff150000 {
360 compatible = "rockchip,rk3399-i2c";
361 reg = <0x0 0xff150000 0x0 0x1000>;
362 assigned-clocks = <&cru SCLK_I2C6>;
363 assigned-clock-rates = <200000000>;
364 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
365 clock-names = "i2c", "pclk";
366 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&i2c6_xfer>;
369 #address-cells = <1>;
370 #size-cells = <0>;
371 status = "disabled";
372 };
373
374 i2c7: i2c@ff160000 {
375 compatible = "rockchip,rk3399-i2c";
376 reg = <0x0 0xff160000 0x0 0x1000>;
377 assigned-clocks = <&cru SCLK_I2C7>;
378 assigned-clock-rates = <200000000>;
379 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
380 clock-names = "i2c", "pclk";
381 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&i2c7_xfer>;
384 #address-cells = <1>;
385 #size-cells = <0>;
386 status = "disabled";
387 };
388
f048b9a4
JX		 389 uart0: serial@ff180000 {
390 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
391 reg = <0x0 0xff180000 0x0 0x100>;
392 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
393 clock-names = "baudclk", "apb_pclk";
394 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
395 reg-shift = <2>;
396 reg-io-width = <4>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&uart0_xfer>;
399 status = "disabled";
400 };
401
402 uart1: serial@ff190000 {
403 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
404 reg = <0x0 0xff190000 0x0 0x100>;
405 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
406 clock-names = "baudclk", "apb_pclk";
407 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
408 reg-shift = <2>;
409 reg-io-width = <4>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&uart1_xfer>;
412 status = "disabled";
413 };
414
415 uart2: serial@ff1a0000 {
416 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
417 reg = <0x0 0xff1a0000 0x0 0x100>;
418 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
419 clock-names = "baudclk", "apb_pclk";
420 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
421 reg-shift = <2>;
422 reg-io-width = <4>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&uart2c_xfer>;
425 status = "disabled";
426 };
427
428 uart3: serial@ff1b0000 {
429 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
430 reg = <0x0 0xff1b0000 0x0 0x100>;
431 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
432 clock-names = "baudclk", "apb_pclk";
433 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
434 reg-shift = <2>;
435 reg-io-width = <4>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&uart3_xfer>;
438 status = "disabled";
439 };
440
441 spi0: spi@ff1c0000 {
442 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
443 reg = <0x0 0xff1c0000 0x0 0x1000>;
444 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
445 clock-names = "spiclk", "apb_pclk";
446 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
449 #address-cells = <1>;
450 #size-cells = <0>;
451 status = "disabled";
452 };
453
454 spi1: spi@ff1d0000 {
455 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
456 reg = <0x0 0xff1d0000 0x0 0x1000>;
457 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
458 clock-names = "spiclk", "apb_pclk";
459 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
462 #address-cells = <1>;
463 #size-cells = <0>;
464 status = "disabled";
465 };
466
467 spi2: spi@ff1e0000 {
468 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
469 reg = <0x0 0xff1e0000 0x0 0x1000>;
470 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
471 clock-names = "spiclk", "apb_pclk";
472 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
475 #address-cells = <1>;
476 #size-cells = <0>;
477 status = "disabled";
478 };
479
480 spi4: spi@ff1f0000 {
481 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
482 reg = <0x0 0xff1f0000 0x0 0x1000>;
483 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
484 clock-names = "spiclk", "apb_pclk";
485 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
488 #address-cells = <1>;
489 #size-cells = <0>;
490 status = "disabled";
491 };
492
493 spi5: spi@ff200000 {
494 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
495 reg = <0x0 0xff200000 0x0 0x1000>;
496 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
497 clock-names = "spiclk", "apb_pclk";
498 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
501 #address-cells = <1>;
502 #size-cells = <0>;
503 status = "disabled";
504 };
505
95c27ba7
CW		 506 thermal-zones {
507 cpu_thermal: cpu {
508 polling-delay-passive = <100>;
509 polling-delay = <1000>;
510
511 thermal-sensors = <&tsadc 0>;
512
513 trips {
514 cpu_alert0: cpu_alert0 {
515 temperature = <70000>;
516 hysteresis = <2000>;
517 type = "passive";
518 };
519 cpu_alert1: cpu_alert1 {
520 temperature = <75000>;
521 hysteresis = <2000>;
522 type = "passive";
523 };
524 cpu_crit: cpu_crit {
525 temperature = <95000>;
526 hysteresis = <2000>;
527 type = "critical";
528 };
529 };
530
531 cooling-maps {
532 map0 {
533 trip = <&cpu_alert0>;
534 cooling-device =
535 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
536 };
537 map1 {
538 trip = <&cpu_alert1>;
539 cooling-device =
540 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
541 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
542 };
543 };
544 };
545
546 gpu_thermal: gpu {
547 polling-delay-passive = <100>;
548 polling-delay = <1000>;
549
550 thermal-sensors = <&tsadc 1>;
551
552 trips {
553 gpu_alert0: gpu_alert0 {
554 temperature = <75000>;
555 hysteresis = <2000>;
556 type = "passive";
557 };
558 gpu_crit: gpu_crit {
559 temperature = <95000>;
560 hysteresis = <2000>;
561 type = "critical";
562 };
563 };
564
565 cooling-maps {
566 map0 {
567 trip = <&gpu_alert0>;
568 cooling-device =
569 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
570 };
571 };
572 };
573 };
574
575 tsadc: tsadc@ff260000 {
576 compatible = "rockchip,rk3399-tsadc";
577 reg = <0x0 0xff260000 0x0 0x100>;
578 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
579 assigned-clocks = <&cru SCLK_TSADC>;
580 assigned-clock-rates = <750000>;
581 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
582 clock-names = "tsadc", "apb_pclk";
583 resets = <&cru SRST_TSADC>;
584 reset-names = "tsadc-apb";
585 rockchip,grf = <&grf>;
586 rockchip,hw-tshut-temp = <95000>;
587 pinctrl-names = "init", "default", "sleep";
588 pinctrl-0 = <&otp_gpio>;
589 pinctrl-1 = <&otp_out>;
590 pinctrl-2 = <&otp_gpio>;
591 #thermal-sensor-cells = <1>;
592 status = "disabled";
593 };
594
f048b9a4 595 pmugrf: syscon@ff320000 {
16759262 596 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
f048b9a4 597 reg = <0x0 0xff320000 0x0 0x1000>;
16759262
BN		 598 #address-cells = <1>;
599 #size-cells = <1>;
6d0e3a45
HS		 600
601 pmu_io_domains: io-domains {
602 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
603 status = "disabled";
604 };
f048b9a4
JX		 605 };
606
607 spi3: spi@ff350000 {
608 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
609 reg = <0x0 0xff350000 0x0 0x1000>;
610 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
611 clock-names = "spiclk", "apb_pclk";
612 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
613 pinctrl-names = "default";
614 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
615 #address-cells = <1>;
616 #size-cells = <0>;
617 status = "disabled";
618 };
619
620 uart4: serial@ff370000 {
621 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
622 reg = <0x0 0xff370000 0x0 0x100>;
623 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
624 clock-names = "baudclk", "apb_pclk";
625 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
626 reg-shift = <2>;
627 reg-io-width = <4>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&uart4_xfer>;
630 status = "disabled";
69e5a8fe
DW		 631 };
632
633 i2c0: i2c@ff3c0000 {
634 compatible = "rockchip,rk3399-i2c";
635 reg = <0x0 0xff3c0000 0x0 0x1000>;
636 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
637 assigned-clock-rates = <200000000>;
638 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
639 clock-names = "i2c", "pclk";
640 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
641 pinctrl-names = "default";
642 pinctrl-0 = <&i2c0_xfer>;
643 #address-cells = <1>;
644 #size-cells = <0>;
645 status = "disabled";
646 };
647
648 i2c4: i2c@ff3d0000 {
649 compatible = "rockchip,rk3399-i2c";
650 reg = <0x0 0xff3d0000 0x0 0x1000>;
651 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
652 assigned-clock-rates = <200000000>;
653 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
654 clock-names = "i2c", "pclk";
655 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
656 pinctrl-names = "default";
657 pinctrl-0 = <&i2c4_xfer>;
658 #address-cells = <1>;
659 #size-cells = <0>;
660 status = "disabled";
661 };
662
663 i2c8: i2c@ff3e0000 {
664 compatible = "rockchip,rk3399-i2c";
665 reg = <0x0 0xff3e0000 0x0 0x1000>;
666 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
667 assigned-clock-rates = <200000000>;
668 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
669 clock-names = "i2c", "pclk";
670 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&i2c8_xfer>;
673 #address-cells = <1>;
674 #size-cells = <0>;
675 status = "disabled";
f048b9a4
JX		 676 };
677
678 pwm0: pwm@ff420000 {
679 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
680 reg = <0x0 0xff420000 0x0 0x10>;
681 #pwm-cells = <3>;
682 pinctrl-names = "default";
683 pinctrl-0 = <&pwm0_pin>;
684 clocks = <&pmucru PCLK_RKPWM_PMU>;
685 clock-names = "pwm";
686 status = "disabled";
687 };
688
689 pwm1: pwm@ff420010 {
690 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
691 reg = <0x0 0xff420010 0x0 0x10>;
692 #pwm-cells = <3>;
693 pinctrl-names = "default";
694 pinctrl-0 = <&pwm1_pin>;
695 clocks = <&pmucru PCLK_RKPWM_PMU>;
696 clock-names = "pwm";
697 status = "disabled";
698 };
699
700 pwm2: pwm@ff420020 {
701 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
702 reg = <0x0 0xff420020 0x0 0x10>;
703 #pwm-cells = <3>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&pwm2_pin>;
706 clocks = <&pmucru PCLK_RKPWM_PMU>;
707 clock-names = "pwm";
708 status = "disabled";
709 };
710
711 pwm3: pwm@ff420030 {
712 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
713 reg = <0x0 0xff420030 0x0 0x10>;
714 #pwm-cells = <3>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&pwm3a_pin>;
717 clocks = <&pmucru PCLK_RKPWM_PMU>;
718 clock-names = "pwm";
719 status = "disabled";
720 };
721
722 pmucru: pmu-clock-controller@ff750000 {
723 compatible = "rockchip,rk3399-pmucru";
724 reg = <0x0 0xff750000 0x0 0x1000>;
725 #clock-cells = <1>;
726 #reset-cells = <1>;
727 assigned-clocks = <&pmucru PLL_PPLL>;
728 assigned-clock-rates = <676000000>;
729 };
730
731 cru: clock-controller@ff760000 {
732 compatible = "rockchip,rk3399-cru";
733 reg = <0x0 0xff760000 0x0 0x1000>;
734 #clock-cells = <1>;
735 #reset-cells = <1>;
a09906cd
XZ		 736 assigned-clocks =
737 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
738 <&cru PLL_NPLL>,
739 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
740 <&cru PCLK_PERIHP>,
741 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
742 <&cru PCLK_PERILP0>,
743 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
744 assigned-clock-rates =
745 <594000000>, <800000000>,
746 <1000000000>,
747 <150000000>, <75000000>,
748 <37500000>,
749 <100000000>, <100000000>,
750 <50000000>,
751 <100000000>, <50000000>;
f048b9a4
JX		 752 };
753
754 grf: syscon@ff770000 {
16759262 755 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
f048b9a4 756 reg = <0x0 0xff770000 0x0 0x10000>;
16759262
BN		 757 #address-cells = <1>;
758 #size-cells = <1>;
b4e87c09 759
6d0e3a45
HS		 760 io_domains: io-domains {
761 compatible = "rockchip,rk3399-io-voltage-domain";
762 status = "disabled";
763 };
764
b4e87c09
BN		 765 emmc_phy: phy@f780 {
766 compatible = "rockchip,rk3399-emmc-phy";
767 reg = <0xf780 0x24>;
768 #phy-cells = <0>;
769 status = "disabled";
770 };
f048b9a4
JX		 771 };
772
773 watchdog@ff840000 {
774 compatible = "snps,dw-wdt";
775 reg = <0x0 0xff840000 0x0 0x100>;
776 clocks = <&cru PCLK_WDT>;
777 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
778 };
779
780 spdif: spdif@ff870000 {
781 compatible = "rockchip,rk3399-spdif";
782 reg = <0x0 0xff870000 0x0 0x1000>;
783 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
784 dmas = <&dmac_bus 7>;
785 dma-names = "tx";
786 clock-names = "mclk", "hclk";
787 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
788 pinctrl-names = "default";
789 pinctrl-0 = <&spdif_bus>;
790 status = "disabled";
791 };
792
793 i2s0: i2s@ff880000 {
794 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
795 reg = <0x0 0xff880000 0x0 0x1000>;
796 rockchip,grf = <&grf>;
797 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
798 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
799 dma-names = "tx", "rx";
800 clock-names = "i2s_clk", "i2s_hclk";
801 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
802 pinctrl-names = "default";
803 pinctrl-0 = <&i2s0_8ch_bus>;
804 status = "disabled";
805 };
806
807 i2s1: i2s@ff890000 {
808 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
809 reg = <0x0 0xff890000 0x0 0x1000>;
810 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
811 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
812 dma-names = "tx", "rx";
813 clock-names = "i2s_clk", "i2s_hclk";
814 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
815 pinctrl-names = "default";
816 pinctrl-0 = <&i2s1_2ch_bus>;
817 status = "disabled";
818 };
819
820 i2s2: i2s@ff8a0000 {
821 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
822 reg = <0x0 0xff8a0000 0x0 0x1000>;
823 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
824 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
825 dma-names = "tx", "rx";
826 clock-names = "i2s_clk", "i2s_hclk";
827 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
828 status = "disabled";
829 };
830
831 pinctrl: pinctrl {
832 compatible = "rockchip,rk3399-pinctrl";
833 rockchip,grf = <&grf>;
834 rockchip,pmu = <&pmugrf>;
835 #address-cells = <2>;
836 #size-cells = <2>;
837 ranges;
838
839 gpio0: gpio0@ff720000 {
840 compatible = "rockchip,gpio-bank";
841 reg = <0x0 0xff720000 0x0 0x100>;
842 clocks = <&pmucru PCLK_GPIO0_PMU>;
843 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
844
845 gpio-controller;
846 #gpio-cells = <0x2>;
847
848 interrupt-controller;
849 #interrupt-cells = <0x2>;
850 };
851
852 gpio1: gpio1@ff730000 {
853 compatible = "rockchip,gpio-bank";
854 reg = <0x0 0xff730000 0x0 0x100>;
855 clocks = <&pmucru PCLK_GPIO1_PMU>;
856 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
857
858 gpio-controller;
859 #gpio-cells = <0x2>;
860
861 interrupt-controller;
862 #interrupt-cells = <0x2>;
863 };
864
865 gpio2: gpio2@ff780000 {
866 compatible = "rockchip,gpio-bank";
867 reg = <0x0 0xff780000 0x0 0x100>;
868 clocks = <&cru PCLK_GPIO2>;
869 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
870
871 gpio-controller;
872 #gpio-cells = <0x2>;
873
874 interrupt-controller;
875 #interrupt-cells = <0x2>;
876 };
877
878 gpio3: gpio3@ff788000 {
879 compatible = "rockchip,gpio-bank";
880 reg = <0x0 0xff788000 0x0 0x100>;
881 clocks = <&cru PCLK_GPIO3>;
882 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
883
884 gpio-controller;
885 #gpio-cells = <0x2>;
886
887 interrupt-controller;
888 #interrupt-cells = <0x2>;
889 };
890
891 gpio4: gpio4@ff790000 {
892 compatible = "rockchip,gpio-bank";
893 reg = <0x0 0xff790000 0x0 0x100>;
894 clocks = <&cru PCLK_GPIO4>;
895 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
896
897 gpio-controller;
898 #gpio-cells = <0x2>;
899
900 interrupt-controller;
901 #interrupt-cells = <0x2>;
902 };
903
904 pcfg_pull_up: pcfg-pull-up {
905 bias-pull-up;
906 };
907
908 pcfg_pull_down: pcfg-pull-down {
909 bias-pull-down;
910 };
911
912 pcfg_pull_none: pcfg-pull-none {
913 bias-disable;
914 };
915
916 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
917 bias-disable;
918 drive-strength = <12>;
919 };
920
921 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
922 bias-pull-up;
923 drive-strength = <8>;
924 };
925
926 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
927 bias-pull-down;
928 drive-strength = <4>;
929 };
930
931 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
932 bias-pull-up;
933 drive-strength = <2>;
934 };
935
936 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
937 bias-pull-down;
938 drive-strength = <12>;
939 };
940
941 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
942 bias-disable;
943 drive-strength = <13>;
944 };
945
946 i2c0 {
947 i2c0_xfer: i2c0-xfer {
948 rockchip,pins =
949 <1 15 RK_FUNC_2 &pcfg_pull_none>,
950 <1 16 RK_FUNC_2 &pcfg_pull_none>;
951 };
952 };
953
954 i2c1 {
955 i2c1_xfer: i2c1-xfer {
956 rockchip,pins =
957 <4 2 RK_FUNC_1 &pcfg_pull_none>,
958 <4 1 RK_FUNC_1 &pcfg_pull_none>;
959 };
960 };
961
962 i2c2 {
963 i2c2_xfer: i2c2-xfer {
964 rockchip,pins =
965 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
966 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
967 };
968 };
969
970 i2c3 {
971 i2c3_xfer: i2c3-xfer {
972 rockchip,pins =
973 <4 17 RK_FUNC_1 &pcfg_pull_none>,
974 <4 16 RK_FUNC_1 &pcfg_pull_none>;
975 };
976 };
977
978 i2c4 {
979 i2c4_xfer: i2c4-xfer {
980 rockchip,pins =
981 <1 12 RK_FUNC_1 &pcfg_pull_none>,
982 <1 11 RK_FUNC_1 &pcfg_pull_none>;
983 };
984 };
985
986 i2c5 {
987 i2c5_xfer: i2c5-xfer {
988 rockchip,pins =
989 <3 11 RK_FUNC_2 &pcfg_pull_none>,
990 <3 10 RK_FUNC_2 &pcfg_pull_none>;
991 };
992 };
993
994 i2c6 {
995 i2c6_xfer: i2c6-xfer {
996 rockchip,pins =
997 <2 10 RK_FUNC_2 &pcfg_pull_none>,
998 <2 9 RK_FUNC_2 &pcfg_pull_none>;
999 };
1000 };
1001
1002 i2c7 {
1003 i2c7_xfer: i2c7-xfer {
1004 rockchip,pins =
1005 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1006 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1007 };
1008 };
1009
1010 i2c8 {
1011 i2c8_xfer: i2c8-xfer {
1012 rockchip,pins =
1013 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1014 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1015 };
1016 };
1017
1018 i2s0 {
1019 i2s0_8ch_bus: i2s0-8ch-bus {
1020 rockchip,pins =
1021 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1022 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1023 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1024 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1025 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1026 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1027 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1028 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1029 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1030 };
1031 };
1032
1033 i2s1 {
1034 i2s1_2ch_bus: i2s1-2ch-bus {
1035 rockchip,pins =
1036 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1037 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1038 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1039 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1040 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1041 };
1042 };
1043
1044 spdif {
1045 spdif_bus: spdif-bus {
1046 rockchip,pins =
1047 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1048 };
1049 };
1050
1051 spi0 {
1052 spi0_clk: spi0-clk {
1053 rockchip,pins =
1054 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1055 };
1056 spi0_cs0: spi0-cs0 {
1057 rockchip,pins =
1058 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1059 };
1060 spi0_cs1: spi0-cs1 {
1061 rockchip,pins =
1062 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1063 };
1064 spi0_tx: spi0-tx {
1065 rockchip,pins =
1066 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1067 };
1068 spi0_rx: spi0-rx {
1069 rockchip,pins =
1070 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1071 };
1072 };
1073
1074 spi1 {
1075 spi1_clk: spi1-clk {
1076 rockchip,pins =
1077 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1078 };
1079 spi1_cs0: spi1-cs0 {
1080 rockchip,pins =
1081 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1082 };
1083 spi1_rx: spi1-rx {
1084 rockchip,pins =
1085 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1086 };
1087 spi1_tx: spi1-tx {
1088 rockchip,pins =
1089 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1090 };
1091 };
1092
1093 spi2 {
1094 spi2_clk: spi2-clk {
1095 rockchip,pins =
1096 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1097 };
1098 spi2_cs0: spi2-cs0 {
1099 rockchip,pins =
1100 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1101 };
1102 spi2_rx: spi2-rx {
1103 rockchip,pins =
1104 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1105 };
1106 spi2_tx: spi2-tx {
1107 rockchip,pins =
1108 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1109 };
1110 };
1111
1112 spi3 {
1113 spi3_clk: spi3-clk {
1114 rockchip,pins =
1115 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1116 };
1117 spi3_cs0: spi3-cs0 {
1118 rockchip,pins =
1119 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1120 };
1121 spi3_rx: spi3-rx {
1122 rockchip,pins =
1123 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1124 };
1125 spi3_tx: spi3-tx {
1126 rockchip,pins =
1127 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1128 };
1129 };
1130
1131 spi4 {
1132 spi4_clk: spi4-clk {
1133 rockchip,pins =
1134 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1135 };
1136 spi4_cs0: spi4-cs0 {
1137 rockchip,pins =
1138 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1139 };
1140 spi4_rx: spi4-rx {
1141 rockchip,pins =
1142 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1143 };
1144 spi4_tx: spi4-tx {
1145 rockchip,pins =
1146 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1147 };
1148 };
1149
1150 spi5 {
1151 spi5_clk: spi5-clk {
1152 rockchip,pins =
1153 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1154 };
1155 spi5_cs0: spi5-cs0 {
1156 rockchip,pins =
1157 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1158 };
1159 spi5_rx: spi5-rx {
1160 rockchip,pins =
1161 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1162 };
1163 spi5_tx: spi5-tx {
1164 rockchip,pins =
1165 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1166 };
1167 };
1168
95c27ba7
CW		 1169 tsadc {
1170 otp_gpio: otp-gpio {
1171 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1172 };
1173
1174 otp_out: otp-out {
1175 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1176 };
1177 };
1178
f048b9a4
JX		 1179 uart0 {
1180 uart0_xfer: uart0-xfer {
1181 rockchip,pins =
1182 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1183 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1184 };
1185
1186 uart0_cts: uart0-cts {
1187 rockchip,pins =
1188 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1189 };
1190
1191 uart0_rts: uart0-rts {
1192 rockchip,pins =
1193 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1194 };
1195 };
1196
1197 uart1 {
1198 uart1_xfer: uart1-xfer {
1199 rockchip,pins =
1200 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1201 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1202 };
1203 };
1204
1205 uart2a {
1206 uart2a_xfer: uart2a-xfer {
1207 rockchip,pins =
1208 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1209 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1210 };
1211 };
1212
1213 uart2b {
1214 uart2b_xfer: uart2b-xfer {
1215 rockchip,pins =
1216 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1217 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1218 };
1219 };
1220
1221 uart2c {
1222 uart2c_xfer: uart2c-xfer {
1223 rockchip,pins =
1224 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1225 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1226 };
1227 };
1228
1229 uart3 {
1230 uart3_xfer: uart3-xfer {
1231 rockchip,pins =
1232 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1233 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1234 };
1235
1236 uart3_cts: uart3-cts {
1237 rockchip,pins =
1238 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1239 };
1240
1241 uart3_rts: uart3-rts {
1242 rockchip,pins =
1243 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1244 };
1245 };
1246
1247 uart4 {
1248 uart4_xfer: uart4-xfer {
1249 rockchip,pins =
1250 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1251 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1252 };
1253 };
1254
1255 uarthdcp {
1256 uarthdcp_xfer: uarthdcp-xfer {
1257 rockchip,pins =
1258 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1259 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1260 };
1261 };
1262
1263 pwm0 {
1264 pwm0_pin: pwm0-pin {
1265 rockchip,pins =
1266 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1267 };
1268
1269 vop0_pwm_pin: vop0-pwm-pin {
1270 rockchip,pins =
1271 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1272 };
1273 };
1274
1275 pwm1 {
1276 pwm1_pin: pwm1-pin {
1277 rockchip,pins =
1278 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1279 };
1280
1281 vop1_pwm_pin: vop1-pwm-pin {
1282 rockchip,pins =
1283 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1284 };
1285 };
1286
1287 pwm2 {
1288 pwm2_pin: pwm2-pin {
1289 rockchip,pins =
1290 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1291 };
1292 };
1293
1294 pwm3a {
1295 pwm3a_pin: pwm3a-pin {
1296 rockchip,pins =
1297 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1298 };
1299 };
1300
1301 pwm3b {
1302 pwm3b_pin: pwm3b-pin {
1303 rockchip,pins =
1304 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1305 };
1306 };
1307 };
1308};
Linux kernel - Deliverables
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