projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f048b9a4 JX |
1 | /* |
| 2 | * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd | |
| 3 | * | |
| 4 | * This file is dual-licensed: you can use it either under the terms | |
| 5 | * of the GPL or the X11 license, at your option. Note that this dual | |
| 6 | * licensing only applies to this file, and not this project as a | |
| 7 | * whole. | |
| 8 | * | |
| 9 | * a) This library is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License as | |
| 11 | * published by the Free Software Foundation; either version 2 of the | |
| 12 | * License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This library is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * Or, alternatively, | |
| 20 | * | |
| 21 | * b) Permission is hereby granted, free of charge, to any person | |
| 22 | * obtaining a copy of this software and associated documentation | |
| 23 | * files (the "Software"), to deal in the Software without | |
| 24 | * restriction, including without limitation the rights to use, | |
| 25 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 26 | * sell copies of the Software, and to permit persons to whom the | |
| 27 | * Software is furnished to do so, subject to the following | |
| 28 | * conditions: | |
| 29 | * | |
| 30 | * The above copyright notice and this permission notice shall be | |
| 31 | * included in all copies or substantial portions of the Software. | |
| 32 | * | |
| 33 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 34 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 35 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 36 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 37 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 38 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 39 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 40 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 41 | */ | |
| 42 | ||
| 43 | #include <dt-bindings/clock/rk3399-cru.h> | |
| 44 | #include <dt-bindings/gpio/gpio.h> | |
| 45 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| 46 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 47 | #include <dt-bindings/pinctrl/rockchip.h> | |
| 48 | ||
| 49 | / { | |
| 50 | compatible = "rockchip,rk3399"; | |
| 51 | ||
| 52 | interrupt-parent = <&gic>; | |
| 53 | #address-cells = <2>; | |
| 54 | #size-cells = <2>; | |
| 55 | ||
| 56 | aliases { | |
| 57 | serial0 = &uart0; | |
| 58 | serial1 = &uart1; | |
| 59 | serial2 = &uart2; | |
| 60 | serial3 = &uart3; | |
| 61 | serial4 = &uart4; | |
| 62 | }; | |
| 63 | ||
| 64 | cpus { | |
| 65 | #address-cells = <2>; | |
| 66 | #size-cells = <0>; | |
| 67 | ||
| 68 | cpu-map { | |
| 69 | cluster0 { | |
| 70 | core0 { | |
| 71 | cpu = <&cpu_l0>; | |
| 72 | }; | |
| 73 | core1 { | |
| 74 | cpu = <&cpu_l1>; | |
| 75 | }; | |
| 76 | core2 { | |
| 77 | cpu = <&cpu_l2>; | |
| 78 | }; | |
| 79 | core3 { | |
| 80 | cpu = <&cpu_l3>; | |
| 81 | }; | |
| 82 | }; | |
| 83 | ||
| 84 | cluster1 { | |
| 85 | core0 { | |
| 86 | cpu = <&cpu_b0>; | |
| 87 | }; | |
| 88 | core1 { | |
| 89 | cpu = <&cpu_b1>; | |
| 90 | }; | |
| 91 | }; | |
| 92 | }; | |
| 93 | ||
| 94 | cpu_l0: cpu@0 { | |
| 95 | device_type = "cpu"; | |
| 96 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 97 | reg = <0x0 0x0>; | |
| 98 | enable-method = "psci"; | |
| 99 | #cooling-cells = <2>; /* min followed by max */ | |
| 100 | clocks = <&cru ARMCLKL>; | |
| 101 | }; | |
| 102 | ||
| 103 | cpu_l1: cpu@1 { | |
| 104 | device_type = "cpu"; | |
| 105 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 106 | reg = <0x0 0x1>; | |
| 107 | enable-method = "psci"; | |
| 108 | clocks = <&cru ARMCLKL>; | |
| 109 | }; | |
| 110 | ||
| 111 | cpu_l2: cpu@2 { | |
| 112 | device_type = "cpu"; | |
| 113 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 114 | reg = <0x0 0x2>; | |
| 115 | enable-method = "psci"; | |
| 116 | clocks = <&cru ARMCLKL>; | |
| 117 | }; | |
| 118 | ||
| 119 | cpu_l3: cpu@3 { | |
| 120 | device_type = "cpu"; | |
| 121 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 122 | reg = <0x0 0x3>; | |
| 123 | enable-method = "psci"; | |
| 124 | clocks = <&cru ARMCLKL>; | |
| 125 | }; | |
| 126 | ||
| 127 | cpu_b0: cpu@100 { | |
| 128 | device_type = "cpu"; | |
| 129 | compatible = "arm,cortex-a72", "arm,armv8"; | |
| 130 | reg = <0x0 0x100>; | |
| 131 | enable-method = "psci"; | |
| 132 | #cooling-cells = <2>; /* min followed by max */ | |
| 133 | clocks = <&cru ARMCLKB>; | |
| 134 | }; | |
| 135 | ||
| 136 | cpu_b1: cpu@101 { | |
| 137 | device_type = "cpu"; | |
| 138 | compatible = "arm,cortex-a72", "arm,armv8"; | |
| 139 | reg = <0x0 0x101>; | |
| 140 | enable-method = "psci"; | |
| 141 | clocks = <&cru ARMCLKB>; | |
| 142 | }; | |
| 143 | }; | |
| 144 | ||
| 145 | psci { | |
| 146 | compatible = "arm,psci-1.0"; | |
| 147 | method = "smc"; | |
| 148 | }; | |
| 149 | ||
| 150 | timer { | |
| 151 | compatible = "arm,armv8-timer"; | |
| 152 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, | |
| 153 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, | |
| 154 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, | |
| 155 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; | |
| 156 | }; | |
| 157 | ||
| 158 | xin24m: xin24m { | |
| 159 | compatible = "fixed-clock"; | |
| 160 | clock-frequency = <24000000>; | |
| 161 | clock-output-names = "xin24m"; | |
| 162 | #clock-cells = <0>; | |
| 163 | }; | |
| 164 | ||
| 165 | amba { | |
| 166 | compatible = "arm,amba-bus"; | |
| 167 | #address-cells = <2>; | |
| 168 | #size-cells = <2>; | |
| 169 | ranges; | |
| 170 | ||
| 171 | dmac_bus: dma-controller@ff6d0000 { | |
| 172 | compatible = "arm,pl330", "arm,primecell"; | |
| 173 | reg = <0x0 0xff6d0000 0x0 0x4000>; | |
| 174 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, | |
| 175 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
| 176 | #dma-cells = <1>; | |
| 177 | clocks = <&cru ACLK_DMAC0_PERILP>; | |
| 178 | clock-names = "apb_pclk"; | |
| 179 | }; | |
| 180 | ||
| 181 | dmac_peri: dma-controller@ff6e0000 { | |
| 182 | compatible = "arm,pl330", "arm,primecell"; | |
| 183 | reg = <0x0 0xff6e0000 0x0 0x4000>; | |
| 184 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
| 185 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 186 | #dma-cells = <1>; | |
| 187 | clocks = <&cru ACLK_DMAC1_PERILP>; | |
| 188 | clock-names = "apb_pclk"; | |
| 189 | }; | |
| 190 | }; | |
| 191 | ||
| 192 | sdio0: dwmmc@fe310000 { | |
| 193 | compatible = "rockchip,rk3399-dw-mshc", | |
| 194 | "rockchip,rk3288-dw-mshc"; | |
| 195 | reg = <0x0 0xfe310000 0x0 0x4000>; | |
| 196 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | |
| 197 | clock-freq-min-max = <400000 150000000>; | |
| 198 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, | |
| 199 | <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; | |
| 200 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
| 201 | fifo-depth = <0x100>; | |
| 202 | status = "disabled"; | |
| 203 | }; | |
| 204 | ||
| 205 | sdmmc: dwmmc@fe320000 { | |
| 206 | compatible = "rockchip,rk3399-dw-mshc", | |
| 207 | "rockchip,rk3288-dw-mshc"; | |
| 208 | reg = <0x0 0xfe320000 0x0 0x4000>; | |
| 209 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
| 210 | clock-freq-min-max = <400000 150000000>; | |
| 211 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, | |
| 212 | <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; | |
| 213 | clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; | |
| 214 | fifo-depth = <0x100>; | |
| 215 | status = "disabled"; | |
| 216 | }; | |
| 217 | ||
| b4e87c09 BN |
218 | sdhci: sdhci@fe330000 { |
| 219 | compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; | |
| 220 | reg = <0x0 0xfe330000 0x0 0x10000>; | |
| 221 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 222 | assigned-clocks = <&cru SCLK_EMMC>; | |
| 223 | assigned-clock-rates = <200000000>; | |
| 224 | clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; | |
| 225 | clock-names = "clk_xin", "clk_ahb"; | |
| 226 | phys = <&emmc_phy>; | |
| 227 | phy-names = "phy_arasan"; | |
| 228 | status = "disabled"; | |
| 229 | }; | |
| 230 | ||
| f048b9a4 JX |
231 | usb_host0_ehci: usb@fe380000 { |
| 232 | compatible = "generic-ehci"; | |
| 233 | reg = <0x0 0xfe380000 0x0 0x20000>; | |
| 234 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
| 235 | clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; | |
| 236 | clock-names = "hclk_host0", "hclk_host0_arb"; | |
| 237 | status = "disabled"; | |
| 238 | }; | |
| 239 | ||
| 240 | usb_host0_ohci: usb@fe3a0000 { | |
| 241 | compatible = "generic-ohci"; | |
| 242 | reg = <0x0 0xfe3a0000 0x0 0x20000>; | |
| 243 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
| 244 | clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; | |
| 245 | clock-names = "hclk_host0", "hclk_host0_arb"; | |
| 246 | status = "disabled"; | |
| 247 | }; | |
| 248 | ||
| 249 | usb_host1_ehci: usb@fe3c0000 { | |
| 250 | compatible = "generic-ehci"; | |
| 251 | reg = <0x0 0xfe3c0000 0x0 0x20000>; | |
| 252 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 253 | clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; | |
| 254 | clock-names = "hclk_host1", "hclk_host1_arb"; | |
| 255 | status = "disabled"; | |
| 256 | }; | |
| 257 | ||
| 258 | usb_host1_ohci: usb@fe3e0000 { | |
| 259 | compatible = "generic-ohci"; | |
| 260 | reg = <0x0 0xfe3e0000 0x0 0x20000>; | |
| 261 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
| 262 | clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; | |
| 263 | clock-names = "hclk_host1", "hclk_host1_arb"; | |
| 264 | status = "disabled"; | |
| 265 | }; | |
| 266 | ||
| 267 | gic: interrupt-controller@fee00000 { | |
| 268 | compatible = "arm,gic-v3"; | |
| 269 | #interrupt-cells = <3>; | |
| 270 | #address-cells = <2>; | |
| 271 | #size-cells = <2>; | |
| 272 | ranges; | |
| 273 | interrupt-controller; | |
| 274 | ||
| 275 | reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ | |
| 276 | <0x0 0xfef00000 0 0xc0000>, /* GICR */ | |
| 277 | <0x0 0xfff00000 0 0x10000>, /* GICC */ | |
| 278 | <0x0 0xfff10000 0 0x10000>, /* GICH */ | |
| 279 | <0x0 0xfff20000 0 0x10000>; /* GICV */ | |
| 280 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 281 | its: interrupt-controller@fee20000 { | |
| 282 | compatible = "arm,gic-v3-its"; | |
| 283 | msi-controller; | |
| 284 | reg = <0x0 0xfee20000 0x0 0x20000>; | |
| 285 | }; | |
| 286 | }; | |
| 287 | ||
| 288 | uart0: serial@ff180000 { | |
| 289 | compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| 290 | reg = <0x0 0xff180000 0x0 0x100>; | |
| 291 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
| 292 | clock-names = "baudclk", "apb_pclk"; | |
| 293 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; | |
| 294 | reg-shift = <2>; | |
| 295 | reg-io-width = <4>; | |
| 296 | pinctrl-names = "default"; | |
| 297 | pinctrl-0 = <&uart0_xfer>; | |
| 298 | status = "disabled"; | |
| 299 | }; | |
| 300 | ||
| 301 | uart1: serial@ff190000 { | |
| 302 | compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| 303 | reg = <0x0 0xff190000 0x0 0x100>; | |
| 304 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
| 305 | clock-names = "baudclk", "apb_pclk"; | |
| 306 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
| 307 | reg-shift = <2>; | |
| 308 | reg-io-width = <4>; | |
| 309 | pinctrl-names = "default"; | |
| 310 | pinctrl-0 = <&uart1_xfer>; | |
| 311 | status = "disabled"; | |
| 312 | }; | |
| 313 | ||
| 314 | uart2: serial@ff1a0000 { | |
| 315 | compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| 316 | reg = <0x0 0xff1a0000 0x0 0x100>; | |
| 317 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
| 318 | clock-names = "baudclk", "apb_pclk"; | |
| 319 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
| 320 | reg-shift = <2>; | |
| 321 | reg-io-width = <4>; | |
| 322 | pinctrl-names = "default"; | |
| 323 | pinctrl-0 = <&uart2c_xfer>; | |
| 324 | status = "disabled"; | |
| 325 | }; | |
| 326 | ||
| 327 | uart3: serial@ff1b0000 { | |
| 328 | compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| 329 | reg = <0x0 0xff1b0000 0x0 0x100>; | |
| 330 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; | |
| 331 | clock-names = "baudclk", "apb_pclk"; | |
| 332 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
| 333 | reg-shift = <2>; | |
| 334 | reg-io-width = <4>; | |
| 335 | pinctrl-names = "default"; | |
| 336 | pinctrl-0 = <&uart3_xfer>; | |
| 337 | status = "disabled"; | |
| 338 | }; | |
| 339 | ||
| 340 | spi0: spi@ff1c0000 { | |
| 341 | compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| 342 | reg = <0x0 0xff1c0000 0x0 0x1000>; | |
| 343 | clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; | |
| 344 | clock-names = "spiclk", "apb_pclk"; | |
| 345 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
| 346 | pinctrl-names = "default"; | |
| 347 | pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; | |
| 348 | #address-cells = <1>; | |
| 349 | #size-cells = <0>; | |
| 350 | status = "disabled"; | |
| 351 | }; | |
| 352 | ||
| 353 | spi1: spi@ff1d0000 { | |
| 354 | compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| 355 | reg = <0x0 0xff1d0000 0x0 0x1000>; | |
| 356 | clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; | |
| 357 | clock-names = "spiclk", "apb_pclk"; | |
| 358 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
| 359 | pinctrl-names = "default"; | |
| 360 | pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; | |
| 361 | #address-cells = <1>; | |
| 362 | #size-cells = <0>; | |
| 363 | status = "disabled"; | |
| 364 | }; | |
| 365 | ||
| 366 | spi2: spi@ff1e0000 { | |
| 367 | compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| 368 | reg = <0x0 0xff1e0000 0x0 0x1000>; | |
| 369 | clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; | |
| 370 | clock-names = "spiclk", "apb_pclk"; | |
| 371 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
| 372 | pinctrl-names = "default"; | |
| 373 | pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; | |
| 374 | #address-cells = <1>; | |
| 375 | #size-cells = <0>; | |
| 376 | status = "disabled"; | |
| 377 | }; | |
| 378 | ||
| 379 | spi4: spi@ff1f0000 { | |
| 380 | compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| 381 | reg = <0x0 0xff1f0000 0x0 0x1000>; | |
| 382 | clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; | |
| 383 | clock-names = "spiclk", "apb_pclk"; | |
| 384 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
| 385 | pinctrl-names = "default"; | |
| 386 | pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; | |
| 387 | #address-cells = <1>; | |
| 388 | #size-cells = <0>; | |
| 389 | status = "disabled"; | |
| 390 | }; | |
| 391 | ||
| 392 | spi5: spi@ff200000 { | |
| 393 | compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| 394 | reg = <0x0 0xff200000 0x0 0x1000>; | |
| 395 | clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; | |
| 396 | clock-names = "spiclk", "apb_pclk"; | |
| 397 | interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; | |
| 398 | pinctrl-names = "default"; | |
| 399 | pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; | |
| 400 | #address-cells = <1>; | |
| 401 | #size-cells = <0>; | |
| 402 | status = "disabled"; | |
| 403 | }; | |
| 404 | ||
| 405 | pmugrf: syscon@ff320000 { | |
| 16759262 | 406 | compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; |
| f048b9a4 | 407 | reg = <0x0 0xff320000 0x0 0x1000>; |
| 16759262 BN |
408 | #address-cells = <1>; |
| 409 | #size-cells = <1>; | |
| 6d0e3a45 HS |
410 | |
| 411 | pmu_io_domains: io-domains { | |
| 412 | compatible = "rockchip,rk3399-pmu-io-voltage-domain"; | |
| 413 | status = "disabled"; | |
| 414 | }; | |
| f048b9a4 JX |
415 | }; |
| 416 | ||
| 417 | spi3: spi@ff350000 { | |
| 418 | compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; | |
| 419 | reg = <0x0 0xff350000 0x0 0x1000>; | |
| 420 | clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; | |
| 421 | clock-names = "spiclk", "apb_pclk"; | |
| 422 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
| 423 | pinctrl-names = "default"; | |
| 424 | pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; | |
| 425 | #address-cells = <1>; | |
| 426 | #size-cells = <0>; | |
| 427 | status = "disabled"; | |
| 428 | }; | |
| 429 | ||
| 430 | uart4: serial@ff370000 { | |
| 431 | compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; | |
| 432 | reg = <0x0 0xff370000 0x0 0x100>; | |
| 433 | clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; | |
| 434 | clock-names = "baudclk", "apb_pclk"; | |
| 435 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
| 436 | reg-shift = <2>; | |
| 437 | reg-io-width = <4>; | |
| 438 | pinctrl-names = "default"; | |
| 439 | pinctrl-0 = <&uart4_xfer>; | |
| 440 | status = "disabled"; | |
| 441 | }; | |
| 442 | ||
| 443 | pwm0: pwm@ff420000 { | |
| 444 | compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; | |
| 445 | reg = <0x0 0xff420000 0x0 0x10>; | |
| 446 | #pwm-cells = <3>; | |
| 447 | pinctrl-names = "default"; | |
| 448 | pinctrl-0 = <&pwm0_pin>; | |
| 449 | clocks = <&pmucru PCLK_RKPWM_PMU>; | |
| 450 | clock-names = "pwm"; | |
| 451 | status = "disabled"; | |
| 452 | }; | |
| 453 | ||
| 454 | pwm1: pwm@ff420010 { | |
| 455 | compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; | |
| 456 | reg = <0x0 0xff420010 0x0 0x10>; | |
| 457 | #pwm-cells = <3>; | |
| 458 | pinctrl-names = "default"; | |
| 459 | pinctrl-0 = <&pwm1_pin>; | |
| 460 | clocks = <&pmucru PCLK_RKPWM_PMU>; | |
| 461 | clock-names = "pwm"; | |
| 462 | status = "disabled"; | |
| 463 | }; | |
| 464 | ||
| 465 | pwm2: pwm@ff420020 { | |
| 466 | compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; | |
| 467 | reg = <0x0 0xff420020 0x0 0x10>; | |
| 468 | #pwm-cells = <3>; | |
| 469 | pinctrl-names = "default"; | |
| 470 | pinctrl-0 = <&pwm2_pin>; | |
| 471 | clocks = <&pmucru PCLK_RKPWM_PMU>; | |
| 472 | clock-names = "pwm"; | |
| 473 | status = "disabled"; | |
| 474 | }; | |
| 475 | ||
| 476 | pwm3: pwm@ff420030 { | |
| 477 | compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; | |
| 478 | reg = <0x0 0xff420030 0x0 0x10>; | |
| 479 | #pwm-cells = <3>; | |
| 480 | pinctrl-names = "default"; | |
| 481 | pinctrl-0 = <&pwm3a_pin>; | |
| 482 | clocks = <&pmucru PCLK_RKPWM_PMU>; | |
| 483 | clock-names = "pwm"; | |
| 484 | status = "disabled"; | |
| 485 | }; | |
| 486 | ||
| 487 | pmucru: pmu-clock-controller@ff750000 { | |
| 488 | compatible = "rockchip,rk3399-pmucru"; | |
| 489 | reg = <0x0 0xff750000 0x0 0x1000>; | |
| 490 | #clock-cells = <1>; | |
| 491 | #reset-cells = <1>; | |
| 492 | assigned-clocks = <&pmucru PLL_PPLL>; | |
| 493 | assigned-clock-rates = <676000000>; | |
| 494 | }; | |
| 495 | ||
| 496 | cru: clock-controller@ff760000 { | |
| 497 | compatible = "rockchip,rk3399-cru"; | |
| 498 | reg = <0x0 0xff760000 0x0 0x1000>; | |
| 499 | #clock-cells = <1>; | |
| 500 | #reset-cells = <1>; | |
| a09906cd XZ |
501 | assigned-clocks = |
| 502 | <&cru PLL_GPLL>, <&cru PLL_CPLL>, | |
| 503 | <&cru PLL_NPLL>, | |
| 504 | <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, | |
| 505 | <&cru PCLK_PERIHP>, | |
| 506 | <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, | |
| 507 | <&cru PCLK_PERILP0>, | |
| 508 | <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; | |
| 509 | assigned-clock-rates = | |
| 510 | <594000000>, <800000000>, | |
| 511 | <1000000000>, | |
| 512 | <150000000>, <75000000>, | |
| 513 | <37500000>, | |
| 514 | <100000000>, <100000000>, | |
| 515 | <50000000>, | |
| 516 | <100000000>, <50000000>; | |
| f048b9a4 JX |
517 | }; |
| 518 | ||
| 519 | grf: syscon@ff770000 { | |
| 16759262 | 520 | compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; |
| f048b9a4 | 521 | reg = <0x0 0xff770000 0x0 0x10000>; |
| 16759262 BN |
522 | #address-cells = <1>; |
| 523 | #size-cells = <1>; | |
| b4e87c09 | 524 | |
| 6d0e3a45 HS |
525 | io_domains: io-domains { |
| 526 | compatible = "rockchip,rk3399-io-voltage-domain"; | |
| 527 | status = "disabled"; | |
| 528 | }; | |
| 529 | ||
| b4e87c09 BN |
530 | emmc_phy: phy@f780 { |
| 531 | compatible = "rockchip,rk3399-emmc-phy"; | |
| 532 | reg = <0xf780 0x24>; | |
| 533 | #phy-cells = <0>; | |
| 534 | status = "disabled"; | |
| 535 | }; | |
| f048b9a4 JX |
536 | }; |
| 537 | ||
| 538 | watchdog@ff840000 { | |
| 539 | compatible = "snps,dw-wdt"; | |
| 540 | reg = <0x0 0xff840000 0x0 0x100>; | |
| 541 | clocks = <&cru PCLK_WDT>; | |
| 542 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
| 543 | }; | |
| 544 | ||
| 545 | spdif: spdif@ff870000 { | |
| 546 | compatible = "rockchip,rk3399-spdif"; | |
| 547 | reg = <0x0 0xff870000 0x0 0x1000>; | |
| 548 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; | |
| 549 | dmas = <&dmac_bus 7>; | |
| 550 | dma-names = "tx"; | |
| 551 | clock-names = "mclk", "hclk"; | |
| 552 | clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; | |
| 553 | pinctrl-names = "default"; | |
| 554 | pinctrl-0 = <&spdif_bus>; | |
| 555 | status = "disabled"; | |
| 556 | }; | |
| 557 | ||
| 558 | i2s0: i2s@ff880000 { | |
| 559 | compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; | |
| 560 | reg = <0x0 0xff880000 0x0 0x1000>; | |
| 561 | rockchip,grf = <&grf>; | |
| 562 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
| 563 | dmas = <&dmac_bus 0>, <&dmac_bus 1>; | |
| 564 | dma-names = "tx", "rx"; | |
| 565 | clock-names = "i2s_clk", "i2s_hclk"; | |
| 566 | clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; | |
| 567 | pinctrl-names = "default"; | |
| 568 | pinctrl-0 = <&i2s0_8ch_bus>; | |
| 569 | status = "disabled"; | |
| 570 | }; | |
| 571 | ||
| 572 | i2s1: i2s@ff890000 { | |
| 573 | compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; | |
| 574 | reg = <0x0 0xff890000 0x0 0x1000>; | |
| 575 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
| 576 | dmas = <&dmac_bus 2>, <&dmac_bus 3>; | |
| 577 | dma-names = "tx", "rx"; | |
| 578 | clock-names = "i2s_clk", "i2s_hclk"; | |
| 579 | clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; | |
| 580 | pinctrl-names = "default"; | |
| 581 | pinctrl-0 = <&i2s1_2ch_bus>; | |
| 582 | status = "disabled"; | |
| 583 | }; | |
| 584 | ||
| 585 | i2s2: i2s@ff8a0000 { | |
| 586 | compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; | |
| 587 | reg = <0x0 0xff8a0000 0x0 0x1000>; | |
| 588 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
| 589 | dmas = <&dmac_bus 4>, <&dmac_bus 5>; | |
| 590 | dma-names = "tx", "rx"; | |
| 591 | clock-names = "i2s_clk", "i2s_hclk"; | |
| 592 | clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; | |
| 593 | status = "disabled"; | |
| 594 | }; | |
| 595 | ||
| 596 | pinctrl: pinctrl { | |
| 597 | compatible = "rockchip,rk3399-pinctrl"; | |
| 598 | rockchip,grf = <&grf>; | |
| 599 | rockchip,pmu = <&pmugrf>; | |
| 600 | #address-cells = <2>; | |
| 601 | #size-cells = <2>; | |
| 602 | ranges; | |
| 603 | ||
| 604 | gpio0: gpio0@ff720000 { | |
| 605 | compatible = "rockchip,gpio-bank"; | |
| 606 | reg = <0x0 0xff720000 0x0 0x100>; | |
| 607 | clocks = <&pmucru PCLK_GPIO0_PMU>; | |
| 608 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 609 | ||
| 610 | gpio-controller; | |
| 611 | #gpio-cells = <0x2>; | |
| 612 | ||
| 613 | interrupt-controller; | |
| 614 | #interrupt-cells = <0x2>; | |
| 615 | }; | |
| 616 | ||
| 617 | gpio1: gpio1@ff730000 { | |
| 618 | compatible = "rockchip,gpio-bank"; | |
| 619 | reg = <0x0 0xff730000 0x0 0x100>; | |
| 620 | clocks = <&pmucru PCLK_GPIO1_PMU>; | |
| 621 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
| 622 | ||
| 623 | gpio-controller; | |
| 624 | #gpio-cells = <0x2>; | |
| 625 | ||
| 626 | interrupt-controller; | |
| 627 | #interrupt-cells = <0x2>; | |
| 628 | }; | |
| 629 | ||
| 630 | gpio2: gpio2@ff780000 { | |
| 631 | compatible = "rockchip,gpio-bank"; | |
| 632 | reg = <0x0 0xff780000 0x0 0x100>; | |
| 633 | clocks = <&cru PCLK_GPIO2>; | |
| 634 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 635 | ||
| 636 | gpio-controller; | |
| 637 | #gpio-cells = <0x2>; | |
| 638 | ||
| 639 | interrupt-controller; | |
| 640 | #interrupt-cells = <0x2>; | |
| 641 | }; | |
| 642 | ||
| 643 | gpio3: gpio3@ff788000 { | |
| 644 | compatible = "rockchip,gpio-bank"; | |
| 645 | reg = <0x0 0xff788000 0x0 0x100>; | |
| 646 | clocks = <&cru PCLK_GPIO3>; | |
| 647 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 648 | ||
| 649 | gpio-controller; | |
| 650 | #gpio-cells = <0x2>; | |
| 651 | ||
| 652 | interrupt-controller; | |
| 653 | #interrupt-cells = <0x2>; | |
| 654 | }; | |
| 655 | ||
| 656 | gpio4: gpio4@ff790000 { | |
| 657 | compatible = "rockchip,gpio-bank"; | |
| 658 | reg = <0x0 0xff790000 0x0 0x100>; | |
| 659 | clocks = <&cru PCLK_GPIO4>; | |
| 660 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; | |
| 661 | ||
| 662 | gpio-controller; | |
| 663 | #gpio-cells = <0x2>; | |
| 664 | ||
| 665 | interrupt-controller; | |
| 666 | #interrupt-cells = <0x2>; | |
| 667 | }; | |
| 668 | ||
| 669 | pcfg_pull_up: pcfg-pull-up { | |
| 670 | bias-pull-up; | |
| 671 | }; | |
| 672 | ||
| 673 | pcfg_pull_down: pcfg-pull-down { | |
| 674 | bias-pull-down; | |
| 675 | }; | |
| 676 | ||
| 677 | pcfg_pull_none: pcfg-pull-none { | |
| 678 | bias-disable; | |
| 679 | }; | |
| 680 | ||
| 681 | pcfg_pull_none_12ma: pcfg-pull-none-12ma { | |
| 682 | bias-disable; | |
| 683 | drive-strength = <12>; | |
| 684 | }; | |
| 685 | ||
| 686 | pcfg_pull_up_8ma: pcfg-pull-up-8ma { | |
| 687 | bias-pull-up; | |
| 688 | drive-strength = <8>; | |
| 689 | }; | |
| 690 | ||
| 691 | pcfg_pull_down_4ma: pcfg-pull-down-4ma { | |
| 692 | bias-pull-down; | |
| 693 | drive-strength = <4>; | |
| 694 | }; | |
| 695 | ||
| 696 | pcfg_pull_up_2ma: pcfg-pull-up-2ma { | |
| 697 | bias-pull-up; | |
| 698 | drive-strength = <2>; | |
| 699 | }; | |
| 700 | ||
| 701 | pcfg_pull_down_12ma: pcfg-pull-down-12ma { | |
| 702 | bias-pull-down; | |
| 703 | drive-strength = <12>; | |
| 704 | }; | |
| 705 | ||
| 706 | pcfg_pull_none_13ma: pcfg-pull-none-13ma { | |
| 707 | bias-disable; | |
| 708 | drive-strength = <13>; | |
| 709 | }; | |
| 710 | ||
| 711 | i2c0 { | |
| 712 | i2c0_xfer: i2c0-xfer { | |
| 713 | rockchip,pins = | |
| 714 | <1 15 RK_FUNC_2 &pcfg_pull_none>, | |
| 715 | <1 16 RK_FUNC_2 &pcfg_pull_none>; | |
| 716 | }; | |
| 717 | }; | |
| 718 | ||
| 719 | i2c1 { | |
| 720 | i2c1_xfer: i2c1-xfer { | |
| 721 | rockchip,pins = | |
| 722 | <4 2 RK_FUNC_1 &pcfg_pull_none>, | |
| 723 | <4 1 RK_FUNC_1 &pcfg_pull_none>; | |
| 724 | }; | |
| 725 | }; | |
| 726 | ||
| 727 | i2c2 { | |
| 728 | i2c2_xfer: i2c2-xfer { | |
| 729 | rockchip,pins = | |
| 730 | <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, | |
| 731 | <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; | |
| 732 | }; | |
| 733 | }; | |
| 734 | ||
| 735 | i2c3 { | |
| 736 | i2c3_xfer: i2c3-xfer { | |
| 737 | rockchip,pins = | |
| 738 | <4 17 RK_FUNC_1 &pcfg_pull_none>, | |
| 739 | <4 16 RK_FUNC_1 &pcfg_pull_none>; | |
| 740 | }; | |
| 741 | }; | |
| 742 | ||
| 743 | i2c4 { | |
| 744 | i2c4_xfer: i2c4-xfer { | |
| 745 | rockchip,pins = | |
| 746 | <1 12 RK_FUNC_1 &pcfg_pull_none>, | |
| 747 | <1 11 RK_FUNC_1 &pcfg_pull_none>; | |
| 748 | }; | |
| 749 | }; | |
| 750 | ||
| 751 | i2c5 { | |
| 752 | i2c5_xfer: i2c5-xfer { | |
| 753 | rockchip,pins = | |
| 754 | <3 11 RK_FUNC_2 &pcfg_pull_none>, | |
| 755 | <3 10 RK_FUNC_2 &pcfg_pull_none>; | |
| 756 | }; | |
| 757 | }; | |
| 758 | ||
| 759 | i2c6 { | |
| 760 | i2c6_xfer: i2c6-xfer { | |
| 761 | rockchip,pins = | |
| 762 | <2 10 RK_FUNC_2 &pcfg_pull_none>, | |
| 763 | <2 9 RK_FUNC_2 &pcfg_pull_none>; | |
| 764 | }; | |
| 765 | }; | |
| 766 | ||
| 767 | i2c7 { | |
| 768 | i2c7_xfer: i2c7-xfer { | |
| 769 | rockchip,pins = | |
| 770 | <2 8 RK_FUNC_2 &pcfg_pull_none>, | |
| 771 | <2 7 RK_FUNC_2 &pcfg_pull_none>; | |
| 772 | }; | |
| 773 | }; | |
| 774 | ||
| 775 | i2c8 { | |
| 776 | i2c8_xfer: i2c8-xfer { | |
| 777 | rockchip,pins = | |
| 778 | <1 21 RK_FUNC_1 &pcfg_pull_none>, | |
| 779 | <1 20 RK_FUNC_1 &pcfg_pull_none>; | |
| 780 | }; | |
| 781 | }; | |
| 782 | ||
| 783 | i2s0 { | |
| 784 | i2s0_8ch_bus: i2s0-8ch-bus { | |
| 785 | rockchip,pins = | |
| 786 | <3 24 RK_FUNC_1 &pcfg_pull_none>, | |
| 787 | <3 25 RK_FUNC_1 &pcfg_pull_none>, | |
| 788 | <3 26 RK_FUNC_1 &pcfg_pull_none>, | |
| 789 | <3 27 RK_FUNC_1 &pcfg_pull_none>, | |
| 790 | <3 28 RK_FUNC_1 &pcfg_pull_none>, | |
| 791 | <3 29 RK_FUNC_1 &pcfg_pull_none>, | |
| 792 | <3 30 RK_FUNC_1 &pcfg_pull_none>, | |
| 793 | <3 31 RK_FUNC_1 &pcfg_pull_none>, | |
| 794 | <4 0 RK_FUNC_1 &pcfg_pull_none>; | |
| 795 | }; | |
| 796 | }; | |
| 797 | ||
| 798 | i2s1 { | |
| 799 | i2s1_2ch_bus: i2s1-2ch-bus { | |
| 800 | rockchip,pins = | |
| 801 | <4 3 RK_FUNC_1 &pcfg_pull_none>, | |
| 802 | <4 4 RK_FUNC_1 &pcfg_pull_none>, | |
| 803 | <4 5 RK_FUNC_1 &pcfg_pull_none>, | |
| 804 | <4 6 RK_FUNC_1 &pcfg_pull_none>, | |
| 805 | <4 7 RK_FUNC_1 &pcfg_pull_none>; | |
| 806 | }; | |
| 807 | }; | |
| 808 | ||
| 809 | spdif { | |
| 810 | spdif_bus: spdif-bus { | |
| 811 | rockchip,pins = | |
| 812 | <4 21 RK_FUNC_1 &pcfg_pull_none>; | |
| 813 | }; | |
| 814 | }; | |
| 815 | ||
| 816 | spi0 { | |
| 817 | spi0_clk: spi0-clk { | |
| 818 | rockchip,pins = | |
| 819 | <3 6 RK_FUNC_2 &pcfg_pull_up>; | |
| 820 | }; | |
| 821 | spi0_cs0: spi0-cs0 { | |
| 822 | rockchip,pins = | |
| 823 | <3 7 RK_FUNC_2 &pcfg_pull_up>; | |
| 824 | }; | |
| 825 | spi0_cs1: spi0-cs1 { | |
| 826 | rockchip,pins = | |
| 827 | <3 8 RK_FUNC_2 &pcfg_pull_up>; | |
| 828 | }; | |
| 829 | spi0_tx: spi0-tx { | |
| 830 | rockchip,pins = | |
| 831 | <3 5 RK_FUNC_2 &pcfg_pull_up>; | |
| 832 | }; | |
| 833 | spi0_rx: spi0-rx { | |
| 834 | rockchip,pins = | |
| 835 | <3 4 RK_FUNC_2 &pcfg_pull_up>; | |
| 836 | }; | |
| 837 | }; | |
| 838 | ||
| 839 | spi1 { | |
| 840 | spi1_clk: spi1-clk { | |
| 841 | rockchip,pins = | |
| 842 | <1 9 RK_FUNC_2 &pcfg_pull_up>; | |
| 843 | }; | |
| 844 | spi1_cs0: spi1-cs0 { | |
| 845 | rockchip,pins = | |
| 846 | <1 10 RK_FUNC_2 &pcfg_pull_up>; | |
| 847 | }; | |
| 848 | spi1_rx: spi1-rx { | |
| 849 | rockchip,pins = | |
| 850 | <1 7 RK_FUNC_2 &pcfg_pull_up>; | |
| 851 | }; | |
| 852 | spi1_tx: spi1-tx { | |
| 853 | rockchip,pins = | |
| 854 | <1 8 RK_FUNC_2 &pcfg_pull_up>; | |
| 855 | }; | |
| 856 | }; | |
| 857 | ||
| 858 | spi2 { | |
| 859 | spi2_clk: spi2-clk { | |
| 860 | rockchip,pins = | |
| 861 | <2 11 RK_FUNC_1 &pcfg_pull_up>; | |
| 862 | }; | |
| 863 | spi2_cs0: spi2-cs0 { | |
| 864 | rockchip,pins = | |
| 865 | <2 12 RK_FUNC_1 &pcfg_pull_up>; | |
| 866 | }; | |
| 867 | spi2_rx: spi2-rx { | |
| 868 | rockchip,pins = | |
| 869 | <2 9 RK_FUNC_1 &pcfg_pull_up>; | |
| 870 | }; | |
| 871 | spi2_tx: spi2-tx { | |
| 872 | rockchip,pins = | |
| 873 | <2 10 RK_FUNC_1 &pcfg_pull_up>; | |
| 874 | }; | |
| 875 | }; | |
| 876 | ||
| 877 | spi3 { | |
| 878 | spi3_clk: spi3-clk { | |
| 879 | rockchip,pins = | |
| 880 | <1 17 RK_FUNC_1 &pcfg_pull_up>; | |
| 881 | }; | |
| 882 | spi3_cs0: spi3-cs0 { | |
| 883 | rockchip,pins = | |
| 884 | <1 18 RK_FUNC_1 &pcfg_pull_up>; | |
| 885 | }; | |
| 886 | spi3_rx: spi3-rx { | |
| 887 | rockchip,pins = | |
| 888 | <1 15 RK_FUNC_1 &pcfg_pull_up>; | |
| 889 | }; | |
| 890 | spi3_tx: spi3-tx { | |
| 891 | rockchip,pins = | |
| 892 | <1 16 RK_FUNC_1 &pcfg_pull_up>; | |
| 893 | }; | |
| 894 | }; | |
| 895 | ||
| 896 | spi4 { | |
| 897 | spi4_clk: spi4-clk { | |
| 898 | rockchip,pins = | |
| 899 | <3 2 RK_FUNC_2 &pcfg_pull_up>; | |
| 900 | }; | |
| 901 | spi4_cs0: spi4-cs0 { | |
| 902 | rockchip,pins = | |
| 903 | <3 3 RK_FUNC_2 &pcfg_pull_up>; | |
| 904 | }; | |
| 905 | spi4_rx: spi4-rx { | |
| 906 | rockchip,pins = | |
| 907 | <3 0 RK_FUNC_2 &pcfg_pull_up>; | |
| 908 | }; | |
| 909 | spi4_tx: spi4-tx { | |
| 910 | rockchip,pins = | |
| 911 | <3 1 RK_FUNC_2 &pcfg_pull_up>; | |
| 912 | }; | |
| 913 | }; | |
| 914 | ||
| 915 | spi5 { | |
| 916 | spi5_clk: spi5-clk { | |
| 917 | rockchip,pins = | |
| 918 | <2 22 RK_FUNC_2 &pcfg_pull_up>; | |
| 919 | }; | |
| 920 | spi5_cs0: spi5-cs0 { | |
| 921 | rockchip,pins = | |
| 922 | <2 23 RK_FUNC_2 &pcfg_pull_up>; | |
| 923 | }; | |
| 924 | spi5_rx: spi5-rx { | |
| 925 | rockchip,pins = | |
| 926 | <2 20 RK_FUNC_2 &pcfg_pull_up>; | |
| 927 | }; | |
| 928 | spi5_tx: spi5-tx { | |
| 929 | rockchip,pins = | |
| 930 | <2 21 RK_FUNC_2 &pcfg_pull_up>; | |
| 931 | }; | |
| 932 | }; | |
| 933 | ||
| 934 | uart0 { | |
| 935 | uart0_xfer: uart0-xfer { | |
| 936 | rockchip,pins = | |
| 937 | <2 16 RK_FUNC_1 &pcfg_pull_up>, | |
| 938 | <2 17 RK_FUNC_1 &pcfg_pull_none>; | |
| 939 | }; | |
| 940 | ||
| 941 | uart0_cts: uart0-cts { | |
| 942 | rockchip,pins = | |
| 943 | <2 18 RK_FUNC_1 &pcfg_pull_none>; | |
| 944 | }; | |
| 945 | ||
| 946 | uart0_rts: uart0-rts { | |
| 947 | rockchip,pins = | |
| 948 | <2 19 RK_FUNC_1 &pcfg_pull_none>; | |
| 949 | }; | |
| 950 | }; | |
| 951 | ||
| 952 | uart1 { | |
| 953 | uart1_xfer: uart1-xfer { | |
| 954 | rockchip,pins = | |
| 955 | <3 12 RK_FUNC_2 &pcfg_pull_up>, | |
| 956 | <3 13 RK_FUNC_2 &pcfg_pull_none>; | |
| 957 | }; | |
| 958 | }; | |
| 959 | ||
| 960 | uart2a { | |
| 961 | uart2a_xfer: uart2a-xfer { | |
| 962 | rockchip,pins = | |
| 963 | <4 8 RK_FUNC_2 &pcfg_pull_up>, | |
| 964 | <4 9 RK_FUNC_2 &pcfg_pull_none>; | |
| 965 | }; | |
| 966 | }; | |
| 967 | ||
| 968 | uart2b { | |
| 969 | uart2b_xfer: uart2b-xfer { | |
| 970 | rockchip,pins = | |
| 971 | <4 16 RK_FUNC_2 &pcfg_pull_up>, | |
| 972 | <4 17 RK_FUNC_2 &pcfg_pull_none>; | |
| 973 | }; | |
| 974 | }; | |
| 975 | ||
| 976 | uart2c { | |
| 977 | uart2c_xfer: uart2c-xfer { | |
| 978 | rockchip,pins = | |
| 979 | <4 19 RK_FUNC_1 &pcfg_pull_up>, | |
| 980 | <4 20 RK_FUNC_1 &pcfg_pull_none>; | |
| 981 | }; | |
| 982 | }; | |
| 983 | ||
| 984 | uart3 { | |
| 985 | uart3_xfer: uart3-xfer { | |
| 986 | rockchip,pins = | |
| 987 | <3 14 RK_FUNC_2 &pcfg_pull_up>, | |
| 988 | <3 15 RK_FUNC_2 &pcfg_pull_none>; | |
| 989 | }; | |
| 990 | ||
| 991 | uart3_cts: uart3-cts { | |
| 992 | rockchip,pins = | |
| 993 | <3 18 RK_FUNC_2 &pcfg_pull_none>; | |
| 994 | }; | |
| 995 | ||
| 996 | uart3_rts: uart3-rts { | |
| 997 | rockchip,pins = | |
| 998 | <3 19 RK_FUNC_2 &pcfg_pull_none>; | |
| 999 | }; | |
| 1000 | }; | |
| 1001 | ||
| 1002 | uart4 { | |
| 1003 | uart4_xfer: uart4-xfer { | |
| 1004 | rockchip,pins = | |
| 1005 | <1 7 RK_FUNC_1 &pcfg_pull_up>, | |
| 1006 | <1 8 RK_FUNC_1 &pcfg_pull_none>; | |
| 1007 | }; | |
| 1008 | }; | |
| 1009 | ||
| 1010 | uarthdcp { | |
| 1011 | uarthdcp_xfer: uarthdcp-xfer { | |
| 1012 | rockchip,pins = | |
| 1013 | <4 21 RK_FUNC_2 &pcfg_pull_up>, | |
| 1014 | <4 22 RK_FUNC_2 &pcfg_pull_none>; | |
| 1015 | }; | |
| 1016 | }; | |
| 1017 | ||
| 1018 | pwm0 { | |
| 1019 | pwm0_pin: pwm0-pin { | |
| 1020 | rockchip,pins = | |
| 1021 | <4 18 RK_FUNC_1 &pcfg_pull_none>; | |
| 1022 | }; | |
| 1023 | ||
| 1024 | vop0_pwm_pin: vop0-pwm-pin { | |
| 1025 | rockchip,pins = | |
| 1026 | <4 18 RK_FUNC_2 &pcfg_pull_none>; | |
| 1027 | }; | |
| 1028 | }; | |
| 1029 | ||
| 1030 | pwm1 { | |
| 1031 | pwm1_pin: pwm1-pin { | |
| 1032 | rockchip,pins = | |
| 1033 | <4 22 RK_FUNC_1 &pcfg_pull_none>; | |
| 1034 | }; | |
| 1035 | ||
| 1036 | vop1_pwm_pin: vop1-pwm-pin { | |
| 1037 | rockchip,pins = | |
| 1038 | <4 18 RK_FUNC_3 &pcfg_pull_none>; | |
| 1039 | }; | |
| 1040 | }; | |
| 1041 | ||
| 1042 | pwm2 { | |
| 1043 | pwm2_pin: pwm2-pin { | |
| 1044 | rockchip,pins = | |
| 1045 | <1 19 RK_FUNC_1 &pcfg_pull_none>; | |
| 1046 | }; | |
| 1047 | }; | |
| 1048 | ||
| 1049 | pwm3a { | |
| 1050 | pwm3a_pin: pwm3a-pin { | |
| 1051 | rockchip,pins = | |
| 1052 | <0 6 RK_FUNC_1 &pcfg_pull_none>; | |
| 1053 | }; | |
| 1054 | }; | |
| 1055 | ||
| 1056 | pwm3b { | |
| 1057 | pwm3b_pin: pwm3b-pin { | |
| 1058 | rockchip,pins = | |
| 1059 | <1 14 RK_FUNC_1 &pcfg_pull_none>; | |
| 1060 | }; | |
| 1061 | }; | |
| 1062 | }; | |
| 1063 | }; |