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arm64: dts: rockchip: add sdhci/emmc for rk3399
[deliverable/linux.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi
CommitLineData
f048b9a4
JX		 1/*
2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/clock/rk3399-cru.h>
44#include <dt-bindings/gpio/gpio.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/interrupt-controller/irq.h>
47#include <dt-bindings/pinctrl/rockchip.h>
48
49/ {
50 compatible = "rockchip,rk3399";
51
52 interrupt-parent = <&gic>;
53 #address-cells = <2>;
54 #size-cells = <2>;
55
56 aliases {
57 serial0 = &uart0;
58 serial1 = &uart1;
59 serial2 = &uart2;
60 serial3 = &uart3;
61 serial4 = &uart4;
62 };
63
64 cpus {
65 #address-cells = <2>;
66 #size-cells = <0>;
67
68 cpu-map {
69 cluster0 {
70 core0 {
71 cpu = <&cpu_l0>;
72 };
73 core1 {
74 cpu = <&cpu_l1>;
75 };
76 core2 {
77 cpu = <&cpu_l2>;
78 };
79 core3 {
80 cpu = <&cpu_l3>;
81 };
82 };
83
84 cluster1 {
85 core0 {
86 cpu = <&cpu_b0>;
87 };
88 core1 {
89 cpu = <&cpu_b1>;
90 };
91 };
92 };
93
94 cpu_l0: cpu@0 {
95 device_type = "cpu";
96 compatible = "arm,cortex-a53", "arm,armv8";
97 reg = <0x0 0x0>;
98 enable-method = "psci";
99 #cooling-cells = <2>; /* min followed by max */
100 clocks = <&cru ARMCLKL>;
101 };
102
103 cpu_l1: cpu@1 {
104 device_type = "cpu";
105 compatible = "arm,cortex-a53", "arm,armv8";
106 reg = <0x0 0x1>;
107 enable-method = "psci";
108 clocks = <&cru ARMCLKL>;
109 };
110
111 cpu_l2: cpu@2 {
112 device_type = "cpu";
113 compatible = "arm,cortex-a53", "arm,armv8";
114 reg = <0x0 0x2>;
115 enable-method = "psci";
116 clocks = <&cru ARMCLKL>;
117 };
118
119 cpu_l3: cpu@3 {
120 device_type = "cpu";
121 compatible = "arm,cortex-a53", "arm,armv8";
122 reg = <0x0 0x3>;
123 enable-method = "psci";
124 clocks = <&cru ARMCLKL>;
125 };
126
127 cpu_b0: cpu@100 {
128 device_type = "cpu";
129 compatible = "arm,cortex-a72", "arm,armv8";
130 reg = <0x0 0x100>;
131 enable-method = "psci";
132 #cooling-cells = <2>; /* min followed by max */
133 clocks = <&cru ARMCLKB>;
134 };
135
136 cpu_b1: cpu@101 {
137 device_type = "cpu";
138 compatible = "arm,cortex-a72", "arm,armv8";
139 reg = <0x0 0x101>;
140 enable-method = "psci";
141 clocks = <&cru ARMCLKB>;
142 };
143 };
144
145 psci {
146 compatible = "arm,psci-1.0";
147 method = "smc";
148 };
149
150 timer {
151 compatible = "arm,armv8-timer";
152 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
153 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
154 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
155 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
156 };
157
158 xin24m: xin24m {
159 compatible = "fixed-clock";
160 clock-frequency = <24000000>;
161 clock-output-names = "xin24m";
162 #clock-cells = <0>;
163 };
164
165 amba {
166 compatible = "arm,amba-bus";
167 #address-cells = <2>;
168 #size-cells = <2>;
169 ranges;
170
171 dmac_bus: dma-controller@ff6d0000 {
172 compatible = "arm,pl330", "arm,primecell";
173 reg = <0x0 0xff6d0000 0x0 0x4000>;
174 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
176 #dma-cells = <1>;
177 clocks = <&cru ACLK_DMAC0_PERILP>;
178 clock-names = "apb_pclk";
179 };
180
181 dmac_peri: dma-controller@ff6e0000 {
182 compatible = "arm,pl330", "arm,primecell";
183 reg = <0x0 0xff6e0000 0x0 0x4000>;
184 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
186 #dma-cells = <1>;
187 clocks = <&cru ACLK_DMAC1_PERILP>;
188 clock-names = "apb_pclk";
189 };
190 };
191
192 sdio0: dwmmc@fe310000 {
193 compatible = "rockchip,rk3399-dw-mshc",
194 "rockchip,rk3288-dw-mshc";
195 reg = <0x0 0xfe310000 0x0 0x4000>;
196 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
197 clock-freq-min-max = <400000 150000000>;
198 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
199 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
200 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
201 fifo-depth = <0x100>;
202 status = "disabled";
203 };
204
205 sdmmc: dwmmc@fe320000 {
206 compatible = "rockchip,rk3399-dw-mshc",
207 "rockchip,rk3288-dw-mshc";
208 reg = <0x0 0xfe320000 0x0 0x4000>;
209 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
210 clock-freq-min-max = <400000 150000000>;
211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
212 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214 fifo-depth = <0x100>;
215 status = "disabled";
216 };
217
b4e87c09
BN		 218 sdhci: sdhci@fe330000 {
219 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
220 reg = <0x0 0xfe330000 0x0 0x10000>;
221 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
222 assigned-clocks = <&cru SCLK_EMMC>;
223 assigned-clock-rates = <200000000>;
224 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
225 clock-names = "clk_xin", "clk_ahb";
226 phys = <&emmc_phy>;
227 phy-names = "phy_arasan";
228 status = "disabled";
229 };
230
f048b9a4
JX		 231 usb_host0_ehci: usb@fe380000 {
232 compatible = "generic-ehci";
233 reg = <0x0 0xfe380000 0x0 0x20000>;
234 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
236 clock-names = "hclk_host0", "hclk_host0_arb";
237 status = "disabled";
238 };
239
240 usb_host0_ohci: usb@fe3a0000 {
241 compatible = "generic-ohci";
242 reg = <0x0 0xfe3a0000 0x0 0x20000>;
243 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
245 clock-names = "hclk_host0", "hclk_host0_arb";
246 status = "disabled";
247 };
248
249 usb_host1_ehci: usb@fe3c0000 {
250 compatible = "generic-ehci";
251 reg = <0x0 0xfe3c0000 0x0 0x20000>;
252 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
254 clock-names = "hclk_host1", "hclk_host1_arb";
255 status = "disabled";
256 };
257
258 usb_host1_ohci: usb@fe3e0000 {
259 compatible = "generic-ohci";
260 reg = <0x0 0xfe3e0000 0x0 0x20000>;
261 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
263 clock-names = "hclk_host1", "hclk_host1_arb";
264 status = "disabled";
265 };
266
267 gic: interrupt-controller@fee00000 {
268 compatible = "arm,gic-v3";
269 #interrupt-cells = <3>;
270 #address-cells = <2>;
271 #size-cells = <2>;
272 ranges;
273 interrupt-controller;
274
275 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
276 <0x0 0xfef00000 0 0xc0000>, /* GICR */
277 <0x0 0xfff00000 0 0x10000>, /* GICC */
278 <0x0 0xfff10000 0 0x10000>, /* GICH */
279 <0x0 0xfff20000 0 0x10000>; /* GICV */
280 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
281 its: interrupt-controller@fee20000 {
282 compatible = "arm,gic-v3-its";
283 msi-controller;
284 reg = <0x0 0xfee20000 0x0 0x20000>;
285 };
286 };
287
288 uart0: serial@ff180000 {
289 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
290 reg = <0x0 0xff180000 0x0 0x100>;
291 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
292 clock-names = "baudclk", "apb_pclk";
293 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
294 reg-shift = <2>;
295 reg-io-width = <4>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&uart0_xfer>;
298 status = "disabled";
299 };
300
301 uart1: serial@ff190000 {
302 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
303 reg = <0x0 0xff190000 0x0 0x100>;
304 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
305 clock-names = "baudclk", "apb_pclk";
306 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
307 reg-shift = <2>;
308 reg-io-width = <4>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&uart1_xfer>;
311 status = "disabled";
312 };
313
314 uart2: serial@ff1a0000 {
315 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
316 reg = <0x0 0xff1a0000 0x0 0x100>;
317 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
318 clock-names = "baudclk", "apb_pclk";
319 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
320 reg-shift = <2>;
321 reg-io-width = <4>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&uart2c_xfer>;
324 status = "disabled";
325 };
326
327 uart3: serial@ff1b0000 {
328 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
329 reg = <0x0 0xff1b0000 0x0 0x100>;
330 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
331 clock-names = "baudclk", "apb_pclk";
332 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
333 reg-shift = <2>;
334 reg-io-width = <4>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&uart3_xfer>;
337 status = "disabled";
338 };
339
340 spi0: spi@ff1c0000 {
341 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
342 reg = <0x0 0xff1c0000 0x0 0x1000>;
343 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
344 clock-names = "spiclk", "apb_pclk";
345 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 status = "disabled";
351 };
352
353 spi1: spi@ff1d0000 {
354 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
355 reg = <0x0 0xff1d0000 0x0 0x1000>;
356 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
357 clock-names = "spiclk", "apb_pclk";
358 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363 status = "disabled";
364 };
365
366 spi2: spi@ff1e0000 {
367 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
368 reg = <0x0 0xff1e0000 0x0 0x1000>;
369 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
370 clock-names = "spiclk", "apb_pclk";
371 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
374 #address-cells = <1>;
375 #size-cells = <0>;
376 status = "disabled";
377 };
378
379 spi4: spi@ff1f0000 {
380 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
381 reg = <0x0 0xff1f0000 0x0 0x1000>;
382 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
383 clock-names = "spiclk", "apb_pclk";
384 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 status = "disabled";
390 };
391
392 spi5: spi@ff200000 {
393 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
394 reg = <0x0 0xff200000 0x0 0x1000>;
395 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
396 clock-names = "spiclk", "apb_pclk";
397 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
400 #address-cells = <1>;
401 #size-cells = <0>;
402 status = "disabled";
403 };
404
405 pmugrf: syscon@ff320000 {
16759262 406 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
f048b9a4 407 reg = <0x0 0xff320000 0x0 0x1000>;
16759262
BN		 408 #address-cells = <1>;
409 #size-cells = <1>;
f048b9a4
JX		 410 };
411
412 spi3: spi@ff350000 {
413 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
414 reg = <0x0 0xff350000 0x0 0x1000>;
415 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
416 clock-names = "spiclk", "apb_pclk";
417 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
420 #address-cells = <1>;
421 #size-cells = <0>;
422 status = "disabled";
423 };
424
425 uart4: serial@ff370000 {
426 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
427 reg = <0x0 0xff370000 0x0 0x100>;
428 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
429 clock-names = "baudclk", "apb_pclk";
430 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
431 reg-shift = <2>;
432 reg-io-width = <4>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&uart4_xfer>;
435 status = "disabled";
436 };
437
438 pwm0: pwm@ff420000 {
439 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
440 reg = <0x0 0xff420000 0x0 0x10>;
441 #pwm-cells = <3>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&pwm0_pin>;
444 clocks = <&pmucru PCLK_RKPWM_PMU>;
445 clock-names = "pwm";
446 status = "disabled";
447 };
448
449 pwm1: pwm@ff420010 {
450 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
451 reg = <0x0 0xff420010 0x0 0x10>;
452 #pwm-cells = <3>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&pwm1_pin>;
455 clocks = <&pmucru PCLK_RKPWM_PMU>;
456 clock-names = "pwm";
457 status = "disabled";
458 };
459
460 pwm2: pwm@ff420020 {
461 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
462 reg = <0x0 0xff420020 0x0 0x10>;
463 #pwm-cells = <3>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&pwm2_pin>;
466 clocks = <&pmucru PCLK_RKPWM_PMU>;
467 clock-names = "pwm";
468 status = "disabled";
469 };
470
471 pwm3: pwm@ff420030 {
472 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
473 reg = <0x0 0xff420030 0x0 0x10>;
474 #pwm-cells = <3>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&pwm3a_pin>;
477 clocks = <&pmucru PCLK_RKPWM_PMU>;
478 clock-names = "pwm";
479 status = "disabled";
480 };
481
482 pmucru: pmu-clock-controller@ff750000 {
483 compatible = "rockchip,rk3399-pmucru";
484 reg = <0x0 0xff750000 0x0 0x1000>;
485 #clock-cells = <1>;
486 #reset-cells = <1>;
487 assigned-clocks = <&pmucru PLL_PPLL>;
488 assigned-clock-rates = <676000000>;
489 };
490
491 cru: clock-controller@ff760000 {
492 compatible = "rockchip,rk3399-cru";
493 reg = <0x0 0xff760000 0x0 0x1000>;
494 #clock-cells = <1>;
495 #reset-cells = <1>;
a09906cd
XZ		 496 assigned-clocks =
497 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
498 <&cru PLL_NPLL>,
499 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
500 <&cru PCLK_PERIHP>,
501 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
502 <&cru PCLK_PERILP0>,
503 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
504 assigned-clock-rates =
505 <594000000>, <800000000>,
506 <1000000000>,
507 <150000000>, <75000000>,
508 <37500000>,
509 <100000000>, <100000000>,
510 <50000000>,
511 <100000000>, <50000000>;
f048b9a4
JX		 512 };
513
514 grf: syscon@ff770000 {
16759262 515 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
f048b9a4 516 reg = <0x0 0xff770000 0x0 0x10000>;
16759262
BN		 517 #address-cells = <1>;
518 #size-cells = <1>;
b4e87c09
BN		 519
520 emmc_phy: phy@f780 {
521 compatible = "rockchip,rk3399-emmc-phy";
522 reg = <0xf780 0x24>;
523 #phy-cells = <0>;
524 status = "disabled";
525 };
f048b9a4
JX		 526 };
527
528 watchdog@ff840000 {
529 compatible = "snps,dw-wdt";
530 reg = <0x0 0xff840000 0x0 0x100>;
531 clocks = <&cru PCLK_WDT>;
532 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
533 };
534
535 spdif: spdif@ff870000 {
536 compatible = "rockchip,rk3399-spdif";
537 reg = <0x0 0xff870000 0x0 0x1000>;
538 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
539 dmas = <&dmac_bus 7>;
540 dma-names = "tx";
541 clock-names = "mclk", "hclk";
542 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
543 pinctrl-names = "default";
544 pinctrl-0 = <&spdif_bus>;
545 status = "disabled";
546 };
547
548 i2s0: i2s@ff880000 {
549 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
550 reg = <0x0 0xff880000 0x0 0x1000>;
551 rockchip,grf = <&grf>;
552 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
553 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
554 dma-names = "tx", "rx";
555 clock-names = "i2s_clk", "i2s_hclk";
556 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&i2s0_8ch_bus>;
559 status = "disabled";
560 };
561
562 i2s1: i2s@ff890000 {
563 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
564 reg = <0x0 0xff890000 0x0 0x1000>;
565 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
566 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
567 dma-names = "tx", "rx";
568 clock-names = "i2s_clk", "i2s_hclk";
569 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&i2s1_2ch_bus>;
572 status = "disabled";
573 };
574
575 i2s2: i2s@ff8a0000 {
576 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
577 reg = <0x0 0xff8a0000 0x0 0x1000>;
578 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
579 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
580 dma-names = "tx", "rx";
581 clock-names = "i2s_clk", "i2s_hclk";
582 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
583 status = "disabled";
584 };
585
586 pinctrl: pinctrl {
587 compatible = "rockchip,rk3399-pinctrl";
588 rockchip,grf = <&grf>;
589 rockchip,pmu = <&pmugrf>;
590 #address-cells = <2>;
591 #size-cells = <2>;
592 ranges;
593
594 gpio0: gpio0@ff720000 {
595 compatible = "rockchip,gpio-bank";
596 reg = <0x0 0xff720000 0x0 0x100>;
597 clocks = <&pmucru PCLK_GPIO0_PMU>;
598 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
599
600 gpio-controller;
601 #gpio-cells = <0x2>;
602
603 interrupt-controller;
604 #interrupt-cells = <0x2>;
605 };
606
607 gpio1: gpio1@ff730000 {
608 compatible = "rockchip,gpio-bank";
609 reg = <0x0 0xff730000 0x0 0x100>;
610 clocks = <&pmucru PCLK_GPIO1_PMU>;
611 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
612
613 gpio-controller;
614 #gpio-cells = <0x2>;
615
616 interrupt-controller;
617 #interrupt-cells = <0x2>;
618 };
619
620 gpio2: gpio2@ff780000 {
621 compatible = "rockchip,gpio-bank";
622 reg = <0x0 0xff780000 0x0 0x100>;
623 clocks = <&cru PCLK_GPIO2>;
624 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
625
626 gpio-controller;
627 #gpio-cells = <0x2>;
628
629 interrupt-controller;
630 #interrupt-cells = <0x2>;
631 };
632
633 gpio3: gpio3@ff788000 {
634 compatible = "rockchip,gpio-bank";
635 reg = <0x0 0xff788000 0x0 0x100>;
636 clocks = <&cru PCLK_GPIO3>;
637 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
638
639 gpio-controller;
640 #gpio-cells = <0x2>;
641
642 interrupt-controller;
643 #interrupt-cells = <0x2>;
644 };
645
646 gpio4: gpio4@ff790000 {
647 compatible = "rockchip,gpio-bank";
648 reg = <0x0 0xff790000 0x0 0x100>;
649 clocks = <&cru PCLK_GPIO4>;
650 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
651
652 gpio-controller;
653 #gpio-cells = <0x2>;
654
655 interrupt-controller;
656 #interrupt-cells = <0x2>;
657 };
658
659 pcfg_pull_up: pcfg-pull-up {
660 bias-pull-up;
661 };
662
663 pcfg_pull_down: pcfg-pull-down {
664 bias-pull-down;
665 };
666
667 pcfg_pull_none: pcfg-pull-none {
668 bias-disable;
669 };
670
671 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
672 bias-disable;
673 drive-strength = <12>;
674 };
675
676 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
677 bias-pull-up;
678 drive-strength = <8>;
679 };
680
681 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
682 bias-pull-down;
683 drive-strength = <4>;
684 };
685
686 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
687 bias-pull-up;
688 drive-strength = <2>;
689 };
690
691 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
692 bias-pull-down;
693 drive-strength = <12>;
694 };
695
696 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
697 bias-disable;
698 drive-strength = <13>;
699 };
700
701 i2c0 {
702 i2c0_xfer: i2c0-xfer {
703 rockchip,pins =
704 <1 15 RK_FUNC_2 &pcfg_pull_none>,
705 <1 16 RK_FUNC_2 &pcfg_pull_none>;
706 };
707 };
708
709 i2c1 {
710 i2c1_xfer: i2c1-xfer {
711 rockchip,pins =
712 <4 2 RK_FUNC_1 &pcfg_pull_none>,
713 <4 1 RK_FUNC_1 &pcfg_pull_none>;
714 };
715 };
716
717 i2c2 {
718 i2c2_xfer: i2c2-xfer {
719 rockchip,pins =
720 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
721 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
722 };
723 };
724
725 i2c3 {
726 i2c3_xfer: i2c3-xfer {
727 rockchip,pins =
728 <4 17 RK_FUNC_1 &pcfg_pull_none>,
729 <4 16 RK_FUNC_1 &pcfg_pull_none>;
730 };
731 };
732
733 i2c4 {
734 i2c4_xfer: i2c4-xfer {
735 rockchip,pins =
736 <1 12 RK_FUNC_1 &pcfg_pull_none>,
737 <1 11 RK_FUNC_1 &pcfg_pull_none>;
738 };
739 };
740
741 i2c5 {
742 i2c5_xfer: i2c5-xfer {
743 rockchip,pins =
744 <3 11 RK_FUNC_2 &pcfg_pull_none>,
745 <3 10 RK_FUNC_2 &pcfg_pull_none>;
746 };
747 };
748
749 i2c6 {
750 i2c6_xfer: i2c6-xfer {
751 rockchip,pins =
752 <2 10 RK_FUNC_2 &pcfg_pull_none>,
753 <2 9 RK_FUNC_2 &pcfg_pull_none>;
754 };
755 };
756
757 i2c7 {
758 i2c7_xfer: i2c7-xfer {
759 rockchip,pins =
760 <2 8 RK_FUNC_2 &pcfg_pull_none>,
761 <2 7 RK_FUNC_2 &pcfg_pull_none>;
762 };
763 };
764
765 i2c8 {
766 i2c8_xfer: i2c8-xfer {
767 rockchip,pins =
768 <1 21 RK_FUNC_1 &pcfg_pull_none>,
769 <1 20 RK_FUNC_1 &pcfg_pull_none>;
770 };
771 };
772
773 i2s0 {
774 i2s0_8ch_bus: i2s0-8ch-bus {
775 rockchip,pins =
776 <3 24 RK_FUNC_1 &pcfg_pull_none>,
777 <3 25 RK_FUNC_1 &pcfg_pull_none>,
778 <3 26 RK_FUNC_1 &pcfg_pull_none>,
779 <3 27 RK_FUNC_1 &pcfg_pull_none>,
780 <3 28 RK_FUNC_1 &pcfg_pull_none>,
781 <3 29 RK_FUNC_1 &pcfg_pull_none>,
782 <3 30 RK_FUNC_1 &pcfg_pull_none>,
783 <3 31 RK_FUNC_1 &pcfg_pull_none>,
784 <4 0 RK_FUNC_1 &pcfg_pull_none>;
785 };
786 };
787
788 i2s1 {
789 i2s1_2ch_bus: i2s1-2ch-bus {
790 rockchip,pins =
791 <4 3 RK_FUNC_1 &pcfg_pull_none>,
792 <4 4 RK_FUNC_1 &pcfg_pull_none>,
793 <4 5 RK_FUNC_1 &pcfg_pull_none>,
794 <4 6 RK_FUNC_1 &pcfg_pull_none>,
795 <4 7 RK_FUNC_1 &pcfg_pull_none>;
796 };
797 };
798
799 spdif {
800 spdif_bus: spdif-bus {
801 rockchip,pins =
802 <4 21 RK_FUNC_1 &pcfg_pull_none>;
803 };
804 };
805
806 spi0 {
807 spi0_clk: spi0-clk {
808 rockchip,pins =
809 <3 6 RK_FUNC_2 &pcfg_pull_up>;
810 };
811 spi0_cs0: spi0-cs0 {
812 rockchip,pins =
813 <3 7 RK_FUNC_2 &pcfg_pull_up>;
814 };
815 spi0_cs1: spi0-cs1 {
816 rockchip,pins =
817 <3 8 RK_FUNC_2 &pcfg_pull_up>;
818 };
819 spi0_tx: spi0-tx {
820 rockchip,pins =
821 <3 5 RK_FUNC_2 &pcfg_pull_up>;
822 };
823 spi0_rx: spi0-rx {
824 rockchip,pins =
825 <3 4 RK_FUNC_2 &pcfg_pull_up>;
826 };
827 };
828
829 spi1 {
830 spi1_clk: spi1-clk {
831 rockchip,pins =
832 <1 9 RK_FUNC_2 &pcfg_pull_up>;
833 };
834 spi1_cs0: spi1-cs0 {
835 rockchip,pins =
836 <1 10 RK_FUNC_2 &pcfg_pull_up>;
837 };
838 spi1_rx: spi1-rx {
839 rockchip,pins =
840 <1 7 RK_FUNC_2 &pcfg_pull_up>;
841 };
842 spi1_tx: spi1-tx {
843 rockchip,pins =
844 <1 8 RK_FUNC_2 &pcfg_pull_up>;
845 };
846 };
847
848 spi2 {
849 spi2_clk: spi2-clk {
850 rockchip,pins =
851 <2 11 RK_FUNC_1 &pcfg_pull_up>;
852 };
853 spi2_cs0: spi2-cs0 {
854 rockchip,pins =
855 <2 12 RK_FUNC_1 &pcfg_pull_up>;
856 };
857 spi2_rx: spi2-rx {
858 rockchip,pins =
859 <2 9 RK_FUNC_1 &pcfg_pull_up>;
860 };
861 spi2_tx: spi2-tx {
862 rockchip,pins =
863 <2 10 RK_FUNC_1 &pcfg_pull_up>;
864 };
865 };
866
867 spi3 {
868 spi3_clk: spi3-clk {
869 rockchip,pins =
870 <1 17 RK_FUNC_1 &pcfg_pull_up>;
871 };
872 spi3_cs0: spi3-cs0 {
873 rockchip,pins =
874 <1 18 RK_FUNC_1 &pcfg_pull_up>;
875 };
876 spi3_rx: spi3-rx {
877 rockchip,pins =
878 <1 15 RK_FUNC_1 &pcfg_pull_up>;
879 };
880 spi3_tx: spi3-tx {
881 rockchip,pins =
882 <1 16 RK_FUNC_1 &pcfg_pull_up>;
883 };
884 };
885
886 spi4 {
887 spi4_clk: spi4-clk {
888 rockchip,pins =
889 <3 2 RK_FUNC_2 &pcfg_pull_up>;
890 };
891 spi4_cs0: spi4-cs0 {
892 rockchip,pins =
893 <3 3 RK_FUNC_2 &pcfg_pull_up>;
894 };
895 spi4_rx: spi4-rx {
896 rockchip,pins =
897 <3 0 RK_FUNC_2 &pcfg_pull_up>;
898 };
899 spi4_tx: spi4-tx {
900 rockchip,pins =
901 <3 1 RK_FUNC_2 &pcfg_pull_up>;
902 };
903 };
904
905 spi5 {
906 spi5_clk: spi5-clk {
907 rockchip,pins =
908 <2 22 RK_FUNC_2 &pcfg_pull_up>;
909 };
910 spi5_cs0: spi5-cs0 {
911 rockchip,pins =
912 <2 23 RK_FUNC_2 &pcfg_pull_up>;
913 };
914 spi5_rx: spi5-rx {
915 rockchip,pins =
916 <2 20 RK_FUNC_2 &pcfg_pull_up>;
917 };
918 spi5_tx: spi5-tx {
919 rockchip,pins =
920 <2 21 RK_FUNC_2 &pcfg_pull_up>;
921 };
922 };
923
924 uart0 {
925 uart0_xfer: uart0-xfer {
926 rockchip,pins =
927 <2 16 RK_FUNC_1 &pcfg_pull_up>,
928 <2 17 RK_FUNC_1 &pcfg_pull_none>;
929 };
930
931 uart0_cts: uart0-cts {
932 rockchip,pins =
933 <2 18 RK_FUNC_1 &pcfg_pull_none>;
934 };
935
936 uart0_rts: uart0-rts {
937 rockchip,pins =
938 <2 19 RK_FUNC_1 &pcfg_pull_none>;
939 };
940 };
941
942 uart1 {
943 uart1_xfer: uart1-xfer {
944 rockchip,pins =
945 <3 12 RK_FUNC_2 &pcfg_pull_up>,
946 <3 13 RK_FUNC_2 &pcfg_pull_none>;
947 };
948 };
949
950 uart2a {
951 uart2a_xfer: uart2a-xfer {
952 rockchip,pins =
953 <4 8 RK_FUNC_2 &pcfg_pull_up>,
954 <4 9 RK_FUNC_2 &pcfg_pull_none>;
955 };
956 };
957
958 uart2b {
959 uart2b_xfer: uart2b-xfer {
960 rockchip,pins =
961 <4 16 RK_FUNC_2 &pcfg_pull_up>,
962 <4 17 RK_FUNC_2 &pcfg_pull_none>;
963 };
964 };
965
966 uart2c {
967 uart2c_xfer: uart2c-xfer {
968 rockchip,pins =
969 <4 19 RK_FUNC_1 &pcfg_pull_up>,
970 <4 20 RK_FUNC_1 &pcfg_pull_none>;
971 };
972 };
973
974 uart3 {
975 uart3_xfer: uart3-xfer {
976 rockchip,pins =
977 <3 14 RK_FUNC_2 &pcfg_pull_up>,
978 <3 15 RK_FUNC_2 &pcfg_pull_none>;
979 };
980
981 uart3_cts: uart3-cts {
982 rockchip,pins =
983 <3 18 RK_FUNC_2 &pcfg_pull_none>;
984 };
985
986 uart3_rts: uart3-rts {
987 rockchip,pins =
988 <3 19 RK_FUNC_2 &pcfg_pull_none>;
989 };
990 };
991
992 uart4 {
993 uart4_xfer: uart4-xfer {
994 rockchip,pins =
995 <1 7 RK_FUNC_1 &pcfg_pull_up>,
996 <1 8 RK_FUNC_1 &pcfg_pull_none>;
997 };
998 };
999
1000 uarthdcp {
1001 uarthdcp_xfer: uarthdcp-xfer {
1002 rockchip,pins =
1003 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1004 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1005 };
1006 };
1007
1008 pwm0 {
1009 pwm0_pin: pwm0-pin {
1010 rockchip,pins =
1011 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1012 };
1013
1014 vop0_pwm_pin: vop0-pwm-pin {
1015 rockchip,pins =
1016 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1017 };
1018 };
1019
1020 pwm1 {
1021 pwm1_pin: pwm1-pin {
1022 rockchip,pins =
1023 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1024 };
1025
1026 vop1_pwm_pin: vop1-pwm-pin {
1027 rockchip,pins =
1028 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1029 };
1030 };
1031
1032 pwm2 {
1033 pwm2_pin: pwm2-pin {
1034 rockchip,pins =
1035 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1036 };
1037 };
1038
1039 pwm3a {
1040 pwm3a_pin: pwm3a-pin {
1041 rockchip,pins =
1042 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1043 };
1044 };
1045
1046 pwm3b {
1047 pwm3b_pin: pwm3b-pin {
1048 rockchip,pins =
1049 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1050 };
1051 };
1052 };
1053};
Linux kernel - Deliverables
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