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5d1b79d2 MS |
1 | /* |
2 | * dts file for Xilinx ZynqMP | |
3 | * | |
4 | * (C) Copyright 2014 - 2015, Xilinx, Inc. | |
5 | * | |
6 | * Michal Simek <michal.simek@xilinx.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | / { | |
15 | compatible = "xlnx,zynqmp"; | |
16 | #address-cells = <2>; | |
17 | #size-cells = <1>; | |
18 | ||
19 | cpus { | |
20 | #address-cells = <1>; | |
21 | #size-cells = <0>; | |
22 | ||
23 | cpu@0 { | |
24 | compatible = "arm,cortex-a53", "arm,armv8"; | |
25 | device_type = "cpu"; | |
26 | enable-method = "psci"; | |
27 | reg = <0x0>; | |
28 | }; | |
29 | ||
30 | cpu@1 { | |
31 | compatible = "arm,cortex-a53", "arm,armv8"; | |
32 | device_type = "cpu"; | |
33 | enable-method = "psci"; | |
34 | reg = <0x1>; | |
35 | }; | |
36 | ||
37 | cpu@2 { | |
38 | compatible = "arm,cortex-a53", "arm,armv8"; | |
39 | device_type = "cpu"; | |
40 | enable-method = "psci"; | |
41 | reg = <0x2>; | |
42 | }; | |
43 | ||
44 | cpu@3 { | |
45 | compatible = "arm,cortex-a53", "arm,armv8"; | |
46 | device_type = "cpu"; | |
47 | enable-method = "psci"; | |
48 | reg = <0x3>; | |
49 | }; | |
50 | }; | |
51 | ||
52 | pmu { | |
53 | compatible = "arm,armv8-pmuv3"; | |
54 | interrupts = <0 143 4>, | |
55 | <0 144 4>, | |
56 | <0 145 4>, | |
57 | <0 146 4>; | |
58 | }; | |
59 | ||
60 | psci { | |
61 | compatible = "arm,psci-0.2"; | |
62 | method = "smc"; | |
63 | }; | |
64 | ||
65 | timer { | |
66 | compatible = "arm,armv8-timer"; | |
67 | interrupt-parent = <&gic>; | |
585dcaca MZ |
68 | interrupts = <1 13 0xf08>, |
69 | <1 14 0xf08>, | |
70 | <1 11 0xf08>, | |
71 | <1 10 0xf08>; | |
5d1b79d2 MS |
72 | }; |
73 | ||
74 | amba_apu { | |
75 | compatible = "simple-bus"; | |
76 | #address-cells = <2>; | |
77 | #size-cells = <1>; | |
78 | ranges; | |
79 | ||
80 | gic: interrupt-controller@f9010000 { | |
81 | compatible = "arm,gic-400", "arm,cortex-a15-gic"; | |
82 | #interrupt-cells = <3>; | |
83 | reg = <0x0 0xf9010000 0x10000>, | |
84 | <0x0 0xf902f000 0x2000>, | |
85 | <0x0 0xf9040000 0x20000>, | |
86 | <0x0 0xf906f000 0x2000>; | |
87 | interrupt-controller; | |
88 | interrupt-parent = <&gic>; | |
89 | interrupts = <1 9 0xf04>; | |
90 | }; | |
91 | }; | |
92 | ||
5087bccb | 93 | amba: amba { |
5d1b79d2 MS |
94 | compatible = "simple-bus"; |
95 | #address-cells = <2>; | |
96 | #size-cells = <1>; | |
97 | ranges; | |
98 | ||
3a8691f5 MS |
99 | can0: can@ff060000 { |
100 | compatible = "xlnx,zynq-can-1.0"; | |
101 | status = "disabled"; | |
3a8691f5 MS |
102 | clock-names = "can_clk", "pclk"; |
103 | reg = <0x0 0xff060000 0x1000>; | |
104 | interrupts = <0 23 4>; | |
105 | interrupt-parent = <&gic>; | |
106 | tx-fifo-depth = <0x40>; | |
107 | rx-fifo-depth = <0x40>; | |
108 | }; | |
109 | ||
110 | can1: can@ff070000 { | |
111 | compatible = "xlnx,zynq-can-1.0"; | |
112 | status = "disabled"; | |
3a8691f5 MS |
113 | clock-names = "can_clk", "pclk"; |
114 | reg = <0x0 0xff070000 0x1000>; | |
115 | interrupts = <0 24 4>; | |
116 | interrupt-parent = <&gic>; | |
117 | tx-fifo-depth = <0x40>; | |
118 | rx-fifo-depth = <0x40>; | |
119 | }; | |
120 | ||
5d1b79d2 MS |
121 | gem0: ethernet@ff0b0000 { |
122 | compatible = "cdns,gem"; | |
123 | status = "disabled"; | |
124 | interrupt-parent = <&gic>; | |
125 | interrupts = <0 57 4>, <0 57 4>; | |
126 | reg = <0x0 0xff0b0000 0x1000>; | |
127 | clock-names = "pclk", "hclk", "tx_clk"; | |
5d1b79d2 MS |
128 | #address-cells = <1>; |
129 | #size-cells = <0>; | |
130 | }; | |
131 | ||
132 | gem1: ethernet@ff0c0000 { | |
133 | compatible = "cdns,gem"; | |
134 | status = "disabled"; | |
135 | interrupt-parent = <&gic>; | |
136 | interrupts = <0 59 4>, <0 59 4>; | |
137 | reg = <0x0 0xff0c0000 0x1000>; | |
138 | clock-names = "pclk", "hclk", "tx_clk"; | |
5d1b79d2 MS |
139 | #address-cells = <1>; |
140 | #size-cells = <0>; | |
141 | }; | |
142 | ||
143 | gem2: ethernet@ff0d0000 { | |
144 | compatible = "cdns,gem"; | |
145 | status = "disabled"; | |
146 | interrupt-parent = <&gic>; | |
147 | interrupts = <0 61 4>, <0 61 4>; | |
148 | reg = <0x0 0xff0d0000 0x1000>; | |
149 | clock-names = "pclk", "hclk", "tx_clk"; | |
5d1b79d2 MS |
150 | #address-cells = <1>; |
151 | #size-cells = <0>; | |
152 | }; | |
153 | ||
154 | gem3: ethernet@ff0e0000 { | |
155 | compatible = "cdns,gem"; | |
156 | status = "disabled"; | |
157 | interrupt-parent = <&gic>; | |
158 | interrupts = <0 63 4>, <0 63 4>; | |
159 | reg = <0x0 0xff0e0000 0x1000>; | |
160 | clock-names = "pclk", "hclk", "tx_clk"; | |
5d1b79d2 MS |
161 | #address-cells = <1>; |
162 | #size-cells = <0>; | |
163 | }; | |
164 | ||
72e5df43 MS |
165 | gpio: gpio@ff0a0000 { |
166 | compatible = "xlnx,zynqmp-gpio-1.0"; | |
167 | status = "disabled"; | |
168 | #gpio-cells = <0x2>; | |
72e5df43 MS |
169 | interrupt-parent = <&gic>; |
170 | interrupts = <0 16 4>; | |
171 | interrupt-controller; | |
172 | #interrupt-cells = <2>; | |
173 | reg = <0x0 0xff0a0000 0x1000>; | |
174 | }; | |
175 | ||
5d1b79d2 MS |
176 | i2c0: i2c@ff020000 { |
177 | compatible = "cdns,i2c-r1p10"; | |
178 | status = "disabled"; | |
179 | interrupt-parent = <&gic>; | |
180 | interrupts = <0 17 4>; | |
181 | reg = <0x0 0xff020000 0x1000>; | |
5d1b79d2 MS |
182 | #address-cells = <1>; |
183 | #size-cells = <0>; | |
184 | }; | |
185 | ||
186 | i2c1: i2c@ff030000 { | |
187 | compatible = "cdns,i2c-r1p10"; | |
188 | status = "disabled"; | |
189 | interrupt-parent = <&gic>; | |
190 | interrupts = <0 18 4>; | |
191 | reg = <0x0 0xff030000 0x1000>; | |
5d1b79d2 MS |
192 | #address-cells = <1>; |
193 | #size-cells = <0>; | |
194 | }; | |
195 | ||
8fae442f SG |
196 | sata: ahci@fd0c0000 { |
197 | compatible = "ceva,ahci-1v84"; | |
198 | status = "disabled"; | |
199 | reg = <0x0 0xfd0c0000 0x2000>; | |
200 | interrupt-parent = <&gic>; | |
201 | interrupts = <0 133 4>; | |
8fae442f SG |
202 | }; |
203 | ||
5d1b79d2 MS |
204 | sdhci0: sdhci@ff160000 { |
205 | compatible = "arasan,sdhci-8.9a"; | |
206 | status = "disabled"; | |
207 | interrupt-parent = <&gic>; | |
208 | interrupts = <0 48 4>; | |
209 | reg = <0x0 0xff160000 0x1000>; | |
210 | clock-names = "clk_xin", "clk_ahb"; | |
5d1b79d2 MS |
211 | }; |
212 | ||
213 | sdhci1: sdhci@ff170000 { | |
214 | compatible = "arasan,sdhci-8.9a"; | |
215 | status = "disabled"; | |
216 | interrupt-parent = <&gic>; | |
217 | interrupts = <0 49 4>; | |
218 | reg = <0x0 0xff170000 0x1000>; | |
219 | clock-names = "clk_xin", "clk_ahb"; | |
5d1b79d2 MS |
220 | }; |
221 | ||
ff92e361 MS |
222 | smmu: smmu@fd800000 { |
223 | compatible = "arm,mmu-500"; | |
224 | reg = <0x0 0xfd800000 0x20000>; | |
225 | #global-interrupts = <1>; | |
226 | interrupt-parent = <&gic>; | |
227 | interrupts = <0 157 4>, | |
228 | <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, | |
229 | <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, | |
230 | <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, | |
231 | <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>; | |
232 | }; | |
233 | ||
f49310dc MS |
234 | spi0: spi@ff040000 { |
235 | compatible = "cdns,spi-r1p6"; | |
236 | status = "disabled"; | |
237 | interrupt-parent = <&gic>; | |
238 | interrupts = <0 19 4>; | |
239 | reg = <0x0 0xff040000 0x1000>; | |
240 | clock-names = "ref_clk", "pclk"; | |
f49310dc MS |
241 | #address-cells = <1>; |
242 | #size-cells = <0>; | |
243 | }; | |
244 | ||
245 | spi1: spi@ff050000 { | |
246 | compatible = "cdns,spi-r1p6"; | |
247 | status = "disabled"; | |
248 | interrupt-parent = <&gic>; | |
249 | interrupts = <0 20 4>; | |
250 | reg = <0x0 0xff050000 0x1000>; | |
251 | clock-names = "ref_clk", "pclk"; | |
f49310dc MS |
252 | #address-cells = <1>; |
253 | #size-cells = <0>; | |
254 | }; | |
255 | ||
8fd7a775 MS |
256 | ttc0: timer@ff110000 { |
257 | compatible = "cdns,ttc"; | |
258 | status = "disabled"; | |
259 | interrupt-parent = <&gic>; | |
260 | interrupts = <0 36 4>, <0 37 4>, <0 38 4>; | |
261 | reg = <0x0 0xff110000 0x1000>; | |
8fd7a775 MS |
262 | timer-width = <32>; |
263 | }; | |
264 | ||
265 | ttc1: timer@ff120000 { | |
266 | compatible = "cdns,ttc"; | |
267 | status = "disabled"; | |
268 | interrupt-parent = <&gic>; | |
269 | interrupts = <0 39 4>, <0 40 4>, <0 41 4>; | |
270 | reg = <0x0 0xff120000 0x1000>; | |
8fd7a775 MS |
271 | timer-width = <32>; |
272 | }; | |
273 | ||
274 | ttc2: timer@ff130000 { | |
275 | compatible = "cdns,ttc"; | |
276 | status = "disabled"; | |
277 | interrupt-parent = <&gic>; | |
278 | interrupts = <0 42 4>, <0 43 4>, <0 44 4>; | |
279 | reg = <0x0 0xff130000 0x1000>; | |
8fd7a775 MS |
280 | timer-width = <32>; |
281 | }; | |
282 | ||
283 | ttc3: timer@ff140000 { | |
284 | compatible = "cdns,ttc"; | |
285 | status = "disabled"; | |
286 | interrupt-parent = <&gic>; | |
287 | interrupts = <0 45 4>, <0 46 4>, <0 47 4>; | |
288 | reg = <0x0 0xff140000 0x1000>; | |
8fd7a775 MS |
289 | timer-width = <32>; |
290 | }; | |
291 | ||
292 | uart0: serial@ff000000 { | |
293 | compatible = "cdns,uart-r1p8"; | |
294 | status = "disabled"; | |
295 | interrupt-parent = <&gic>; | |
296 | interrupts = <0 21 4>; | |
297 | reg = <0x0 0xff000000 0x1000>; | |
298 | clock-names = "uart_clk", "pclk"; | |
8fd7a775 MS |
299 | }; |
300 | ||
301 | uart1: serial@ff010000 { | |
302 | compatible = "cdns,uart-r1p8"; | |
303 | status = "disabled"; | |
304 | interrupt-parent = <&gic>; | |
305 | interrupts = <0 22 4>; | |
306 | reg = <0x0 0xff010000 0x1000>; | |
307 | clock-names = "uart_clk", "pclk"; | |
8fd7a775 MS |
308 | }; |
309 | ||
22eda14a MS |
310 | usb0: usb@fe200000 { |
311 | compatible = "snps,dwc3"; | |
312 | status = "disabled"; | |
313 | interrupt-parent = <&gic>; | |
314 | interrupts = <0 65 4>; | |
315 | reg = <0x0 0xfe200000 0x40000>; | |
316 | clock-names = "clk_xin", "clk_ahb"; | |
22eda14a MS |
317 | }; |
318 | ||
319 | usb1: usb@fe300000 { | |
320 | compatible = "snps,dwc3"; | |
321 | status = "disabled"; | |
322 | interrupt-parent = <&gic>; | |
323 | interrupts = <0 70 4>; | |
324 | reg = <0x0 0xfe300000 0x40000>; | |
325 | clock-names = "clk_xin", "clk_ahb"; | |
22eda14a MS |
326 | }; |
327 | ||
5d1b79d2 MS |
328 | watchdog0: watchdog@fd4d0000 { |
329 | compatible = "cdns,wdt-r1p2"; | |
330 | status = "disabled"; | |
5d1b79d2 MS |
331 | interrupt-parent = <&gic>; |
332 | interrupts = <0 52 1>; | |
333 | reg = <0x0 0xfd4d0000 0x1000>; | |
334 | timeout-sec = <10>; | |
335 | }; | |
336 | }; | |
337 | }; |