projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f1a0c4aa CM |
1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License version 2 as | |
| 6 | * published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope that it will be useful, | |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 11 | * GNU General Public License for more details. | |
| 12 | * | |
| 13 | * You should have received a copy of the GNU General Public License | |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
| 15 | */ | |
| 16 | #ifndef __ASM_CACHETYPE_H | |
| 17 | #define __ASM_CACHETYPE_H | |
| 18 | ||
| 19 | #include <asm/cputype.h> | |
| 20 | ||
| 21 | #define CTR_L1IP_SHIFT 14 | |
| 22 | #define CTR_L1IP_MASK 3 | |
| a41dc0e8 CM |
23 | #define CTR_CWG_SHIFT 24 |
| 24 | #define CTR_CWG_MASK 15 | |
| f1a0c4aa CM |
25 | |
| 26 | #define ICACHE_POLICY_RESERVED 0 | |
| 27 | #define ICACHE_POLICY_AIVIVT 1 | |
| 28 | #define ICACHE_POLICY_VIPT 2 | |
| 29 | #define ICACHE_POLICY_PIPT 3 | |
| 30 | ||
| a41dc0e8 CM |
31 | #ifndef __ASSEMBLY__ |
| 32 | ||
| 59ccc0d4 MR |
33 | #include <linux/bitops.h> |
| 34 | ||
| 35 | #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) | |
| 36 | ||
| 37 | #define ICACHEF_ALIASING BIT(0) | |
| 38 | #define ICACHEF_AIVIVT BIT(1) | |
| 39 | ||
| 40 | extern unsigned long __icache_flags; | |
| f1a0c4aa | 41 | |
| 80c517b0 AB |
42 | #define CCSIDR_EL1_LINESIZE_MASK 0x7 |
| 43 | #define CCSIDR_EL1_LINESIZE(x) ((x) & CCSIDR_EL1_LINESIZE_MASK) | |
| 44 | ||
| 45 | #define CCSIDR_EL1_NUMSETS_SHIFT 13 | |
| 46 | #define CCSIDR_EL1_NUMSETS_MASK (0x7fff << CCSIDR_EL1_NUMSETS_SHIFT) | |
| 47 | #define CCSIDR_EL1_NUMSETS(x) \ | |
| 48 | (((x) & CCSIDR_EL1_NUMSETS_MASK) >> CCSIDR_EL1_NUMSETS_SHIFT) | |
| 49 | ||
| 50 | extern u64 __attribute_const__ icache_get_ccsidr(void); | |
| 51 | ||
| 52 | static inline int icache_get_linesize(void) | |
| 53 | { | |
| 54 | return 16 << CCSIDR_EL1_LINESIZE(icache_get_ccsidr()); | |
| 55 | } | |
| 56 | ||
| 57 | static inline int icache_get_numsets(void) | |
| 58 | { | |
| 59 | return 1 + CCSIDR_EL1_NUMSETS(icache_get_ccsidr()); | |
| 60 | } | |
| 61 | ||
| f1a0c4aa CM |
62 | /* |
| 63 | * Whilst the D-side always behaves as PIPT on AArch64, aliasing is | |
| 64 | * permitted in the I-cache. | |
| 65 | */ | |
| 66 | static inline int icache_is_aliasing(void) | |
| 67 | { | |
| 59ccc0d4 | 68 | return test_bit(ICACHEF_ALIASING, &__icache_flags); |
| f1a0c4aa CM |
69 | } |
| 70 | ||
| 71 | static inline int icache_is_aivivt(void) | |
| 72 | { | |
| 59ccc0d4 | 73 | return test_bit(ICACHEF_AIVIVT, &__icache_flags); |
| f1a0c4aa CM |
74 | } |
| 75 | ||
| a41dc0e8 CM |
76 | static inline u32 cache_type_cwg(void) |
| 77 | { | |
| 78 | return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; | |
| 79 | } | |
| 80 | ||
| 81 | #endif /* __ASSEMBLY__ */ | |
| 82 | ||
| f1a0c4aa | 83 | #endif /* __ASM_CACHETYPE_H */ |