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3be1a5c4 AB |
1 | /* |
2 | * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef __ASM_CPUFEATURE_H | |
10 | #define __ASM_CPUFEATURE_H | |
11 | ||
efd9e03f CM |
12 | #include <linux/jump_label.h> |
13 | ||
3be1a5c4 | 14 | #include <asm/hwcap.h> |
cdcf817b | 15 | #include <asm/sysreg.h> |
3be1a5c4 AB |
16 | |
17 | /* | |
18 | * In the arm64 world (as in the ARM world), elf_hwcap is used both internally | |
19 | * in the kernel and for user space to keep track of which optional features | |
20 | * are supported by the current system. So let's map feature 'x' to HWCAP_x. | |
21 | * Note that HWCAP_x constants are bit fields so we need to take the log. | |
22 | */ | |
23 | ||
24 | #define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap)) | |
25 | #define cpu_feature(x) ilog2(HWCAP_ ## x) | |
26 | ||
5afaa1fc AP |
27 | #define ARM64_WORKAROUND_CLEAN_CACHE 0 |
28 | #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 | |
905e8c5d | 29 | #define ARM64_WORKAROUND_845719 2 |
94a9e04a | 30 | #define ARM64_HAS_SYSREG_GIC_CPUIF 3 |
338d4f49 | 31 | #define ARM64_HAS_PAN 4 |
c739dc83 | 32 | #define ARM64_HAS_LSE_ATOMICS 5 |
6d4e11c5 | 33 | #define ARM64_WORKAROUND_CAVIUM_23154 6 |
498cd5c3 | 34 | #define ARM64_WORKAROUND_834220 7 |
d5370f75 | 35 | #define ARM64_HAS_NO_HW_PREFETCH 8 |
57f4959b | 36 | #define ARM64_HAS_UAO 9 |
70544196 | 37 | #define ARM64_ALT_PAN_NOT_UAO 10 |
d88701be | 38 | #define ARM64_HAS_VIRT_HOST_EXTN 11 |
104a0c02 | 39 | #define ARM64_WORKAROUND_CAVIUM_27456 12 |
042446a3 | 40 | #define ARM64_HAS_32BIT_EL0 13 |
853c3b21 | 41 | #define ARM64_HYP_OFFSET_LOW 14 |
116c81f4 | 42 | #define ARM64_MISMATCHED_CACHE_LINE_SIZE 15 |
301bcfac | 43 | |
116c81f4 | 44 | #define ARM64_NCAPS 16 |
301bcfac AP |
45 | |
46 | #ifndef __ASSEMBLY__ | |
930da09f | 47 | |
144e9697 WD |
48 | #include <linux/kernel.h> |
49 | ||
3c739b57 SP |
50 | /* CPU feature register tracking */ |
51 | enum ftr_type { | |
52 | FTR_EXACT, /* Use a predefined safe value */ | |
53 | FTR_LOWER_SAFE, /* Smaller value is safe */ | |
54 | FTR_HIGHER_SAFE,/* Bigger value is safe */ | |
55 | }; | |
56 | ||
57 | #define FTR_STRICT true /* SANITY check strict matching required */ | |
58 | #define FTR_NONSTRICT false /* SANITY check ignored */ | |
59 | ||
4f0a606b SP |
60 | #define FTR_SIGNED true /* Value should be treated as signed */ |
61 | #define FTR_UNSIGNED false /* Value should be treated as unsigned */ | |
62 | ||
3c739b57 | 63 | struct arm64_ftr_bits { |
4f0a606b SP |
64 | bool sign; /* Value is signed ? */ |
65 | bool strict; /* CPU Sanity check: strict matching required ? */ | |
3c739b57 SP |
66 | enum ftr_type type; |
67 | u8 shift; | |
68 | u8 width; | |
ee7bc638 | 69 | s64 safe_val; /* safe value for FTR_EXACT features */ |
3c739b57 SP |
70 | }; |
71 | ||
72 | /* | |
73 | * @arm64_ftr_reg - Feature register | |
74 | * @strict_mask Bits which should match across all CPUs for sanity. | |
75 | * @sys_val Safe value across the CPUs (system view) | |
76 | */ | |
77 | struct arm64_ftr_reg { | |
5e49d73c AB |
78 | const char *name; |
79 | u64 strict_mask; | |
80 | u64 sys_val; | |
81 | const struct arm64_ftr_bits *ftr_bits; | |
3c739b57 SP |
82 | }; |
83 | ||
675b0563 AB |
84 | extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; |
85 | ||
92406f0c SP |
86 | /* scope of capability check */ |
87 | enum { | |
88 | SCOPE_SYSTEM, | |
89 | SCOPE_LOCAL_CPU, | |
90 | }; | |
91 | ||
359b7064 MZ |
92 | struct arm64_cpu_capabilities { |
93 | const char *desc; | |
94 | u16 capability; | |
92406f0c SP |
95 | int def_scope; /* default scope */ |
96 | bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope); | |
dbb4e152 | 97 | void (*enable)(void *); /* Called on all active CPUs */ |
359b7064 MZ |
98 | union { |
99 | struct { /* To be used for erratum handling only */ | |
100 | u32 midr_model; | |
101 | u32 midr_range_min, midr_range_max; | |
102 | }; | |
94a9e04a MZ |
103 | |
104 | struct { /* Feature register checking */ | |
da8d02d1 | 105 | u32 sys_reg; |
ff96f7bc SP |
106 | u8 field_pos; |
107 | u8 min_field_value; | |
108 | u8 hwcap_type; | |
109 | bool sign; | |
37b01d53 | 110 | unsigned long hwcap; |
94a9e04a | 111 | }; |
359b7064 MZ |
112 | }; |
113 | }; | |
114 | ||
06f9eb88 | 115 | extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); |
efd9e03f | 116 | extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS]; |
930da09f | 117 | |
e3661b12 MZ |
118 | bool this_cpu_has_cap(unsigned int cap); |
119 | ||
3be1a5c4 AB |
120 | static inline bool cpu_have_feature(unsigned int num) |
121 | { | |
122 | return elf_hwcap & (1UL << num); | |
123 | } | |
124 | ||
930da09f AP |
125 | static inline bool cpus_have_cap(unsigned int num) |
126 | { | |
06f9eb88 | 127 | if (num >= ARM64_NCAPS) |
930da09f | 128 | return false; |
efd9e03f CM |
129 | if (__builtin_constant_p(num)) |
130 | return static_branch_unlikely(&cpu_hwcap_keys[num]); | |
131 | else | |
132 | return test_bit(num, cpu_hwcaps); | |
930da09f AP |
133 | } |
134 | ||
135 | static inline void cpus_set_cap(unsigned int num) | |
136 | { | |
efd9e03f | 137 | if (num >= ARM64_NCAPS) { |
930da09f | 138 | pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n", |
06f9eb88 | 139 | num, ARM64_NCAPS); |
efd9e03f | 140 | } else { |
930da09f | 141 | __set_bit(num, cpu_hwcaps); |
efd9e03f CM |
142 | static_branch_enable(&cpu_hwcap_keys[num]); |
143 | } | |
930da09f AP |
144 | } |
145 | ||
ce98a677 | 146 | static inline int __attribute_const__ |
28c5dcb2 | 147 | cpuid_feature_extract_signed_field_width(u64 features, int field, int width) |
79b0e09a | 148 | { |
ce98a677 SP |
149 | return (s64)(features << (64 - width - field)) >> (64 - width); |
150 | } | |
151 | ||
152 | static inline int __attribute_const__ | |
28c5dcb2 | 153 | cpuid_feature_extract_signed_field(u64 features, int field) |
ce98a677 | 154 | { |
28c5dcb2 | 155 | return cpuid_feature_extract_signed_field_width(features, field, 4); |
79b0e09a JM |
156 | } |
157 | ||
d2118271 SP |
158 | static inline unsigned int __attribute_const__ |
159 | cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width) | |
160 | { | |
161 | return (u64)(features << (64 - width - field)) >> (64 - width); | |
162 | } | |
163 | ||
164 | static inline unsigned int __attribute_const__ | |
165 | cpuid_feature_extract_unsigned_field(u64 features, int field) | |
166 | { | |
167 | return cpuid_feature_extract_unsigned_field_width(features, field, 4); | |
168 | } | |
169 | ||
5e49d73c | 170 | static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp) |
3c739b57 SP |
171 | { |
172 | return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift); | |
173 | } | |
174 | ||
28c5dcb2 SP |
175 | static inline int __attribute_const__ |
176 | cpuid_feature_extract_field(u64 features, int field, bool sign) | |
177 | { | |
178 | return (sign) ? | |
179 | cpuid_feature_extract_signed_field(features, field) : | |
180 | cpuid_feature_extract_unsigned_field(features, field); | |
181 | } | |
182 | ||
5e49d73c | 183 | static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val) |
3c739b57 | 184 | { |
28c5dcb2 | 185 | return (s64)cpuid_feature_extract_field(val, ftrp->shift, ftrp->sign); |
3c739b57 SP |
186 | } |
187 | ||
cdcf817b | 188 | static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0) |
79b0e09a | 189 | { |
28c5dcb2 SP |
190 | return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 || |
191 | cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1; | |
79b0e09a JM |
192 | } |
193 | ||
c80aba80 SP |
194 | static inline bool id_aa64pfr0_32bit_el0(u64 pfr0) |
195 | { | |
196 | u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT); | |
197 | ||
198 | return val == ID_AA64PFR0_EL0_32BIT_64BIT; | |
199 | } | |
200 | ||
3a75578e | 201 | void __init setup_cpu_features(void); |
79b0e09a | 202 | |
ce8b602c | 203 | void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, |
359b7064 | 204 | const char *info); |
8e231852 | 205 | void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps); |
c47a1900 SP |
206 | void check_local_cpu_capabilities(void); |
207 | ||
89ba2645 | 208 | void update_cpu_errata_workarounds(void); |
8e231852 | 209 | void __init enable_errata_workarounds(void); |
89ba2645 | 210 | void verify_local_cpu_errata_workarounds(void); |
e116a375 | 211 | |
b3f15378 SP |
212 | u64 read_system_reg(u32 id); |
213 | ||
c1e8656c SP |
214 | static inline bool cpu_supports_mixed_endian_el0(void) |
215 | { | |
216 | return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); | |
217 | } | |
218 | ||
042446a3 SP |
219 | static inline bool system_supports_32bit_el0(void) |
220 | { | |
221 | return cpus_have_cap(ARM64_HAS_32BIT_EL0); | |
222 | } | |
223 | ||
c1e8656c SP |
224 | static inline bool system_supports_mixed_endian_el0(void) |
225 | { | |
226 | return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1)); | |
227 | } | |
e116a375 | 228 | |
301bcfac AP |
229 | #endif /* __ASSEMBLY__ */ |
230 | ||
3be1a5c4 | 231 | #endif |