jump_labels: Allow array initialisers
[deliverable/linux.git] / arch / arm64 / include / asm / cpufeature.h
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1/*
2 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_CPUFEATURE_H
10#define __ASM_CPUFEATURE_H
11
12#include <asm/hwcap.h>
cdcf817b 13#include <asm/sysreg.h>
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14
15/*
16 * In the arm64 world (as in the ARM world), elf_hwcap is used both internally
17 * in the kernel and for user space to keep track of which optional features
18 * are supported by the current system. So let's map feature 'x' to HWCAP_x.
19 * Note that HWCAP_x constants are bit fields so we need to take the log.
20 */
21
22#define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap))
23#define cpu_feature(x) ilog2(HWCAP_ ## x)
24
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25#define ARM64_WORKAROUND_CLEAN_CACHE 0
26#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1
905e8c5d 27#define ARM64_WORKAROUND_845719 2
94a9e04a 28#define ARM64_HAS_SYSREG_GIC_CPUIF 3
338d4f49 29#define ARM64_HAS_PAN 4
c739dc83 30#define ARM64_HAS_LSE_ATOMICS 5
6d4e11c5 31#define ARM64_WORKAROUND_CAVIUM_23154 6
498cd5c3 32#define ARM64_WORKAROUND_834220 7
d5370f75 33#define ARM64_HAS_NO_HW_PREFETCH 8
57f4959b 34#define ARM64_HAS_UAO 9
70544196 35#define ARM64_ALT_PAN_NOT_UAO 10
d88701be 36#define ARM64_HAS_VIRT_HOST_EXTN 11
104a0c02 37#define ARM64_WORKAROUND_CAVIUM_27456 12
042446a3 38#define ARM64_HAS_32BIT_EL0 13
853c3b21 39#define ARM64_HYP_OFFSET_LOW 14
301bcfac 40
853c3b21 41#define ARM64_NCAPS 15
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42
43#ifndef __ASSEMBLY__
930da09f 44
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45#include <linux/kernel.h>
46
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47/* CPU feature register tracking */
48enum ftr_type {
49 FTR_EXACT, /* Use a predefined safe value */
50 FTR_LOWER_SAFE, /* Smaller value is safe */
51 FTR_HIGHER_SAFE,/* Bigger value is safe */
52};
53
54#define FTR_STRICT true /* SANITY check strict matching required */
55#define FTR_NONSTRICT false /* SANITY check ignored */
56
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57#define FTR_SIGNED true /* Value should be treated as signed */
58#define FTR_UNSIGNED false /* Value should be treated as unsigned */
59
3c739b57 60struct arm64_ftr_bits {
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61 bool sign; /* Value is signed ? */
62 bool strict; /* CPU Sanity check: strict matching required ? */
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63 enum ftr_type type;
64 u8 shift;
65 u8 width;
66 s64 safe_val; /* safe value for discrete features */
67};
68
69/*
70 * @arm64_ftr_reg - Feature register
71 * @strict_mask Bits which should match across all CPUs for sanity.
72 * @sys_val Safe value across the CPUs (system view)
73 */
74struct arm64_ftr_reg {
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75 const char *name;
76 u64 strict_mask;
77 u64 sys_val;
78 const struct arm64_ftr_bits *ftr_bits;
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79};
80
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81extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
82
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83/* scope of capability check */
84enum {
85 SCOPE_SYSTEM,
86 SCOPE_LOCAL_CPU,
87};
88
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89struct arm64_cpu_capabilities {
90 const char *desc;
91 u16 capability;
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92 int def_scope; /* default scope */
93 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
dbb4e152 94 void (*enable)(void *); /* Called on all active CPUs */
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95 union {
96 struct { /* To be used for erratum handling only */
97 u32 midr_model;
98 u32 midr_range_min, midr_range_max;
99 };
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100
101 struct { /* Feature register checking */
da8d02d1 102 u32 sys_reg;
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103 u8 field_pos;
104 u8 min_field_value;
105 u8 hwcap_type;
106 bool sign;
37b01d53 107 unsigned long hwcap;
94a9e04a 108 };
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109 };
110};
111
06f9eb88 112extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
930da09f 113
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114bool this_cpu_has_cap(unsigned int cap);
115
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116static inline bool cpu_have_feature(unsigned int num)
117{
118 return elf_hwcap & (1UL << num);
119}
120
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121static inline bool cpus_have_cap(unsigned int num)
122{
06f9eb88 123 if (num >= ARM64_NCAPS)
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124 return false;
125 return test_bit(num, cpu_hwcaps);
126}
127
128static inline void cpus_set_cap(unsigned int num)
129{
06f9eb88 130 if (num >= ARM64_NCAPS)
930da09f 131 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
06f9eb88 132 num, ARM64_NCAPS);
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133 else
134 __set_bit(num, cpu_hwcaps);
135}
136
ce98a677 137static inline int __attribute_const__
28c5dcb2 138cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
79b0e09a 139{
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140 return (s64)(features << (64 - width - field)) >> (64 - width);
141}
142
143static inline int __attribute_const__
28c5dcb2 144cpuid_feature_extract_signed_field(u64 features, int field)
ce98a677 145{
28c5dcb2 146 return cpuid_feature_extract_signed_field_width(features, field, 4);
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147}
148
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149static inline unsigned int __attribute_const__
150cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
151{
152 return (u64)(features << (64 - width - field)) >> (64 - width);
153}
154
155static inline unsigned int __attribute_const__
156cpuid_feature_extract_unsigned_field(u64 features, int field)
157{
158 return cpuid_feature_extract_unsigned_field_width(features, field, 4);
159}
160
5e49d73c 161static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
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162{
163 return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
164}
165
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166static inline int __attribute_const__
167cpuid_feature_extract_field(u64 features, int field, bool sign)
168{
169 return (sign) ?
170 cpuid_feature_extract_signed_field(features, field) :
171 cpuid_feature_extract_unsigned_field(features, field);
172}
173
5e49d73c 174static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
3c739b57 175{
28c5dcb2 176 return (s64)cpuid_feature_extract_field(val, ftrp->shift, ftrp->sign);
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177}
178
cdcf817b 179static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
79b0e09a 180{
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181 return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
182 cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
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183}
184
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185static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
186{
187 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
188
189 return val == ID_AA64PFR0_EL0_32BIT_64BIT;
190}
191
3a75578e 192void __init setup_cpu_features(void);
79b0e09a 193
ce8b602c 194void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
359b7064 195 const char *info);
8e231852 196void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps);
e116a375 197void check_local_cpu_errata(void);
8e231852 198void __init enable_errata_workarounds(void);
dbb4e152 199
6a6efbb4 200void verify_local_cpu_errata(void);
dbb4e152 201void verify_local_cpu_capabilities(void);
e116a375 202
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203u64 read_system_reg(u32 id);
204
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205static inline bool cpu_supports_mixed_endian_el0(void)
206{
207 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
208}
209
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210static inline bool system_supports_32bit_el0(void)
211{
212 return cpus_have_cap(ARM64_HAS_32BIT_EL0);
213}
214
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215static inline bool system_supports_mixed_endian_el0(void)
216{
217 return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
218}
e116a375 219
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220#endif /* __ASSEMBLY__ */
221
3be1a5c4 222#endif
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