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478fcb2c WD |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_DEBUG_MONITORS_H | |
17 | #define __ASM_DEBUG_MONITORS_H | |
18 | ||
19 | #ifdef __KERNEL__ | |
20 | ||
d7a33f4f DM |
21 | #include <linux/errno.h> |
22 | #include <linux/types.h> | |
03336b1d | 23 | #include <asm/bug.h> |
03923696 | 24 | #include <asm/esr.h> |
951757ae | 25 | #include <asm/insn.h> |
d7a33f4f | 26 | #include <asm/ptrace.h> |
951757ae | 27 | |
51ba2481 MZ |
28 | /* Low-level stepping controls. */ |
29 | #define DBG_MDSCR_SS (1 << 0) | |
30 | #define DBG_SPSR_SS (1 << 21) | |
31 | ||
32 | /* MDSCR_EL1 enabling bits */ | |
33 | #define DBG_MDSCR_KDE (1 << 13) | |
34 | #define DBG_MDSCR_MDE (1 << 15) | |
35 | #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) | |
36 | ||
478fcb2c WD |
37 | #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7) |
38 | ||
39 | /* AArch64 */ | |
40 | #define DBG_ESR_EVT_HWBP 0x0 | |
41 | #define DBG_ESR_EVT_HWSS 0x1 | |
42 | #define DBG_ESR_EVT_HWWP 0x2 | |
43 | #define DBG_ESR_EVT_BRK 0x6 | |
44 | ||
bcf5763b VK |
45 | /* |
46 | * Break point instruction encoding | |
47 | */ | |
951757ae | 48 | #define BREAK_INSTR_SIZE AARCH64_INSN_SIZE |
bcf5763b | 49 | |
bcf5763b VK |
50 | /* |
51 | * #imm16 values used for BRK instruction generation | |
52 | * Allowed values for kgbd are 0x400 - 0x7ff | |
a9ae04c9 | 53 | * 0x100: for triggering a fault on purpose (reserved) |
bcf5763b VK |
54 | * 0x400: for dynamic BRK instruction |
55 | * 0x401: for compile time BRK instruction | |
9fb7410f | 56 | * 0x800: kernel-mode BUG() and WARN() traps |
bcf5763b | 57 | */ |
a9ae04c9 | 58 | #define FAULT_BRK_IMM 0x100 |
7acf71d1 CM |
59 | #define KGDB_DYN_DBG_BRK_IMM 0x400 |
60 | #define KGDB_COMPILED_DBG_BRK_IMM 0x401 | |
bcf5763b VK |
61 | |
62 | /* | |
63 | * BRK instruction encoding | |
64 | * The #imm16 value should be placed at bits[20:5] within BRK ins | |
65 | */ | |
66 | #define AARCH64_BREAK_MON 0xd4200000 | |
67 | ||
a9ae04c9 MB |
68 | /* |
69 | * BRK instruction for provoking a fault on purpose | |
70 | * Unlike kgdb, #imm16 value with unallocated handler is used for faulting. | |
71 | */ | |
72 | #define AARCH64_BREAK_FAULT (AARCH64_BREAK_MON | (FAULT_BRK_IMM << 5)) | |
73 | ||
c696b934 DM |
74 | #define AARCH64_BREAK_KGDB_DYN_DBG \ |
75 | (AARCH64_BREAK_MON | (KGDB_DYN_DBG_BRK_IMM << 5)) | |
76 | #define KGDB_DYN_BRK_INS_BYTE(x) \ | |
77 | ((AARCH64_BREAK_KGDB_DYN_DBG >> (8 * (x))) & 0xff) | |
bcf5763b VK |
78 | |
79 | #define CACHE_FLUSH_IS_SAFE 1 | |
80 | ||
478fcb2c WD |
81 | /* AArch32 */ |
82 | #define DBG_ESR_EVT_BKPT 0x4 | |
83 | #define DBG_ESR_EVT_VECC 0x5 | |
84 | ||
85 | #define AARCH32_BREAK_ARM 0x07f001f0 | |
86 | #define AARCH32_BREAK_THUMB 0xde01 | |
87 | #define AARCH32_BREAK_THUMB2_LO 0xf7f0 | |
88 | #define AARCH32_BREAK_THUMB2_HI 0xa000 | |
89 | ||
90 | #ifndef __ASSEMBLY__ | |
91 | struct task_struct; | |
92 | ||
478fcb2c WD |
93 | #define DBG_ARCH_ID_RESERVED 0 /* In case of ptrace ABI updates. */ |
94 | ||
ee6214ce SP |
95 | #define DBG_HOOK_HANDLED 0 |
96 | #define DBG_HOOK_ERROR 1 | |
97 | ||
98 | struct step_hook { | |
99 | struct list_head node; | |
100 | int (*fn)(struct pt_regs *regs, unsigned int esr); | |
101 | }; | |
102 | ||
103 | void register_step_hook(struct step_hook *hook); | |
104 | void unregister_step_hook(struct step_hook *hook); | |
105 | ||
106 | struct break_hook { | |
107 | struct list_head node; | |
108 | u32 esr_val; | |
109 | u32 esr_mask; | |
110 | int (*fn)(struct pt_regs *regs, unsigned int esr); | |
111 | }; | |
112 | ||
113 | void register_break_hook(struct break_hook *hook); | |
114 | void unregister_break_hook(struct break_hook *hook); | |
115 | ||
478fcb2c WD |
116 | u8 debug_monitors_arch(void); |
117 | ||
6f883d10 | 118 | enum dbg_active_el { |
51ba2481 MZ |
119 | DBG_ACTIVE_EL0 = 0, |
120 | DBG_ACTIVE_EL1, | |
121 | }; | |
122 | ||
6f883d10 WD |
123 | void enable_debug_monitors(enum dbg_active_el el); |
124 | void disable_debug_monitors(enum dbg_active_el el); | |
478fcb2c WD |
125 | |
126 | void user_rewind_single_step(struct task_struct *task); | |
127 | void user_fastforward_single_step(struct task_struct *task); | |
128 | ||
129 | void kernel_enable_single_step(struct pt_regs *regs); | |
130 | void kernel_disable_single_step(void); | |
131 | int kernel_active_single_step(void); | |
132 | ||
133 | #ifdef CONFIG_HAVE_HW_BREAKPOINT | |
134 | int reinstall_suspended_bps(struct pt_regs *regs); | |
135 | #else | |
136 | static inline int reinstall_suspended_bps(struct pt_regs *regs) | |
137 | { | |
138 | return -ENODEV; | |
139 | } | |
140 | #endif | |
141 | ||
1442b6ed | 142 | int aarch32_break_handler(struct pt_regs *regs); |
1442b6ed | 143 | |
478fcb2c WD |
144 | #endif /* __ASSEMBLY */ |
145 | #endif /* __KERNEL__ */ | |
146 | #endif /* __ASM_DEBUG_MONITORS_H */ |