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1 | /* |
2 | * Copyright (C) 2012,2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __ARM_KVM_ASM_H__ | |
19 | #define __ARM_KVM_ASM_H__ | |
20 | ||
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21 | #include <asm/virt.h> |
22 | ||
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23 | /* |
24 | * 0 is reserved as an invalid value. | |
25 | * Order *must* be kept in sync with the hyp switch code. | |
26 | */ | |
27 | #define MPIDR_EL1 1 /* MultiProcessor Affinity Register */ | |
28 | #define CSSELR_EL1 2 /* Cache Size Selection Register */ | |
29 | #define SCTLR_EL1 3 /* System Control Register */ | |
30 | #define ACTLR_EL1 4 /* Auxilliary Control Register */ | |
31 | #define CPACR_EL1 5 /* Coprocessor Access Control */ | |
32 | #define TTBR0_EL1 6 /* Translation Table Base Register 0 */ | |
33 | #define TTBR1_EL1 7 /* Translation Table Base Register 1 */ | |
34 | #define TCR_EL1 8 /* Translation Control Register */ | |
35 | #define ESR_EL1 9 /* Exception Syndrome Register */ | |
36 | #define AFSR0_EL1 10 /* Auxilary Fault Status Register 0 */ | |
37 | #define AFSR1_EL1 11 /* Auxilary Fault Status Register 1 */ | |
38 | #define FAR_EL1 12 /* Fault Address Register */ | |
39 | #define MAIR_EL1 13 /* Memory Attribute Indirection Register */ | |
40 | #define VBAR_EL1 14 /* Vector Base Address Register */ | |
41 | #define CONTEXTIDR_EL1 15 /* Context ID Register */ | |
42 | #define TPIDR_EL0 16 /* Thread ID, User R/W */ | |
43 | #define TPIDRRO_EL0 17 /* Thread ID, User R/O */ | |
44 | #define TPIDR_EL1 18 /* Thread ID, Privileged */ | |
45 | #define AMAIR_EL1 19 /* Aux Memory Attribute Indirection Register */ | |
46 | #define CNTKCTL_EL1 20 /* Timer Control Register (EL1) */ | |
1bbd8054 | 47 | #define PAR_EL1 21 /* Physical Address Register */ |
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48 | #define MDSCR_EL1 22 /* Monitor Debug System Control Register */ |
49 | #define DBGBCR0_EL1 23 /* Debug Breakpoint Control Registers (0-15) */ | |
50 | #define DBGBCR15_EL1 38 | |
51 | #define DBGBVR0_EL1 39 /* Debug Breakpoint Value Registers (0-15) */ | |
52 | #define DBGBVR15_EL1 54 | |
53 | #define DBGWCR0_EL1 55 /* Debug Watchpoint Control Registers (0-15) */ | |
54 | #define DBGWCR15_EL1 70 | |
55 | #define DBGWVR0_EL1 71 /* Debug Watchpoint Value Registers (0-15) */ | |
56 | #define DBGWVR15_EL1 86 | |
57 | #define MDCCINT_EL1 87 /* Monitor Debug Comms Channel Interrupt Enable Reg */ | |
58 | ||
40033a61 | 59 | /* 32bit specific registers. Keep them at the end of the range */ |
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60 | #define DACR32_EL2 88 /* Domain Access Control Register */ |
61 | #define IFSR32_EL2 89 /* Instruction Fault Status Register */ | |
62 | #define FPEXC32_EL2 90 /* Floating-Point Exception Control Register */ | |
63 | #define DBGVCR32_EL2 91 /* Debug Vector Catch Register */ | |
64 | #define TEECR32_EL1 92 /* ThumbEE Configuration Register */ | |
65 | #define TEEHBR32_EL1 93 /* ThumbEE Handler Base Register */ | |
66 | #define NR_SYS_REGS 94 | |
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67 | |
68 | /* 32bit mapping */ | |
69 | #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ | |
70 | #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ | |
71 | #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ | |
72 | #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ | |
73 | #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ | |
74 | #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ | |
75 | #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ | |
76 | #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ | |
77 | #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ | |
78 | #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ | |
79 | #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ | |
80 | #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ | |
81 | #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ | |
82 | #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ | |
83 | #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ | |
84 | #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ | |
85 | #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ | |
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86 | #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ |
87 | #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ | |
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88 | #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ |
89 | #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ | |
90 | #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ | |
91 | #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ | |
92 | #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ | |
93 | #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ | |
94 | #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ | |
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95 | #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ |
96 | #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ | |
40033a61 | 97 | #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ |
72564016 | 98 | #define NR_COPRO_REGS (NR_SYS_REGS * 2) |
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99 | |
100 | #define ARM_EXCEPTION_IRQ 0 | |
101 | #define ARM_EXCEPTION_TRAP 1 | |
102 | ||
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103 | #define KVM_ARM64_DEBUG_DIRTY_SHIFT 0 |
104 | #define KVM_ARM64_DEBUG_DIRTY (1 << KVM_ARM64_DEBUG_DIRTY_SHIFT) | |
105 | ||
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106 | #ifndef __ASSEMBLY__ |
107 | struct kvm; | |
108 | struct kvm_vcpu; | |
109 | ||
110 | extern char __kvm_hyp_init[]; | |
111 | extern char __kvm_hyp_init_end[]; | |
112 | ||
113 | extern char __kvm_hyp_vector[]; | |
114 | ||
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115 | #define __kvm_hyp_code_start __hyp_text_start |
116 | #define __kvm_hyp_code_end __hyp_text_end | |
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117 | |
118 | extern void __kvm_flush_vm_context(void); | |
119 | extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa); | |
120 | ||
121 | extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu); | |
1a9b1305 | 122 | |
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123 | extern u64 __vgic_v3_get_ich_vtr_el2(void); |
124 | ||
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125 | extern char __save_vgic_v2_state[]; |
126 | extern char __restore_vgic_v2_state[]; | |
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127 | extern char __save_vgic_v3_state[]; |
128 | extern char __restore_vgic_v3_state[]; | |
1a9b1305 | 129 | |
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130 | #endif |
131 | ||
132 | #endif /* __ARM_KVM_ASM_H__ */ |