Commit | Line | Data |
---|---|---|
4f04d8f0 CM |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_PGTABLE_HWDEF_H | |
17 | #define __ASM_PGTABLE_HWDEF_H | |
18 | ||
19 | #ifdef CONFIG_ARM64_64K_PAGES | |
20 | #include <asm/pgtable-2level-hwdef.h> | |
21 | #else | |
22 | #include <asm/pgtable-3level-hwdef.h> | |
23 | #endif | |
24 | ||
25 | /* | |
26 | * Hardware page table definitions. | |
27 | * | |
084bd298 SC |
28 | * Level 1 descriptor (PUD). |
29 | */ | |
30 | ||
31 | #define PUD_TABLE_BIT (_AT(pgdval_t, 1) << 1) | |
32 | ||
33 | /* | |
4f04d8f0 CM |
34 | * Level 2 descriptor (PMD). |
35 | */ | |
36 | #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) | |
37 | #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) | |
38 | #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) | |
39 | #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) | |
084bd298 | 40 | #define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1) |
4f04d8f0 CM |
41 | |
42 | /* | |
43 | * Section | |
44 | */ | |
45 | #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) | |
46 | #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) | |
47 | #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) | |
8e620b04 CM |
48 | #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) |
49 | #define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54) | |
4f04d8f0 CM |
50 | |
51 | /* | |
52 | * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). | |
53 | */ | |
54 | #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) | |
55 | #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) | |
56 | ||
57 | /* | |
58 | * Level 3 descriptor (PTE). | |
59 | */ | |
60 | #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) | |
61 | #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) | |
62 | #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) | |
084bd298 | 63 | #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) |
4f04d8f0 CM |
64 | #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ |
65 | #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ | |
66 | #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ | |
67 | #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ | |
68 | #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ | |
8e620b04 CM |
69 | #define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */ |
70 | #define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */ | |
4f04d8f0 CM |
71 | |
72 | /* | |
73 | * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). | |
74 | */ | |
75 | #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) | |
76 | #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) | |
77 | ||
78 | /* | |
79 | * 40-bit physical address supported. | |
80 | */ | |
81 | #define PHYS_MASK_SHIFT (40) | |
82 | #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) | |
83 | ||
84 | /* | |
85 | * TCR flags. | |
86 | */ | |
87 | #define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0)) | |
88 | #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24)) | |
89 | #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24)) | |
90 | #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24)) | |
91 | #define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24)) | |
92 | #define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24)) | |
93 | #define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26)) | |
94 | #define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26)) | |
95 | #define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26)) | |
96 | #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26)) | |
97 | #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) | |
98 | #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) | |
99 | #define TCR_TG0_64K (UL(1) << 14) | |
100 | #define TCR_TG1_64K (UL(1) << 30) | |
101 | #define TCR_IPS_40BIT (UL(2) << 32) | |
102 | #define TCR_ASID16 (UL(1) << 36) | |
103 | ||
104 | #endif |