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4f04d8f0 CM |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_PGTABLE_H | |
17 | #define __ASM_PGTABLE_H | |
18 | ||
19 | #include <asm/proc-fns.h> | |
20 | ||
21 | #include <asm/memory.h> | |
22 | #include <asm/pgtable-hwdef.h> | |
23 | ||
24 | /* | |
25 | * Software defined PTE bits definition. | |
26 | */ | |
a6fadf7e | 27 | #define PTE_VALID (_AT(pteval_t, 1) << 0) |
3676f9ef | 28 | #define PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !pte_present() */ |
4f04d8f0 CM |
29 | #define PTE_DIRTY (_AT(pteval_t, 1) << 55) |
30 | #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) | |
c2c93e5b | 31 | #define PTE_WRITE (_AT(pteval_t, 1) << 57) |
3676f9ef | 32 | #define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */ |
4f04d8f0 CM |
33 | |
34 | /* | |
35 | * VMALLOC and SPARSEMEM_VMEMMAP ranges. | |
08375198 CM |
36 | * |
37 | * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array | |
38 | * (rounded up to PUD_SIZE). | |
39 | * VMALLOC_START: beginning of the kernel VA space | |
40 | * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space, | |
41 | * fixed mappings and modules | |
4f04d8f0 | 42 | */ |
08375198 | 43 | #define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE) |
847264fb | 44 | #define VMALLOC_START (UL(0xffffffffffffffff) << VA_BITS) |
08375198 | 45 | #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) |
4f04d8f0 CM |
46 | |
47 | #define vmemmap ((struct page *)(VMALLOC_END + SZ_64K)) | |
48 | ||
49 | #define FIRST_USER_ADDRESS 0 | |
50 | ||
51 | #ifndef __ASSEMBLY__ | |
52 | extern void __pte_error(const char *file, int line, unsigned long val); | |
53 | extern void __pmd_error(const char *file, int line, unsigned long val); | |
c79b954b | 54 | extern void __pud_error(const char *file, int line, unsigned long val); |
4f04d8f0 CM |
55 | extern void __pgd_error(const char *file, int line, unsigned long val); |
56 | ||
a501e324 CM |
57 | #ifdef CONFIG_SMP |
58 | #define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) | |
59 | #define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) | |
60 | #else | |
61 | #define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF) | |
62 | #define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF) | |
63 | #endif | |
4f04d8f0 | 64 | |
a501e324 CM |
65 | #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE)) |
66 | #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC)) | |
67 | #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL)) | |
4f04d8f0 | 68 | |
a501e324 CM |
69 | #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) |
70 | #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) | |
71 | #define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) | |
a6fadf7e | 72 | |
a501e324 | 73 | #define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) |
4f04d8f0 | 74 | |
a501e324 CM |
75 | #define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE) |
76 | #define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE) | |
8e620b04 | 77 | |
a501e324 | 78 | #define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP) |
36311607 MZ |
79 | #define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP) |
80 | ||
a501e324 | 81 | #define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY) |
36311607 MZ |
82 | #define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDWR | PTE_UXN) |
83 | ||
a501e324 CM |
84 | #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_PXN | PTE_UXN) |
85 | #define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE) | |
86 | #define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE) | |
87 | #define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) | |
88 | #define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) | |
89 | #define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) | |
90 | #define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN) | |
a501e324 CM |
91 | |
92 | #define __P000 PAGE_NONE | |
93 | #define __P001 PAGE_READONLY | |
94 | #define __P010 PAGE_COPY | |
95 | #define __P011 PAGE_COPY | |
5a0fdfad | 96 | #define __P100 PAGE_READONLY_EXEC |
a501e324 CM |
97 | #define __P101 PAGE_READONLY_EXEC |
98 | #define __P110 PAGE_COPY_EXEC | |
99 | #define __P111 PAGE_COPY_EXEC | |
100 | ||
101 | #define __S000 PAGE_NONE | |
102 | #define __S001 PAGE_READONLY | |
103 | #define __S010 PAGE_SHARED | |
104 | #define __S011 PAGE_SHARED | |
5a0fdfad | 105 | #define __S100 PAGE_READONLY_EXEC |
a501e324 CM |
106 | #define __S101 PAGE_READONLY_EXEC |
107 | #define __S110 PAGE_SHARED_EXEC | |
108 | #define __S111 PAGE_SHARED_EXEC | |
4f04d8f0 | 109 | |
4f04d8f0 CM |
110 | /* |
111 | * ZERO_PAGE is a global shared page that is always zero: used | |
112 | * for zero-mapped memory areas etc.. | |
113 | */ | |
114 | extern struct page *empty_zero_page; | |
115 | #define ZERO_PAGE(vaddr) (empty_zero_page) | |
116 | ||
7078db46 CM |
117 | #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) |
118 | ||
4f04d8f0 CM |
119 | #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) |
120 | ||
121 | #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) | |
122 | ||
123 | #define pte_none(pte) (!pte_val(pte)) | |
124 | #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) | |
125 | #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) | |
7078db46 CM |
126 | |
127 | /* Find an entry in the third-level page table. */ | |
128 | #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | |
129 | ||
9ab6d02f | 130 | #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr)) |
4f04d8f0 CM |
131 | |
132 | #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) | |
133 | #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) | |
134 | #define pte_unmap(pte) do { } while (0) | |
135 | #define pte_unmap_nested(pte) do { } while (0) | |
136 | ||
137 | /* | |
138 | * The following only work if pte_present(). Undefined behaviour otherwise. | |
139 | */ | |
84fe6826 SC |
140 | #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) |
141 | #define pte_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) | |
142 | #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) | |
143 | #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) | |
144 | #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) | |
8e620b04 | 145 | #define pte_exec(pte) (!(pte_val(pte) & PTE_UXN)) |
4f04d8f0 | 146 | |
a6fadf7e | 147 | #define pte_valid_user(pte) \ |
02522463 | 148 | ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) |
7f0b1bf0 CM |
149 | #define pte_valid_not_user(pte) \ |
150 | ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) | |
4f04d8f0 | 151 | |
b6d4f280 | 152 | static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) |
44b6dfc5 | 153 | { |
b6d4f280 | 154 | pte_val(pte) &= ~pgprot_val(prot); |
44b6dfc5 SC |
155 | return pte; |
156 | } | |
157 | ||
b6d4f280 | 158 | static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) |
44b6dfc5 | 159 | { |
b6d4f280 | 160 | pte_val(pte) |= pgprot_val(prot); |
44b6dfc5 SC |
161 | return pte; |
162 | } | |
163 | ||
b6d4f280 LA |
164 | static inline pte_t pte_wrprotect(pte_t pte) |
165 | { | |
166 | return clear_pte_bit(pte, __pgprot(PTE_WRITE)); | |
167 | } | |
168 | ||
169 | static inline pte_t pte_mkwrite(pte_t pte) | |
170 | { | |
171 | return set_pte_bit(pte, __pgprot(PTE_WRITE)); | |
172 | } | |
173 | ||
44b6dfc5 SC |
174 | static inline pte_t pte_mkclean(pte_t pte) |
175 | { | |
b6d4f280 | 176 | return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); |
44b6dfc5 SC |
177 | } |
178 | ||
179 | static inline pte_t pte_mkdirty(pte_t pte) | |
180 | { | |
b6d4f280 | 181 | return set_pte_bit(pte, __pgprot(PTE_DIRTY)); |
44b6dfc5 SC |
182 | } |
183 | ||
184 | static inline pte_t pte_mkold(pte_t pte) | |
185 | { | |
b6d4f280 | 186 | return clear_pte_bit(pte, __pgprot(PTE_AF)); |
44b6dfc5 SC |
187 | } |
188 | ||
189 | static inline pte_t pte_mkyoung(pte_t pte) | |
190 | { | |
b6d4f280 | 191 | return set_pte_bit(pte, __pgprot(PTE_AF)); |
44b6dfc5 SC |
192 | } |
193 | ||
194 | static inline pte_t pte_mkspecial(pte_t pte) | |
195 | { | |
b6d4f280 | 196 | return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); |
44b6dfc5 | 197 | } |
4f04d8f0 CM |
198 | |
199 | static inline void set_pte(pte_t *ptep, pte_t pte) | |
200 | { | |
201 | *ptep = pte; | |
7f0b1bf0 CM |
202 | |
203 | /* | |
204 | * Only if the new pte is valid and kernel, otherwise TLB maintenance | |
205 | * or update_mmu_cache() have the necessary barriers. | |
206 | */ | |
207 | if (pte_valid_not_user(pte)) { | |
208 | dsb(ishst); | |
209 | isb(); | |
210 | } | |
4f04d8f0 CM |
211 | } |
212 | ||
213 | extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); | |
214 | ||
215 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
216 | pte_t *ptep, pte_t pte) | |
217 | { | |
a6fadf7e | 218 | if (pte_valid_user(pte)) { |
71fdb6bf | 219 | if (!pte_special(pte) && pte_exec(pte)) |
02522463 | 220 | __sync_icache_dcache(pte, addr); |
c2c93e5b SC |
221 | if (pte_dirty(pte) && pte_write(pte)) |
222 | pte_val(pte) &= ~PTE_RDONLY; | |
223 | else | |
224 | pte_val(pte) |= PTE_RDONLY; | |
02522463 WD |
225 | } |
226 | ||
4f04d8f0 CM |
227 | set_pte(ptep, pte); |
228 | } | |
229 | ||
230 | /* | |
231 | * Huge pte definitions. | |
232 | */ | |
084bd298 SC |
233 | #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) |
234 | #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) | |
235 | ||
236 | /* | |
237 | * Hugetlb definitions. | |
238 | */ | |
239 | #define HUGE_MAX_HSTATE 2 | |
240 | #define HPAGE_SHIFT PMD_SHIFT | |
241 | #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) | |
242 | #define HPAGE_MASK (~(HPAGE_SIZE - 1)) | |
243 | #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) | |
4f04d8f0 | 244 | |
4f04d8f0 CM |
245 | #define __HAVE_ARCH_PTE_SPECIAL |
246 | ||
29e56940 SC |
247 | static inline pte_t pud_pte(pud_t pud) |
248 | { | |
249 | return __pte(pud_val(pud)); | |
250 | } | |
251 | ||
252 | static inline pmd_t pud_pmd(pud_t pud) | |
253 | { | |
254 | return __pmd(pud_val(pud)); | |
255 | } | |
256 | ||
9c7e535f SC |
257 | static inline pte_t pmd_pte(pmd_t pmd) |
258 | { | |
259 | return __pte(pmd_val(pmd)); | |
260 | } | |
af074848 | 261 | |
9c7e535f SC |
262 | static inline pmd_t pte_pmd(pte_t pte) |
263 | { | |
264 | return __pmd(pte_val(pte)); | |
265 | } | |
af074848 SC |
266 | |
267 | /* | |
268 | * THP definitions. | |
269 | */ | |
af074848 SC |
270 | |
271 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
272 | #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) | |
9c7e535f | 273 | #define pmd_trans_splitting(pmd) pte_special(pmd_pte(pmd)) |
29e56940 SC |
274 | #ifdef CONFIG_HAVE_RCU_TABLE_FREE |
275 | #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH | |
276 | struct vm_area_struct; | |
277 | void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address, | |
278 | pmd_t *pmdp); | |
279 | #endif /* CONFIG_HAVE_RCU_TABLE_FREE */ | |
280 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
af074848 | 281 | |
9c7e535f SC |
282 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) |
283 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) | |
284 | #define pmd_mksplitting(pmd) pte_pmd(pte_mkspecial(pmd_pte(pmd))) | |
285 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) | |
286 | #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) | |
287 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) | |
288 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) | |
e3a920af | 289 | #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK)) |
af074848 | 290 | |
9c7e535f SC |
291 | #define __HAVE_ARCH_PMD_WRITE |
292 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) | |
af074848 SC |
293 | |
294 | #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) | |
295 | ||
296 | #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) | |
297 | #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) | |
298 | #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) | |
299 | ||
300 | #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) | |
29e56940 | 301 | #define pud_write(pud) pte_write(pud_pte(pud)) |
206a2a73 | 302 | #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT) |
af074848 | 303 | |
ceb21835 | 304 | #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) |
af074848 SC |
305 | |
306 | static inline int has_transparent_hugepage(void) | |
307 | { | |
308 | return 1; | |
309 | } | |
310 | ||
a501e324 CM |
311 | #define __pgprot_modify(prot,mask,bits) \ |
312 | __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) | |
313 | ||
4f04d8f0 CM |
314 | /* |
315 | * Mark the prot value as uncacheable and unbufferable. | |
316 | */ | |
317 | #define pgprot_noncached(prot) \ | |
de2db743 | 318 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) |
4f04d8f0 | 319 | #define pgprot_writecombine(prot) \ |
de2db743 | 320 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) |
4f04d8f0 CM |
321 | #define __HAVE_PHYS_MEM_ACCESS_PROT |
322 | struct file; | |
323 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
324 | unsigned long size, pgprot_t vma_prot); | |
325 | ||
326 | #define pmd_none(pmd) (!pmd_val(pmd)) | |
327 | #define pmd_present(pmd) (pmd_val(pmd)) | |
328 | ||
329 | #define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) | |
330 | ||
36311607 MZ |
331 | #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ |
332 | PMD_TYPE_TABLE) | |
333 | #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ | |
334 | PMD_TYPE_SECT) | |
335 | ||
f3b766a2 | 336 | #ifdef CONFIG_ARM64_64K_PAGES |
206a2a73 SC |
337 | #define pud_sect(pud) (0) |
338 | #else | |
339 | #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ | |
340 | PUD_TYPE_SECT) | |
341 | #endif | |
36311607 | 342 | |
4f04d8f0 CM |
343 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
344 | { | |
345 | *pmdp = pmd; | |
98f7685e | 346 | dsb(ishst); |
7f0b1bf0 | 347 | isb(); |
4f04d8f0 CM |
348 | } |
349 | ||
350 | static inline void pmd_clear(pmd_t *pmdp) | |
351 | { | |
352 | set_pmd(pmdp, __pmd(0)); | |
353 | } | |
354 | ||
355 | static inline pte_t *pmd_page_vaddr(pmd_t pmd) | |
356 | { | |
357 | return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK); | |
358 | } | |
359 | ||
360 | #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) | |
361 | ||
362 | /* | |
363 | * Conversion functions: convert a page and protection to a page entry, | |
364 | * and a page entry and page directory to the page they refer to. | |
365 | */ | |
366 | #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) | |
367 | ||
abe669d7 | 368 | #if CONFIG_ARM64_PGTABLE_LEVELS > 2 |
4f04d8f0 | 369 | |
7078db46 CM |
370 | #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) |
371 | ||
4f04d8f0 CM |
372 | #define pud_none(pud) (!pud_val(pud)) |
373 | #define pud_bad(pud) (!(pud_val(pud) & 2)) | |
374 | #define pud_present(pud) (pud_val(pud)) | |
375 | ||
376 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
377 | { | |
378 | *pudp = pud; | |
98f7685e | 379 | dsb(ishst); |
7f0b1bf0 | 380 | isb(); |
4f04d8f0 CM |
381 | } |
382 | ||
383 | static inline void pud_clear(pud_t *pudp) | |
384 | { | |
385 | set_pud(pudp, __pud(0)); | |
386 | } | |
387 | ||
388 | static inline pmd_t *pud_page_vaddr(pud_t pud) | |
389 | { | |
390 | return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); | |
391 | } | |
392 | ||
7078db46 CM |
393 | /* Find an entry in the second-level page table. */ |
394 | #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) | |
395 | ||
396 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) | |
397 | { | |
398 | return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr); | |
399 | } | |
400 | ||
29e56940 SC |
401 | #define pud_page(pud) pmd_page(pud_pmd(pud)) |
402 | ||
abe669d7 | 403 | #endif /* CONFIG_ARM64_PGTABLE_LEVELS > 2 */ |
4f04d8f0 | 404 | |
abe669d7 | 405 | #if CONFIG_ARM64_PGTABLE_LEVELS > 3 |
c79b954b | 406 | |
7078db46 CM |
407 | #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) |
408 | ||
c79b954b JL |
409 | #define pgd_none(pgd) (!pgd_val(pgd)) |
410 | #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) | |
411 | #define pgd_present(pgd) (pgd_val(pgd)) | |
412 | ||
413 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) | |
414 | { | |
415 | *pgdp = pgd; | |
416 | dsb(ishst); | |
417 | } | |
418 | ||
419 | static inline void pgd_clear(pgd_t *pgdp) | |
420 | { | |
421 | set_pgd(pgdp, __pgd(0)); | |
422 | } | |
423 | ||
424 | static inline pud_t *pgd_page_vaddr(pgd_t pgd) | |
425 | { | |
426 | return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK); | |
427 | } | |
428 | ||
7078db46 CM |
429 | /* Find an entry in the frst-level page table. */ |
430 | #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) | |
431 | ||
432 | static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr) | |
433 | { | |
434 | return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr); | |
435 | } | |
436 | ||
abe669d7 | 437 | #endif /* CONFIG_ARM64_PGTABLE_LEVELS > 3 */ |
c79b954b | 438 | |
7078db46 CM |
439 | #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) |
440 | ||
4f04d8f0 CM |
441 | /* to find an entry in a page-table-directory */ |
442 | #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) | |
443 | ||
444 | #define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) | |
445 | ||
446 | /* to find an entry in a kernel page-table-directory */ | |
447 | #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) | |
448 | ||
4f04d8f0 CM |
449 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
450 | { | |
a6fadf7e | 451 | const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | |
c2c93e5b | 452 | PTE_PROT_NONE | PTE_VALID | PTE_WRITE; |
4f04d8f0 CM |
453 | pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); |
454 | return pte; | |
455 | } | |
456 | ||
9c7e535f SC |
457 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
458 | { | |
459 | return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); | |
460 | } | |
461 | ||
4f04d8f0 CM |
462 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
463 | extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; | |
464 | ||
4f04d8f0 CM |
465 | /* |
466 | * Encode and decode a swap entry: | |
3676f9ef CM |
467 | * bits 0-1: present (must be zero) |
468 | * bit 2: PTE_FILE | |
469 | * bits 3-8: swap type | |
470 | * bits 9-57: swap offset | |
4f04d8f0 | 471 | */ |
3676f9ef | 472 | #define __SWP_TYPE_SHIFT 3 |
4f04d8f0 | 473 | #define __SWP_TYPE_BITS 6 |
3676f9ef | 474 | #define __SWP_OFFSET_BITS 49 |
4f04d8f0 CM |
475 | #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) |
476 | #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) | |
3676f9ef | 477 | #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) |
4f04d8f0 CM |
478 | |
479 | #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) | |
3676f9ef | 480 | #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) |
4f04d8f0 CM |
481 | #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) |
482 | ||
483 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
484 | #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) | |
485 | ||
486 | /* | |
487 | * Ensure that there are not more swap files than can be encoded in the kernel | |
aad9061b | 488 | * PTEs. |
4f04d8f0 CM |
489 | */ |
490 | #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) | |
491 | ||
492 | /* | |
493 | * Encode and decode a file entry: | |
3676f9ef CM |
494 | * bits 0-1: present (must be zero) |
495 | * bit 2: PTE_FILE | |
496 | * bits 3-57: file offset / PAGE_SIZE | |
4f04d8f0 CM |
497 | */ |
498 | #define pte_file(pte) (pte_val(pte) & PTE_FILE) | |
3676f9ef CM |
499 | #define pte_to_pgoff(x) (pte_val(x) >> 3) |
500 | #define pgoff_to_pte(x) __pte(((x) << 3) | PTE_FILE) | |
4f04d8f0 | 501 | |
3676f9ef | 502 | #define PTE_FILE_MAX_BITS 55 |
4f04d8f0 CM |
503 | |
504 | extern int kern_addr_valid(unsigned long addr); | |
505 | ||
506 | #include <asm-generic/pgtable.h> | |
507 | ||
4f04d8f0 CM |
508 | #define pgtable_cache_init() do { } while (0) |
509 | ||
510 | #endif /* !__ASSEMBLY__ */ | |
511 | ||
512 | #endif /* __ASM_PGTABLE_H */ |