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08e875c1 CM |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_SMP_H | |
17 | #define __ASM_SMP_H | |
18 | ||
bb905274 SP |
19 | /* Values for secondary_data.status */ |
20 | ||
21 | #define CPU_MMU_OFF (-1) | |
22 | #define CPU_BOOT_SUCCESS (0) | |
23 | /* The cpu invoked ops->cpu_die, synchronise it with cpu_kill */ | |
24 | #define CPU_KILL_ME (1) | |
25 | /* The cpu couldn't die gracefully and is looping in the kernel */ | |
26 | #define CPU_STUCK_IN_KERNEL (2) | |
27 | /* Fatal system error detected by secondary CPU, crash the system */ | |
28 | #define CPU_PANIC_KERNEL (3) | |
29 | ||
30 | #ifndef __ASSEMBLY__ | |
31 | ||
08e875c1 CM |
32 | #include <linux/threads.h> |
33 | #include <linux/cpumask.h> | |
34 | #include <linux/thread_info.h> | |
35 | ||
08e875c1 CM |
36 | #define raw_smp_processor_id() (current_thread_info()->cpu) |
37 | ||
38 | struct seq_file; | |
39 | ||
40 | /* | |
41 | * generate IPI list text | |
42 | */ | |
43 | extern void show_ipi_list(struct seq_file *p, int prec); | |
44 | ||
45 | /* | |
46 | * Called from C code, this handles an IPI. | |
47 | */ | |
48 | extern void handle_IPI(int ipinr, struct pt_regs *regs); | |
49 | ||
50 | /* | |
fccb9a81 HG |
51 | * Discover the set of possible CPUs and determine their |
52 | * SMP operations. | |
08e875c1 | 53 | */ |
0f078336 | 54 | extern void smp_init_cpus(void); |
08e875c1 CM |
55 | |
56 | /* | |
57 | * Provide a function to raise an IPI cross call on CPUs in callmap. | |
58 | */ | |
59 | extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int)); | |
60 | ||
36310736 FW |
61 | extern void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
62 | ||
08e875c1 CM |
63 | /* |
64 | * Called from the secondary holding pen, this is the secondary CPU entry point. | |
65 | */ | |
66 | asmlinkage void secondary_start_kernel(void); | |
67 | ||
68 | /* | |
69 | * Initial data for bringing up a secondary CPU. | |
bb905274 SP |
70 | * @stack - sp for the secondary CPU |
71 | * @status - Result passed back from the secondary CPU to | |
72 | * indicate failure. | |
08e875c1 CM |
73 | */ |
74 | struct secondary_data { | |
75 | void *stack; | |
bb905274 | 76 | long status; |
08e875c1 | 77 | }; |
bb905274 | 78 | |
08e875c1 | 79 | extern struct secondary_data secondary_data; |
bb905274 | 80 | extern long __early_cpu_boot_status; |
652af899 | 81 | extern void secondary_entry(void); |
08e875c1 CM |
82 | |
83 | extern void arch_send_call_function_single_ipi(int cpu); | |
84 | extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); | |
85 | ||
5e89c55e LP |
86 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
87 | extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask); | |
88 | #else | |
89 | static inline void arch_send_wakeup_ipi_mask(const struct cpumask *mask) | |
90 | { | |
91 | BUILD_BUG(); | |
92 | } | |
93 | #endif | |
94 | ||
9327e2c6 MR |
95 | extern int __cpu_disable(void); |
96 | ||
97 | extern void __cpu_die(unsigned int cpu); | |
98 | extern void cpu_die(void); | |
fce6361f | 99 | extern void cpu_die_early(void); |
9327e2c6 | 100 | |
c4bc34d2 SP |
101 | static inline void cpu_park_loop(void) |
102 | { | |
103 | for (;;) { | |
104 | wfe(); | |
105 | wfi(); | |
106 | } | |
107 | } | |
108 | ||
bb905274 SP |
109 | static inline void update_cpu_boot_status(int val) |
110 | { | |
111 | WRITE_ONCE(secondary_data.status, val); | |
112 | /* Ensure the visibility of the status update */ | |
113 | dsb(ishst); | |
114 | } | |
115 | ||
17eebd1a SP |
116 | /* |
117 | * The calling secondary CPU has detected serious configuration mismatch, | |
118 | * which calls for a kernel panic. Update the boot status and park the calling | |
119 | * CPU. | |
120 | */ | |
121 | static inline void cpu_panic_kernel(void) | |
122 | { | |
123 | update_cpu_boot_status(CPU_PANIC_KERNEL); | |
124 | cpu_park_loop(); | |
125 | } | |
126 | ||
5c492c3f JM |
127 | /* |
128 | * If a secondary CPU enters the kernel but fails to come online, | |
129 | * (e.g. due to mismatched features), and cannot exit the kernel, | |
130 | * we increment cpus_stuck_in_kernel and leave the CPU in a | |
131 | * quiesecent loop within the kernel text. The memory containing | |
132 | * this loop must not be re-used for anything else as the 'stuck' | |
133 | * core is executing it. | |
134 | * | |
135 | * This function is used to inhibit features like kexec and hibernate. | |
136 | */ | |
137 | bool cpus_are_stuck_in_kernel(void); | |
138 | ||
bb905274 SP |
139 | #endif /* ifndef __ASSEMBLY__ */ |
140 | ||
08e875c1 | 141 | #endif /* ifndef __ASM_SMP_H */ |