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72c58395 CM |
1 | /* |
2 | * Macros for accessing system registers with older binutils. | |
3 | * | |
4 | * Copyright (C) 2014 ARM Ltd. | |
5 | * Author: Catalin Marinas <catalin.marinas@arm.com> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef __ASM_SYSREG_H | |
21 | #define __ASM_SYSREG_H | |
22 | ||
3600c2fd MR |
23 | #include <linux/stringify.h> |
24 | ||
338d4f49 JM |
25 | #include <asm/opcodes.h> |
26 | ||
9ded63aa SP |
27 | /* |
28 | * ARMv8 ARM reserves the following encoding for system registers: | |
29 | * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", | |
30 | * C5.2, version:ARM DDI 0487A.f) | |
31 | * [20-19] : Op0 | |
32 | * [18-16] : Op1 | |
33 | * [15-12] : CRn | |
34 | * [11-8] : CRm | |
35 | * [7-5] : Op2 | |
36 | */ | |
72c58395 | 37 | #define sys_reg(op0, op1, crn, crm, op2) \ |
9ded63aa | 38 | ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5)) |
72c58395 | 39 | |
3c739b57 SP |
40 | #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) |
41 | #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) | |
42 | #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) | |
43 | ||
44 | #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) | |
45 | #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) | |
46 | #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) | |
47 | #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) | |
48 | #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) | |
49 | #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) | |
50 | #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) | |
51 | ||
52 | #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) | |
53 | #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) | |
54 | #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) | |
55 | #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) | |
56 | #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) | |
57 | #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) | |
58 | #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) | |
59 | ||
60 | #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) | |
61 | #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) | |
62 | #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) | |
63 | ||
64 | #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) | |
65 | #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) | |
66 | ||
67 | #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) | |
68 | #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) | |
69 | ||
70 | #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) | |
71 | #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) | |
72 | ||
73 | #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) | |
74 | #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) | |
406e3087 | 75 | #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) |
3c739b57 SP |
76 | |
77 | #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) | |
78 | #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) | |
79 | #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) | |
80 | ||
81 | #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) | |
57f4959b | 82 | #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3) |
338d4f49 JM |
83 | |
84 | #define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\ | |
85 | (!!x)<<8 | 0x1f) | |
57f4959b JM |
86 | #define SET_PSTATE_UAO(x) __inst_arm(0xd5000000 | REG_PSTATE_UAO_IMM |\ |
87 | (!!x)<<8 | 0x1f) | |
338d4f49 | 88 | |
3c739b57 SP |
89 | /* SCTLR_EL1 */ |
90 | #define SCTLR_EL1_CP15BEN (0x1 << 5) | |
91 | #define SCTLR_EL1_SED (0x1 << 8) | |
92 | #define SCTLR_EL1_SPAN (0x1 << 23) | |
93 | ||
94 | ||
95 | /* id_aa64isar0 */ | |
96 | #define ID_AA64ISAR0_RDM_SHIFT 28 | |
97 | #define ID_AA64ISAR0_ATOMICS_SHIFT 20 | |
98 | #define ID_AA64ISAR0_CRC32_SHIFT 16 | |
99 | #define ID_AA64ISAR0_SHA2_SHIFT 12 | |
100 | #define ID_AA64ISAR0_SHA1_SHIFT 8 | |
101 | #define ID_AA64ISAR0_AES_SHIFT 4 | |
102 | ||
103 | /* id_aa64pfr0 */ | |
104 | #define ID_AA64PFR0_GIC_SHIFT 24 | |
105 | #define ID_AA64PFR0_ASIMD_SHIFT 20 | |
106 | #define ID_AA64PFR0_FP_SHIFT 16 | |
107 | #define ID_AA64PFR0_EL3_SHIFT 12 | |
108 | #define ID_AA64PFR0_EL2_SHIFT 8 | |
109 | #define ID_AA64PFR0_EL1_SHIFT 4 | |
110 | #define ID_AA64PFR0_EL0_SHIFT 0 | |
111 | ||
112 | #define ID_AA64PFR0_FP_NI 0xf | |
113 | #define ID_AA64PFR0_FP_SUPPORTED 0x0 | |
114 | #define ID_AA64PFR0_ASIMD_NI 0xf | |
115 | #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 | |
116 | #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 | |
117 | #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 | |
118 | ||
119 | /* id_aa64mmfr0 */ | |
120 | #define ID_AA64MMFR0_TGRAN4_SHIFT 28 | |
121 | #define ID_AA64MMFR0_TGRAN64_SHIFT 24 | |
122 | #define ID_AA64MMFR0_TGRAN16_SHIFT 20 | |
cdcf817b | 123 | #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 |
3c739b57 | 124 | #define ID_AA64MMFR0_SNSMEM_SHIFT 12 |
cdcf817b | 125 | #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 |
3c739b57 SP |
126 | #define ID_AA64MMFR0_ASID_SHIFT 4 |
127 | #define ID_AA64MMFR0_PARANGE_SHIFT 0 | |
128 | ||
129 | #define ID_AA64MMFR0_TGRAN4_NI 0xf | |
130 | #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 | |
131 | #define ID_AA64MMFR0_TGRAN64_NI 0xf | |
132 | #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 | |
133 | #define ID_AA64MMFR0_TGRAN16_NI 0x0 | |
134 | #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 | |
135 | ||
136 | /* id_aa64mmfr1 */ | |
137 | #define ID_AA64MMFR1_PAN_SHIFT 20 | |
138 | #define ID_AA64MMFR1_LOR_SHIFT 16 | |
139 | #define ID_AA64MMFR1_HPD_SHIFT 12 | |
140 | #define ID_AA64MMFR1_VHE_SHIFT 8 | |
141 | #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 | |
142 | #define ID_AA64MMFR1_HADBS_SHIFT 0 | |
143 | ||
cb678d60 SP |
144 | #define ID_AA64MMFR1_VMIDBITS_8 0 |
145 | #define ID_AA64MMFR1_VMIDBITS_16 2 | |
146 | ||
406e3087 JM |
147 | /* id_aa64mmfr2 */ |
148 | #define ID_AA64MMFR2_UAO_SHIFT 4 | |
149 | ||
3c739b57 SP |
150 | /* id_aa64dfr0 */ |
151 | #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 | |
152 | #define ID_AA64DFR0_WRPS_SHIFT 20 | |
153 | #define ID_AA64DFR0_BRPS_SHIFT 12 | |
154 | #define ID_AA64DFR0_PMUVER_SHIFT 8 | |
155 | #define ID_AA64DFR0_TRACEVER_SHIFT 4 | |
156 | #define ID_AA64DFR0_DEBUGVER_SHIFT 0 | |
157 | ||
158 | #define ID_ISAR5_RDM_SHIFT 24 | |
159 | #define ID_ISAR5_CRC32_SHIFT 16 | |
160 | #define ID_ISAR5_SHA2_SHIFT 12 | |
161 | #define ID_ISAR5_SHA1_SHIFT 8 | |
162 | #define ID_ISAR5_AES_SHIFT 4 | |
163 | #define ID_ISAR5_SEVL_SHIFT 0 | |
164 | ||
165 | #define MVFR0_FPROUND_SHIFT 28 | |
166 | #define MVFR0_FPSHVEC_SHIFT 24 | |
167 | #define MVFR0_FPSQRT_SHIFT 20 | |
168 | #define MVFR0_FPDIVIDE_SHIFT 16 | |
169 | #define MVFR0_FPTRAP_SHIFT 12 | |
170 | #define MVFR0_FPDP_SHIFT 8 | |
171 | #define MVFR0_FPSP_SHIFT 4 | |
172 | #define MVFR0_SIMD_SHIFT 0 | |
173 | ||
174 | #define MVFR1_SIMDFMAC_SHIFT 28 | |
175 | #define MVFR1_FPHP_SHIFT 24 | |
176 | #define MVFR1_SIMDHP_SHIFT 20 | |
177 | #define MVFR1_SIMDSP_SHIFT 16 | |
178 | #define MVFR1_SIMDINT_SHIFT 12 | |
179 | #define MVFR1_SIMDLS_SHIFT 8 | |
180 | #define MVFR1_FPDNAN_SHIFT 4 | |
181 | #define MVFR1_FPFTZ_SHIFT 0 | |
182 | ||
4bf8b96e SP |
183 | |
184 | #define ID_AA64MMFR0_TGRAN4_SHIFT 28 | |
185 | #define ID_AA64MMFR0_TGRAN64_SHIFT 24 | |
186 | #define ID_AA64MMFR0_TGRAN16_SHIFT 20 | |
187 | ||
188 | #define ID_AA64MMFR0_TGRAN4_NI 0xf | |
189 | #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 | |
190 | #define ID_AA64MMFR0_TGRAN64_NI 0xf | |
191 | #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 | |
192 | #define ID_AA64MMFR0_TGRAN16_NI 0x0 | |
193 | #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 | |
194 | ||
195 | #if defined(CONFIG_ARM64_4K_PAGES) | |
196 | #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT | |
197 | #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED | |
44eaacf1 SP |
198 | #elif defined(CONFIG_ARM64_16K_PAGES) |
199 | #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT | |
200 | #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED | |
4bf8b96e SP |
201 | #elif defined(CONFIG_ARM64_64K_PAGES) |
202 | #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT | |
203 | #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED | |
204 | #endif | |
205 | ||
72c58395 CM |
206 | #ifdef __ASSEMBLY__ |
207 | ||
208 | .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 | |
7abc7d83 | 209 | .equ .L__reg_num_x\num, \num |
72c58395 | 210 | .endr |
7abc7d83 | 211 | .equ .L__reg_num_xzr, 31 |
72c58395 CM |
212 | |
213 | .macro mrs_s, rt, sreg | |
7abc7d83 | 214 | .inst 0xd5200000|(\sreg)|(.L__reg_num_\rt) |
72c58395 CM |
215 | .endm |
216 | ||
217 | .macro msr_s, sreg, rt | |
7abc7d83 | 218 | .inst 0xd5000000|(\sreg)|(.L__reg_num_\rt) |
72c58395 CM |
219 | .endm |
220 | ||
221 | #else | |
222 | ||
3600c2fd MR |
223 | #include <linux/types.h> |
224 | ||
72c58395 CM |
225 | asm( |
226 | " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" | |
7abc7d83 | 227 | " .equ .L__reg_num_x\\num, \\num\n" |
72c58395 | 228 | " .endr\n" |
7abc7d83 | 229 | " .equ .L__reg_num_xzr, 31\n" |
72c58395 CM |
230 | "\n" |
231 | " .macro mrs_s, rt, sreg\n" | |
7abc7d83 | 232 | " .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n" |
72c58395 CM |
233 | " .endm\n" |
234 | "\n" | |
235 | " .macro msr_s, sreg, rt\n" | |
7abc7d83 | 236 | " .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n" |
72c58395 CM |
237 | " .endm\n" |
238 | ); | |
239 | ||
870828e5 JM |
240 | static inline void config_sctlr_el1(u32 clear, u32 set) |
241 | { | |
242 | u32 val; | |
243 | ||
244 | asm volatile("mrs %0, sctlr_el1" : "=r" (val)); | |
245 | val &= ~clear; | |
246 | val |= set; | |
247 | asm volatile("msr sctlr_el1, %0" : : "r" (val)); | |
248 | } | |
3600c2fd MR |
249 | |
250 | /* | |
251 | * Unlike read_cpuid, calls to read_sysreg are never expected to be | |
252 | * optimized away or replaced with synthetic values. | |
253 | */ | |
254 | #define read_sysreg(r) ({ \ | |
255 | u64 __val; \ | |
256 | asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ | |
257 | __val; \ | |
258 | }) | |
259 | ||
260 | #define write_sysreg(v, r) do { \ | |
261 | u64 __val = (u64)v; \ | |
262 | asm volatile("msr " __stringify(r) ", %0" \ | |
263 | : : "r" (__val)); \ | |
264 | } while (0) | |
265 | ||
72c58395 CM |
266 | #endif |
267 | ||
268 | #endif /* __ASM_SYSREG_H */ |