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f35a9205 MZ |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software: you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __ASM__VIRT_H | |
19 | #define __ASM__VIRT_H | |
20 | ||
21 | #define BOOT_CPU_MODE_EL2 (0x0e12b007) | |
22 | ||
23 | #ifndef __ASSEMBLY__ | |
82b2f495 | 24 | #include <asm/cacheflush.h> |
f35a9205 MZ |
25 | |
26 | /* | |
27 | * __boot_cpu_mode records what mode CPUs were booted in. | |
28 | * A correctly-implemented bootloader must start all CPUs in the same mode: | |
29 | * In this case, both 32bit halves of __boot_cpu_mode will contain the | |
30 | * same value (either 0 if booted in EL1, BOOT_CPU_MODE_EL2 if booted in EL2). | |
31 | * | |
32 | * Should the bootloader fail to do this, the two values will be different. | |
33 | * This allows the kernel to flag an error when the secondaries have come up. | |
34 | */ | |
35 | extern u32 __boot_cpu_mode[2]; | |
36 | ||
712c6ff4 MZ |
37 | void __hyp_set_vectors(phys_addr_t phys_vector_base); |
38 | phys_addr_t __hyp_get_vectors(void); | |
39 | ||
82b2f495 MR |
40 | static inline void sync_boot_mode(void) |
41 | { | |
42 | /* | |
43 | * As secondaries write to __boot_cpu_mode with caches disabled, we | |
44 | * must flush the corresponding cache entries to ensure the visibility | |
45 | * of their writes. | |
46 | */ | |
47 | __flush_dcache_area(__boot_cpu_mode, sizeof(__boot_cpu_mode)); | |
48 | } | |
49 | ||
f35a9205 MZ |
50 | /* Reports the availability of HYP mode */ |
51 | static inline bool is_hyp_mode_available(void) | |
52 | { | |
82b2f495 | 53 | sync_boot_mode(); |
f35a9205 MZ |
54 | return (__boot_cpu_mode[0] == BOOT_CPU_MODE_EL2 && |
55 | __boot_cpu_mode[1] == BOOT_CPU_MODE_EL2); | |
56 | } | |
57 | ||
58 | /* Check if the bootloader has booted CPUs in different modes */ | |
59 | static inline bool is_hyp_mode_mismatched(void) | |
60 | { | |
82b2f495 | 61 | sync_boot_mode(); |
f35a9205 MZ |
62 | return __boot_cpu_mode[0] != __boot_cpu_mode[1]; |
63 | } | |
64 | ||
65 | #endif /* __ASSEMBLY__ */ | |
66 | ||
67 | #endif /* ! __ASM__VIRT_H */ |