[deliverable/linux.git] / arch / arm64 / kernel / armv8_deprecated.c

/*
 *  Copyright (C) 2014 ARM Limited
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/perf_event.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/sysctl.h>

#include <asm/alternative.h>
#include <asm/cpufeature.h>
#include <asm/insn.h>
#include <asm/opcodes.h>
#include <asm/sysreg.h>
#include <asm/system_misc.h>
#include <asm/traps.h>
#include <asm/uaccess.h>
#include <asm/cpufeature.h>

#define CREATE_TRACE_POINTS
#include "trace-events-emulation.h"

/*
 * The runtime support for deprecated instruction support can be in one of
 * following three states -
 *
 * 0 = undef
 * 1 = emulate (software emulation)
 * 2 = hw (supported in hardware)
 */
enum insn_emulation_mode {
	INSN_UNDEF,
	INSN_EMULATE,
	INSN_HW,
};

enum legacy_insn_status {
	INSN_DEPRECATED,
	INSN_OBSOLETE,
};

struct insn_emulation_ops {
	const char		*name;
	enum legacy_insn_status	status;
	struct undef_hook	*hooks;
	int			(*set_hw_mode)(bool enable);
};

struct insn_emulation {
	struct list_head node;
	struct insn_emulation_ops *ops;
	int current_mode;
	int min;
	int max;
};

static LIST_HEAD(insn_emulation);
static int nr_insn_emulated __initdata;
static DEFINE_RAW_SPINLOCK(insn_emulation_lock);

static void register_emulation_hooks(struct insn_emulation_ops *ops)
{
	struct undef_hook *hook;

	BUG_ON(!ops->hooks);

	for (hook = ops->hooks; hook->instr_mask; hook++)
		register_undef_hook(hook);

	pr_notice("Registered %s emulation handler\n", ops->name);
}

static void remove_emulation_hooks(struct insn_emulation_ops *ops)
{
	struct undef_hook *hook;

	BUG_ON(!ops->hooks);

	for (hook = ops->hooks; hook->instr_mask; hook++)
		unregister_undef_hook(hook);

	pr_notice("Removed %s emulation handler\n", ops->name);
}

static void enable_insn_hw_mode(void *data)
{
	struct insn_emulation *insn = (struct insn_emulation *)data;
	if (insn->ops->set_hw_mode)
		insn->ops->set_hw_mode(true);
}

static void disable_insn_hw_mode(void *data)
{
	struct insn_emulation *insn = (struct insn_emulation *)data;
	if (insn->ops->set_hw_mode)
		insn->ops->set_hw_mode(false);
}

/* Run set_hw_mode(mode) on all active CPUs */
static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
{
	if (!insn->ops->set_hw_mode)
		return -EINVAL;
	if (enable)
		on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
	else
		on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
	return 0;
}

/*
 * Run set_hw_mode for all insns on a starting CPU.
 * Returns:
 *  0 		- If all the hooks ran successfully.
 * -EINVAL	- At least one hook is not supported by the CPU.
 */
static int run_all_insn_set_hw_mode(unsigned int cpu)
{
	int rc = 0;
	unsigned long flags;
	struct insn_emulation *insn;

	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
	list_for_each_entry(insn, &insn_emulation, node) {
		bool enable = (insn->current_mode == INSN_HW);
		if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
			pr_warn("CPU[%u] cannot support the emulation of %s",
				cpu, insn->ops->name);
			rc = -EINVAL;
		}
	}
	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
	return rc;
}

static int update_insn_emulation_mode(struct insn_emulation *insn,
				       enum insn_emulation_mode prev)
{
	int ret = 0;

	switch (prev) {
	case INSN_UNDEF: /* Nothing to be done */
		break;
	case INSN_EMULATE:
		remove_emulation_hooks(insn->ops);
		break;
	case INSN_HW:
		if (!run_all_cpu_set_hw_mode(insn, false))
			pr_notice("Disabled %s support\n", insn->ops->name);
		break;
	}

	switch (insn->current_mode) {
	case INSN_UNDEF:
		break;
	case INSN_EMULATE:
		register_emulation_hooks(insn->ops);
		break;
	case INSN_HW:
		ret = run_all_cpu_set_hw_mode(insn, true);
		if (!ret)
			pr_notice("Enabled %s support\n", insn->ops->name);
		break;
	}

	return ret;
}

static void __init register_insn_emulation(struct insn_emulation_ops *ops)
{
	unsigned long flags;
	struct insn_emulation *insn;

	insn = kzalloc(sizeof(*insn), GFP_KERNEL);
	insn->ops = ops;
	insn->min = INSN_UNDEF;

	switch (ops->status) {
	case INSN_DEPRECATED:
		insn->current_mode = INSN_EMULATE;
		/* Disable the HW mode if it was turned on at early boot time */
		run_all_cpu_set_hw_mode(insn, false);
		insn->max = INSN_HW;
		break;
	case INSN_OBSOLETE:
		insn->current_mode = INSN_UNDEF;
		insn->max = INSN_EMULATE;
		break;
	}

	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
	list_add(&insn->node, &insn_emulation);
	nr_insn_emulated++;
	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);

	/* Register any handlers if required */
	update_insn_emulation_mode(insn, INSN_UNDEF);
}

static int emulation_proc_handler(struct ctl_table *table, int write,
				  void __user *buffer, size_t *lenp,
				  loff_t *ppos)
{
	int ret = 0;
	struct insn_emulation *insn = (struct insn_emulation *) table->data;
	enum insn_emulation_mode prev_mode = insn->current_mode;

	table->data = &insn->current_mode;
	ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);

	if (ret || !write || prev_mode == insn->current_mode)
		goto ret;

	ret = update_insn_emulation_mode(insn, prev_mode);
	if (ret) {
		/* Mode change failed, revert to previous mode. */
		insn->current_mode = prev_mode;
		update_insn_emulation_mode(insn, INSN_UNDEF);
	}
ret:
	table->data = insn;
	return ret;
}

static struct ctl_table ctl_abi[] = {
	{
		.procname = "abi",
		.mode = 0555,
	},
	{ }
};

static void __init register_insn_emulation_sysctl(struct ctl_table *table)
{
	unsigned long flags;
	int i = 0;
	struct insn_emulation *insn;
	struct ctl_table *insns_sysctl, *sysctl;

	insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1),
			      GFP_KERNEL);

	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
	list_for_each_entry(insn, &insn_emulation, node) {
		sysctl = &insns_sysctl[i];

		sysctl->mode = 0644;
		sysctl->maxlen = sizeof(int);

		sysctl->procname = insn->ops->name;
		sysctl->data = insn;
		sysctl->extra1 = &insn->min;
		sysctl->extra2 = &insn->max;
		sysctl->proc_handler = emulation_proc_handler;
		i++;
	}
	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);

	table->child = insns_sysctl;
	register_sysctl_table(table);
}

/*
 *  Implement emulation of the SWP/SWPB instructions using load-exclusive and
 *  store-exclusive.
 *
 *  Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
 *  Where: Rt  = destination
 *	   Rt2 = source
 *	   Rn  = address
 */

/*
 * Error-checking SWP macros implemented using ldxr{b}/stxr{b}
 */
#define __user_swpX_asm(data, addr, res, temp, B)		\
	__asm__ __volatile__(					\
	ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN,	\
		    CONFIG_ARM64_PAN)				\
	"0:	ldxr"B"		%w2, [%3]\n"			\
	"1:	stxr"B"		%w0, %w1, [%3]\n"		\
	"	cbz		%w0, 2f\n"			\
	"	mov		%w0, %w4\n"			\
	"	b		3f\n"				\
	"2:\n"							\
	"	mov		%w1, %w2\n"			\
	"3:\n"							\
	"	.pushsection	 .fixup,\"ax\"\n"		\
	"	.align		2\n"				\
	"4:	mov		%w0, %w5\n"			\
	"	b		3b\n"				\
	"	.popsection"					\
	_ASM_EXTABLE(0b, 4b)					\
	_ASM_EXTABLE(1b, 4b)					\
	ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN,	\
		CONFIG_ARM64_PAN)				\
	: "=&r" (res), "+r" (data), "=&r" (temp)		\
	: "r" (addr), "i" (-EAGAIN), "i" (-EFAULT)		\
	: "memory")

#define __user_swp_asm(data, addr, res, temp) \
	__user_swpX_asm(data, addr, res, temp, "")
#define __user_swpb_asm(data, addr, res, temp) \
	__user_swpX_asm(data, addr, res, temp, "b")

/*
 * Bit 22 of the instruction encoding distinguishes between
 * the SWP and SWPB variants (bit set means SWPB).
 */
#define TYPE_SWPB (1 << 22)

static int emulate_swpX(unsigned int address, unsigned int *data,
			unsigned int type)
{
	unsigned int res = 0;

	if ((type != TYPE_SWPB) && (address & 0x3)) {
		/* SWP to unaligned address not permitted */
		pr_debug("SWP instruction on unaligned pointer!\n");
		return -EFAULT;
	}

	while (1) {
		unsigned long temp;

		if (type == TYPE_SWPB)
			__user_swpb_asm(*data, address, res, temp);
		else
			__user_swp_asm(*data, address, res, temp);

		if (likely(res != -EAGAIN) || signal_pending(current))
			break;

		cond_resched();
	}

	return res;
}

#define	ARM_OPCODE_CONDITION_UNCOND	0xf

static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
{
	u32 cc_bits  = opcode >> 28;

	if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
		if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
			return ARM_OPCODE_CONDTEST_PASS;
		else
			return ARM_OPCODE_CONDTEST_FAIL;
	}
	return ARM_OPCODE_CONDTEST_UNCOND;
}

/*
 * swp_handler logs the id of calling process, dissects the instruction, sanity
 * checks the memory location, calls emulate_swpX for the actual operation and
 * deals with fixup/error handling before returning
 */
static int swp_handler(struct pt_regs *regs, u32 instr)
{
	u32 destreg, data, type, address = 0;
	int rn, rt2, res = 0;

	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);

	type = instr & TYPE_SWPB;

	switch (aarch32_check_condition(instr, regs->pstate)) {
	case ARM_OPCODE_CONDTEST_PASS:
		break;
	case ARM_OPCODE_CONDTEST_FAIL:
		/* Condition failed - return to next instruction */
		goto ret;
	case ARM_OPCODE_CONDTEST_UNCOND:
		/* If unconditional encoding - not a SWP, undef */
		return -EFAULT;
	default:
		return -EINVAL;
	}

	rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
	rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);

	address = (u32)regs->user_regs.regs[rn];
	data	= (u32)regs->user_regs.regs[rt2];
	destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);

	pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
		rn, address, destreg,
		aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);

	/* Check access in reasonable access range for both SWP and SWPB */
	if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
		pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
			address);
		goto fault;
	}

	res = emulate_swpX(address, &data, type);
	if (res == -EFAULT)
		goto fault;
	else if (res == 0)
		regs->user_regs.regs[destreg] = data;

ret:
	if (type == TYPE_SWPB)
		trace_instruction_emulation("swpb", regs->pc);
	else
		trace_instruction_emulation("swp", regs->pc);

	pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
			current->comm, (unsigned long)current->pid, regs->pc);

	regs->pc += 4;
	return 0;

fault:
	pr_debug("SWP{B} emulation: access caused memory abort!\n");
	arm64_notify_segfault(regs, address);

	return 0;
}

/*
 * Only emulate SWP/SWPB executed in ARM state/User mode.
 * The kernel must be SWP free and SWP{B} does not exist in Thumb.
 */
static struct undef_hook swp_hooks[] = {
	{
		.instr_mask	= 0x0fb00ff0,
		.instr_val	= 0x01000090,
		.pstate_mask	= COMPAT_PSR_MODE_MASK,
		.pstate_val	= COMPAT_PSR_MODE_USR,
		.fn		= swp_handler
	},
	{ }
};

static struct insn_emulation_ops swp_ops = {
	.name = "swp",
	.status = INSN_OBSOLETE,
	.hooks = swp_hooks,
	.set_hw_mode = NULL,
};

static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
{
	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);

	switch (aarch32_check_condition(instr, regs->pstate)) {
	case ARM_OPCODE_CONDTEST_PASS:
		break;
	case ARM_OPCODE_CONDTEST_FAIL:
		/* Condition failed - return to next instruction */
		goto ret;
	case ARM_OPCODE_CONDTEST_UNCOND:
		/* If unconditional encoding - not a barrier instruction */
		return -EFAULT;
	default:
		return -EINVAL;
	}

	switch (aarch32_insn_mcr_extract_crm(instr)) {
	case 10:
		/*
		 * dmb - mcr p15, 0, Rt, c7, c10, 5
		 * dsb - mcr p15, 0, Rt, c7, c10, 4
		 */
		if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
			dmb(sy);
			trace_instruction_emulation(
				"mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
		} else {
			dsb(sy);
			trace_instruction_emulation(
				"mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
		}
		break;
	case 5:
		/*
		 * isb - mcr p15, 0, Rt, c7, c5, 4
		 *
		 * Taking an exception or returning from one acts as an
		 * instruction barrier. So no explicit barrier needed here.
		 */
		trace_instruction_emulation(
			"mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
		break;
	}

ret:
	pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
			current->comm, (unsigned long)current->pid, regs->pc);

	regs->pc += 4;
	return 0;
}

static int cp15_barrier_set_hw_mode(bool enable)
{
	if (enable)
		config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
	else
		config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
	return 0;
}

static struct undef_hook cp15_barrier_hooks[] = {
	{
		.instr_mask	= 0x0fff0fdf,
		.instr_val	= 0x0e070f9a,
		.pstate_mask	= COMPAT_PSR_MODE_MASK,
		.pstate_val	= COMPAT_PSR_MODE_USR,
		.fn		= cp15barrier_handler,
	},
	{
		.instr_mask	= 0x0fff0fff,
		.instr_val	= 0x0e070f95,
		.pstate_mask	= COMPAT_PSR_MODE_MASK,
		.pstate_val	= COMPAT_PSR_MODE_USR,
		.fn		= cp15barrier_handler,
	},
	{ }
};

static struct insn_emulation_ops cp15_barrier_ops = {
	.name = "cp15_barrier",
	.status = INSN_DEPRECATED,
	.hooks = cp15_barrier_hooks,
	.set_hw_mode = cp15_barrier_set_hw_mode,
};

static int setend_set_hw_mode(bool enable)
{
	if (!cpu_supports_mixed_endian_el0())
		return -EINVAL;

	if (enable)
		config_sctlr_el1(SCTLR_EL1_SED, 0);
	else
		config_sctlr_el1(0, SCTLR_EL1_SED);
	return 0;
}

static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
{
	char *insn;

	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);

	if (big_endian) {
		insn = "setend be";
		regs->pstate |= COMPAT_PSR_E_BIT;
	} else {
		insn = "setend le";
		regs->pstate &= ~COMPAT_PSR_E_BIT;
	}

	trace_instruction_emulation(insn, regs->pc);
	pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
			current->comm, (unsigned long)current->pid, regs->pc);

	return 0;
}

static int a32_setend_handler(struct pt_regs *regs, u32 instr)
{
	int rc = compat_setend_handler(regs, (instr >> 9) & 1);
	regs->pc += 4;
	return rc;
}

static int t16_setend_handler(struct pt_regs *regs, u32 instr)
{
	int rc = compat_setend_handler(regs, (instr >> 3) & 1);
	regs->pc += 2;
	return rc;
}

static struct undef_hook setend_hooks[] = {
	{
		.instr_mask	= 0xfffffdff,
		.instr_val	= 0xf1010000,
		.pstate_mask	= COMPAT_PSR_MODE_MASK,
		.pstate_val	= COMPAT_PSR_MODE_USR,
		.fn		= a32_setend_handler,
	},
	{
		/* Thumb mode */
		.instr_mask	= 0x0000fff7,
		.instr_val	= 0x0000b650,
		.pstate_mask	= (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK),
		.pstate_val	= (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR),
		.fn		= t16_setend_handler,
	},
	{}
};

static struct insn_emulation_ops setend_ops = {
	.name = "setend",
	.status = INSN_DEPRECATED,
	.hooks = setend_hooks,
	.set_hw_mode = setend_set_hw_mode,
};

/*
 * Invoked as late_initcall, since not needed before init spawned.
 */
static int __init armv8_deprecated_init(void)
{
	if (IS_ENABLED(CONFIG_SWP_EMULATION))
		register_insn_emulation(&swp_ops);

	if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
		register_insn_emulation(&cp15_barrier_ops);

	if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
		if(system_supports_mixed_endian_el0())
			register_insn_emulation(&setend_ops);
		else
			pr_info("setend instruction emulation is not supported on the system");
	}

	cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
				  "AP_ARM64_ISNDEP_STARTING",
				  run_all_insn_set_hw_mode, NULL);
	register_insn_emulation_sysctl(ctl_abi);

	return 0;
}

late_initcall(armv8_deprecated_init);
Commit	Line	Data
587064b6 PA	1	/*
	2	* Copyright (C) 2014 ARM Limited
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
c852f320	9	#include <linux/cpu.h>
587064b6 PA	10	#include <linux/init.h>
587064b6 PA	11	#include <linux/list.h>
bd35a4ad PA	12	#include <linux/perf_event.h>
bd35a4ad PA	13	#include <linux/sched.h>
587064b6 PA	14	#include <linux/slab.h>
	15	#include <linux/sysctl.h>
	16
338d4f49 JM	17	#include <asm/alternative.h>
338d4f49 JM	18	#include <asm/cpufeature.h>
bd35a4ad PA	19	#include <asm/insn.h>
bd35a4ad PA	20	#include <asm/opcodes.h>
870828e5	21	#include <asm/sysreg.h>
bd35a4ad	22	#include <asm/system_misc.h>
587064b6	23	#include <asm/traps.h>
bd35a4ad	24	#include <asm/uaccess.h>
736d474f	25	#include <asm/cpufeature.h>
587064b6	26
d784e298 PA	27	#define CREATE_TRACE_POINTS
	28	#include "trace-events-emulation.h"
	29
587064b6 PA	30	/*
	31	* The runtime support for deprecated instruction support can be in one of
	32	* following three states -
	33	*
	34	* 0 = undef
	35	* 1 = emulate (software emulation)
	36	* 2 = hw (supported in hardware)
	37	*/
	38	enum insn_emulation_mode {
	39	INSN_UNDEF,
	40	INSN_EMULATE,
	41	INSN_HW,
	42	};
	43
	44	enum legacy_insn_status {
	45	INSN_DEPRECATED,
	46	INSN_OBSOLETE,
	47	};
	48
	49	struct insn_emulation_ops {
	50	const char *name;
	51	enum legacy_insn_status status;
	52	struct undef_hook *hooks;
	53	int (*set_hw_mode)(bool enable);
	54	};
	55
	56	struct insn_emulation {
	57	struct list_head node;
	58	struct insn_emulation_ops *ops;
	59	int current_mode;
	60	int min;
	61	int max;
	62	};
	63
	64	static LIST_HEAD(insn_emulation);
a7c61a34	65	static int nr_insn_emulated __initdata;
587064b6 PA	66	static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
	67
	68	static void register_emulation_hooks(struct insn_emulation_ops *ops)
	69	{
	70	struct undef_hook *hook;
	71
	72	BUG_ON(!ops->hooks);
	73
	74	for (hook = ops->hooks; hook->instr_mask; hook++)
	75	register_undef_hook(hook);
	76
	77	pr_notice("Registered %s emulation handler\n", ops->name);
	78	}
	79
	80	static void remove_emulation_hooks(struct insn_emulation_ops *ops)
	81	{
	82	struct undef_hook *hook;
	83
	84	BUG_ON(!ops->hooks);
	85
	86	for (hook = ops->hooks; hook->instr_mask; hook++)
	87	unregister_undef_hook(hook);
	88
	89	pr_notice("Removed %s emulation handler\n", ops->name);
	90	}
	91
736d474f SP	92	static void enable_insn_hw_mode(void *data)
	93	{
	94	struct insn_emulation insn = (struct insn_emulation )data;
	95	if (insn->ops->set_hw_mode)
	96	insn->ops->set_hw_mode(true);
	97	}
	98
	99	static void disable_insn_hw_mode(void *data)
	100	{
	101	struct insn_emulation insn = (struct insn_emulation )data;
	102	if (insn->ops->set_hw_mode)
	103	insn->ops->set_hw_mode(false);
	104	}
	105
	106	/* Run set_hw_mode(mode) on all active CPUs */
	107	static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
	108	{
	109	if (!insn->ops->set_hw_mode)
	110	return -EINVAL;
	111	if (enable)
	112	on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
	113	else
	114	on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
	115	return 0;
	116	}
	117
	118	/*
	119	* Run set_hw_mode for all insns on a starting CPU.
	120	* Returns:
	121	* 0 - If all the hooks ran successfully.
	122	* -EINVAL - At least one hook is not supported by the CPU.
	123	*/
27c01a8c	124	static int run_all_insn_set_hw_mode(unsigned int cpu)
736d474f SP	125	{
	126	int rc = 0;
	127	unsigned long flags;
	128	struct insn_emulation *insn;
	129
	130	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
	131	list_for_each_entry(insn, &insn_emulation, node) {
	132	bool enable = (insn->current_mode == INSN_HW);
	133	if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
27c01a8c	134	pr_warn("CPU[%u] cannot support the emulation of %s",
736d474f SP	135	cpu, insn->ops->name);
	136	rc = -EINVAL;
	137	}
	138	}
	139	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
	140	return rc;
	141	}
	142
587064b6 PA	143	static int update_insn_emulation_mode(struct insn_emulation *insn,
	144	enum insn_emulation_mode prev)
	145	{
	146	int ret = 0;
	147
	148	switch (prev) {
	149	case INSN_UNDEF: /* Nothing to be done */
	150	break;
	151	case INSN_EMULATE:
	152	remove_emulation_hooks(insn->ops);
	153	break;
	154	case INSN_HW:
736d474f	155	if (!run_all_cpu_set_hw_mode(insn, false))
587064b6	156	pr_notice("Disabled %s support\n", insn->ops->name);
587064b6 PA	157	break;
	158	}
	159
	160	switch (insn->current_mode) {
	161	case INSN_UNDEF:
	162	break;
	163	case INSN_EMULATE:
	164	register_emulation_hooks(insn->ops);
	165	break;
	166	case INSN_HW:
736d474f SP	167	ret = run_all_cpu_set_hw_mode(insn, true);
736d474f SP	168	if (!ret)
587064b6	169	pr_notice("Enabled %s support\n", insn->ops->name);
587064b6 PA	170	break;
	171	}
	172
	173	return ret;
	174	}
	175
a7c61a34	176	static void __init register_insn_emulation(struct insn_emulation_ops *ops)
587064b6 PA	177	{
	178	unsigned long flags;
	179	struct insn_emulation *insn;
	180
	181	insn = kzalloc(sizeof(*insn), GFP_KERNEL);
	182	insn->ops = ops;
	183	insn->min = INSN_UNDEF;
	184
	185	switch (ops->status) {
	186	case INSN_DEPRECATED:
	187	insn->current_mode = INSN_EMULATE;
736d474f SP	188	/* Disable the HW mode if it was turned on at early boot time */
736d474f SP	189	run_all_cpu_set_hw_mode(insn, false);
587064b6 PA	190	insn->max = INSN_HW;
	191	break;
	192	case INSN_OBSOLETE:
	193	insn->current_mode = INSN_UNDEF;
	194	insn->max = INSN_EMULATE;
	195	break;
	196	}
	197
	198	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
	199	list_add(&insn->node, &insn_emulation);
	200	nr_insn_emulated++;
	201	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
	202
	203	/* Register any handlers if required */
	204	update_insn_emulation_mode(insn, INSN_UNDEF);
	205	}
	206
	207	static int emulation_proc_handler(struct ctl_table *table, int write,
	208	void __user buffer, size_t lenp,
	209	loff_t *ppos)
	210	{
	211	int ret = 0;
	212	struct insn_emulation insn = (struct insn_emulation ) table->data;
	213	enum insn_emulation_mode prev_mode = insn->current_mode;
	214
	215	table->data = &insn->current_mode;
	216	ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
	217
	218	if (ret \|\| !write \|\| prev_mode == insn->current_mode)
	219	goto ret;
	220
	221	ret = update_insn_emulation_mode(insn, prev_mode);
90963395	222	if (ret) {
587064b6 PA	223	/* Mode change failed, revert to previous mode. */
	224	insn->current_mode = prev_mode;
	225	update_insn_emulation_mode(insn, INSN_UNDEF);
	226	}
	227	ret:
	228	table->data = insn;
	229	return ret;
	230	}
	231
	232	static struct ctl_table ctl_abi[] = {
	233	{
	234	.procname = "abi",
	235	.mode = 0555,
	236	},
	237	{ }
	238	};
	239
a7c61a34	240	static void __init register_insn_emulation_sysctl(struct ctl_table *table)
587064b6 PA	241	{
	242	unsigned long flags;
	243	int i = 0;
	244	struct insn_emulation *insn;
	245	struct ctl_table insns_sysctl, sysctl;
	246
	247	insns_sysctl = kzalloc(sizeof(sysctl) (nr_insn_emulated + 1),
	248	GFP_KERNEL);
	249
	250	raw_spin_lock_irqsave(&insn_emulation_lock, flags);
	251	list_for_each_entry(insn, &insn_emulation, node) {
	252	sysctl = &insns_sysctl[i];
	253
	254	sysctl->mode = 0644;
	255	sysctl->maxlen = sizeof(int);
	256
	257	sysctl->procname = insn->ops->name;
	258	sysctl->data = insn;
	259	sysctl->extra1 = &insn->min;
	260	sysctl->extra2 = &insn->max;
	261	sysctl->proc_handler = emulation_proc_handler;
	262	i++;
	263	}
	264	raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
	265
	266	table->child = insns_sysctl;
	267	register_sysctl_table(table);
	268	}
	269
bd35a4ad PA	270	/*
	271	* Implement emulation of the SWP/SWPB instructions using load-exclusive and
	272	* store-exclusive.
	273	*
	274	* Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
	275	* Where: Rt = destination
	276	* Rt2 = source
	277	* Rn = address
	278	*/
	279
	280	/*
	281	* Error-checking SWP macros implemented using ldxr{b}/stxr{b}
	282	*/
	283	#define __user_swpX_asm(data, addr, res, temp, B) \
	284	__asm__ __volatile__( \
338d4f49 JM	285	ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \
338d4f49 JM	286	CONFIG_ARM64_PAN) \
589cb22b WD	287	"0: ldxr"B" %w2, [%3]\n" \
589cb22b WD	288	"1: stxr"B" %w0, %w1, [%3]\n" \
bd35a4ad PA	289	" cbz %w0, 2f\n" \
bd35a4ad PA	290	" mov %w0, %w4\n" \
589cb22b	291	" b 3f\n" \
bd35a4ad	292	"2:\n" \
589cb22b WD	293	" mov %w1, %w2\n" \
589cb22b WD	294	"3:\n" \
bd35a4ad PA	295	" .pushsection .fixup,\"ax\"\n" \
bd35a4ad PA	296	" .align 2\n" \
589cb22b WD	297	"4: mov %w0, %w5\n" \
589cb22b WD	298	" b 3b\n" \
bd35a4ad	299	" .popsection" \
6c94f27a AB	300	_ASM_EXTABLE(0b, 4b) \
6c94f27a AB	301	_ASM_EXTABLE(1b, 4b) \
338d4f49 JM	302	ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \
338d4f49 JM	303	CONFIG_ARM64_PAN) \
bd35a4ad PA	304	: "=&r" (res), "+r" (data), "=&r" (temp) \
	305	: "r" (addr), "i" (-EAGAIN), "i" (-EFAULT) \
	306	: "memory")
	307
	308	#define __user_swp_asm(data, addr, res, temp) \
	309	__user_swpX_asm(data, addr, res, temp, "")
	310	#define __user_swpb_asm(data, addr, res, temp) \
	311	__user_swpX_asm(data, addr, res, temp, "b")
	312
	313	/*
	314	* Bit 22 of the instruction encoding distinguishes between
	315	* the SWP and SWPB variants (bit set means SWPB).
	316	*/
	317	#define TYPE_SWPB (1 << 22)
	318
bd35a4ad PA	319	static int emulate_swpX(unsigned int address, unsigned int *data,
	320	unsigned int type)
	321	{
	322	unsigned int res = 0;
	323
	324	if ((type != TYPE_SWPB) && (address & 0x3)) {
	325	/* SWP to unaligned address not permitted */
	326	pr_debug("SWP instruction on unaligned pointer!\n");
	327	return -EFAULT;
	328	}
	329
	330	while (1) {
	331	unsigned long temp;
	332
	333	if (type == TYPE_SWPB)
	334	__user_swpb_asm(*data, address, res, temp);
	335	else
	336	__user_swp_asm(*data, address, res, temp);
	337
	338	if (likely(res != -EAGAIN) \|\| signal_pending(current))
	339	break;
	340
	341	cond_resched();
	342	}
	343
	344	return res;
	345	}
	346
2af3ec08 DL	347	#define ARM_OPCODE_CONDITION_UNCOND 0xf
	348
	349	static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
	350	{
	351	u32 cc_bits = opcode >> 28;
	352
	353	if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
	354	if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
	355	return ARM_OPCODE_CONDTEST_PASS;
	356	else
	357	return ARM_OPCODE_CONDTEST_FAIL;
	358	}
	359	return ARM_OPCODE_CONDTEST_UNCOND;
	360	}
	361
bd35a4ad PA	362	/*
	363	* swp_handler logs the id of calling process, dissects the instruction, sanity
	364	* checks the memory location, calls emulate_swpX for the actual operation and
	365	* deals with fixup/error handling before returning
	366	*/
	367	static int swp_handler(struct pt_regs *regs, u32 instr)
	368	{
	369	u32 destreg, data, type, address = 0;
	370	int rn, rt2, res = 0;
	371
	372	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
	373
	374	type = instr & TYPE_SWPB;
	375
2af3ec08	376	switch (aarch32_check_condition(instr, regs->pstate)) {
bd35a4ad PA	377	case ARM_OPCODE_CONDTEST_PASS:
	378	break;
	379	case ARM_OPCODE_CONDTEST_FAIL:
	380	/* Condition failed - return to next instruction */
	381	goto ret;
	382	case ARM_OPCODE_CONDTEST_UNCOND:
	383	/* If unconditional encoding - not a SWP, undef */
	384	return -EFAULT;
	385	default:
	386	return -EINVAL;
	387	}
	388
	389	rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
	390	rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
	391
	392	address = (u32)regs->user_regs.regs[rn];
	393	data = (u32)regs->user_regs.regs[rt2];
	394	destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
	395
	396	pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
	397	rn, address, destreg,
	398	aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
	399
	400	/* Check access in reasonable access range for both SWP and SWPB */
	401	if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
	402	pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
	403	address);
	404	goto fault;
	405	}
	406
	407	res = emulate_swpX(address, &data, type);
	408	if (res == -EFAULT)
	409	goto fault;
	410	else if (res == 0)
	411	regs->user_regs.regs[destreg] = data;
	412
	413	ret:
d784e298 PA	414	if (type == TYPE_SWPB)
	415	trace_instruction_emulation("swpb", regs->pc);
	416	else
	417	trace_instruction_emulation("swp", regs->pc);
	418
bd35a4ad PA	419	pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
	420	current->comm, (unsigned long)current->pid, regs->pc);
	421
	422	regs->pc += 4;
	423	return 0;
	424
	425	fault:
390bf177 AP	426	pr_debug("SWP{B} emulation: access caused memory abort!\n");
390bf177 AP	427	arm64_notify_segfault(regs, address);
bd35a4ad PA	428
	429	return 0;
	430	}
	431
	432	/*
	433	* Only emulate SWP/SWPB executed in ARM state/User mode.
	434	* The kernel must be SWP free and SWP{B} does not exist in Thumb.
	435	*/
	436	static struct undef_hook swp_hooks[] = {
	437	{
	438	.instr_mask = 0x0fb00ff0,
	439	.instr_val = 0x01000090,
	440	.pstate_mask = COMPAT_PSR_MODE_MASK,
	441	.pstate_val = COMPAT_PSR_MODE_USR,
	442	.fn = swp_handler
	443	},
	444	{ }
	445	};
	446
	447	static struct insn_emulation_ops swp_ops = {
	448	.name = "swp",
	449	.status = INSN_OBSOLETE,
	450	.hooks = swp_hooks,
	451	.set_hw_mode = NULL,
	452	};
	453
c852f320 PA	454	static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
	455	{
	456	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
	457
2af3ec08	458	switch (aarch32_check_condition(instr, regs->pstate)) {
c852f320 PA	459	case ARM_OPCODE_CONDTEST_PASS:
	460	break;
	461	case ARM_OPCODE_CONDTEST_FAIL:
	462	/* Condition failed - return to next instruction */
	463	goto ret;
	464	case ARM_OPCODE_CONDTEST_UNCOND:
	465	/* If unconditional encoding - not a barrier instruction */
	466	return -EFAULT;
	467	default:
	468	return -EINVAL;
	469	}
	470
	471	switch (aarch32_insn_mcr_extract_crm(instr)) {
	472	case 10:
	473	/*
	474	* dmb - mcr p15, 0, Rt, c7, c10, 5
	475	* dsb - mcr p15, 0, Rt, c7, c10, 4
	476	*/
d784e298	477	if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
c852f320	478	dmb(sy);
d784e298 PA	479	trace_instruction_emulation(
	480	"mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
	481	} else {
c852f320	482	dsb(sy);
d784e298 PA	483	trace_instruction_emulation(
	484	"mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
	485	}
c852f320 PA	486	break;
	487	case 5:
	488	/*
	489	* isb - mcr p15, 0, Rt, c7, c5, 4
	490	*
	491	* Taking an exception or returning from one acts as an
	492	* instruction barrier. So no explicit barrier needed here.
	493	*/
d784e298 PA	494	trace_instruction_emulation(
d784e298 PA	495	"mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
c852f320 PA	496	break;
	497	}
	498
	499	ret:
	500	pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
	501	current->comm, (unsigned long)current->pid, regs->pc);
	502
	503	regs->pc += 4;
	504	return 0;
	505	}
	506
c852f320 PA	507	static int cp15_barrier_set_hw_mode(bool enable)
c852f320 PA	508	{
736d474f SP	509	if (enable)
	510	config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
	511	else
	512	config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
	513	return 0;
c852f320 PA	514	}
	515
	516	static struct undef_hook cp15_barrier_hooks[] = {
	517	{
	518	.instr_mask = 0x0fff0fdf,
	519	.instr_val = 0x0e070f9a,
	520	.pstate_mask = COMPAT_PSR_MODE_MASK,
	521	.pstate_val = COMPAT_PSR_MODE_USR,
	522	.fn = cp15barrier_handler,
	523	},
	524	{
	525	.instr_mask = 0x0fff0fff,
	526	.instr_val = 0x0e070f95,
	527	.pstate_mask = COMPAT_PSR_MODE_MASK,
	528	.pstate_val = COMPAT_PSR_MODE_USR,
	529	.fn = cp15barrier_handler,
	530	},
	531	{ }
	532	};
	533
	534	static struct insn_emulation_ops cp15_barrier_ops = {
	535	.name = "cp15_barrier",
	536	.status = INSN_DEPRECATED,
	537	.hooks = cp15_barrier_hooks,
	538	.set_hw_mode = cp15_barrier_set_hw_mode,
	539	};
	540
2d888f48 SP	541	static int setend_set_hw_mode(bool enable)
	542	{
	543	if (!cpu_supports_mixed_endian_el0())
	544	return -EINVAL;
	545
	546	if (enable)
	547	config_sctlr_el1(SCTLR_EL1_SED, 0);
	548	else
	549	config_sctlr_el1(0, SCTLR_EL1_SED);
	550	return 0;
	551	}
	552
	553	static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
	554	{
	555	char *insn;
	556
	557	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
	558
	559	if (big_endian) {
	560	insn = "setend be";
	561	regs->pstate \|= COMPAT_PSR_E_BIT;
	562	} else {
	563	insn = "setend le";
	564	regs->pstate &= ~COMPAT_PSR_E_BIT;
	565	}
	566
	567	trace_instruction_emulation(insn, regs->pc);
	568	pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
	569	current->comm, (unsigned long)current->pid, regs->pc);
	570
	571	return 0;
	572	}
	573
	574	static int a32_setend_handler(struct pt_regs *regs, u32 instr)
	575	{
	576	int rc = compat_setend_handler(regs, (instr >> 9) & 1);
	577	regs->pc += 4;
	578	return rc;
	579	}
	580
	581	static int t16_setend_handler(struct pt_regs *regs, u32 instr)
	582	{
	583	int rc = compat_setend_handler(regs, (instr >> 3) & 1);
	584	regs->pc += 2;
	585	return rc;
	586	}
	587
	588	static struct undef_hook setend_hooks[] = {
	589	{
	590	.instr_mask = 0xfffffdff,
	591	.instr_val = 0xf1010000,
	592	.pstate_mask = COMPAT_PSR_MODE_MASK,
	593	.pstate_val = COMPAT_PSR_MODE_USR,
	594	.fn = a32_setend_handler,
	595	},
	596	{
	597	/* Thumb mode */
	598	.instr_mask = 0x0000fff7,
	599	.instr_val = 0x0000b650,
	600	.pstate_mask = (COMPAT_PSR_T_BIT \| COMPAT_PSR_MODE_MASK),
	601	.pstate_val = (COMPAT_PSR_T_BIT \| COMPAT_PSR_MODE_USR),
	602	.fn = t16_setend_handler,
	603	},
	604	{}
605	};
606
607	static struct insn_emulation_ops setend_ops = {
608	.name = "setend",
609	.status = INSN_DEPRECATED,
610	.hooks = setend_hooks,
611	.set_hw_mode = setend_set_hw_mode,
612	};
613
587064b6 PA	614	/*
	615	* Invoked as late_initcall, since not needed before init spawned.
	616	*/
	617	static int __init armv8_deprecated_init(void)
	618	{
bd35a4ad PA	619	if (IS_ENABLED(CONFIG_SWP_EMULATION))
	620	register_insn_emulation(&swp_ops);
	621
c852f320 PA	622	if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
	623	register_insn_emulation(&cp15_barrier_ops);
	624
2d888f48 SP	625	if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
	626	if(system_supports_mixed_endian_el0())
	627	register_insn_emulation(&setend_ops);
	628	else
	629	pr_info("setend instruction emulation is not supported on the system");
	630	}
	631
27c01a8c SAS	632	cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
	633	"AP_ARM64_ISNDEP_STARTING",
	634	run_all_insn_set_hw_mode, NULL);
587064b6 PA	635	register_insn_emulation_sysctl(ctl_abi);
	636
	637	return 0;
	638	}
	639
	640	late_initcall(armv8_deprecated_init);