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arm64: perf: move to common attr_group fields
[deliverable/linux.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57
SP		 21#include <linux/bsearch.h>
22#include <linux/sort.h>
359b7064
MZ		 23#include <linux/types.h>
24#include <asm/cpu.h>
25#include <asm/cpufeature.h>
dbb4e152 26#include <asm/cpu_ops.h>
13f417f3 27#include <asm/mmu_context.h>
338d4f49 28#include <asm/processor.h>
cdcf817b 29#include <asm/sysreg.h>
d88701be 30#include <asm/virt.h>
359b7064 31
9cdf8ec4
SP		 32unsigned long elf_hwcap __read_mostly;
33EXPORT_SYMBOL_GPL(elf_hwcap);
34
35#ifdef CONFIG_COMPAT
36#define COMPAT_ELF_HWCAP_DEFAULT \
37 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
38 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
39 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
40 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
41 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
42 COMPAT_HWCAP_LPAE)
43unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
44unsigned int compat_elf_hwcap2 __read_mostly;
45#endif
46
47DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
48
efd9e03f
CM		 49DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
50EXPORT_SYMBOL(cpu_hwcap_keys);
51
4f0a606b 52#define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 53 { \
4f0a606b 54 .sign = SIGNED, \
3c739b57
SP		 55 .strict = STRICT, \
56 .type = TYPE, \
57 .shift = SHIFT, \
58 .width = WIDTH, \
59 .safe_val = SAFE_VAL, \
60 }
61
0710cfdb 62/* Define a feature with unsigned values */
4f0a606b 63#define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
4f0a606b
SP		 64 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
65
0710cfdb
SP		 66/* Define a feature with a signed value */
67#define S_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
68 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
69
3c739b57
SP		 70#define ARM64_FTR_END \
71 { \
72 .width = 0, \
73 }
74
70544196
JM		 75/* meta feature for alternatives */
76static bool __maybe_unused
92406f0c
SP		 77cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
78
70544196 79
5e49d73c 80static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
3c739b57
SP		 81 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
82 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
84 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
85 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
86 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
87 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
88 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
89 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
90 ARM64_FTR_END,
91};
92
5e49d73c 93static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
3c739b57
SP		 94 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
95 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
96 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
0710cfdb
SP		 97 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
98 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57
SP		 99 /* Linux doesn't care about the EL3 */
100 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
101 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
102 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
103 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
104 ARM64_FTR_END,
105};
106
5e49d73c 107static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
3c739b57 108 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
0710cfdb
SP		 109 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
110 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
3c739b57
SP		 111 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
112 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
113 /* Linux shouldn't care about secure memory */
114 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
115 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
116 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
117 /*
118 * Differing PARange is fine as long as all peripherals and memory are mapped
119 * within the minimum PARange of all CPUs
120 */
0710cfdb 121 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 122 ARM64_FTR_END,
123};
124
5e49d73c 125static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
3c739b57
SP		 126 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
127 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
130 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
133 ARM64_FTR_END,
134};
135
5e49d73c 136static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
7d7b4ae4
KW		 137 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
138 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
139 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
406e3087 140 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
7d7b4ae4 141 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 142 ARM64_FTR_END,
143};
144
5e49d73c 145static const struct arm64_ftr_bits ftr_ctr[] = {
0710cfdb 146 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
3c739b57 147 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
0710cfdb
SP		 148 ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
149 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
150 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
3c739b57
SP		 151 /*
152 * Linux can handle differing I-cache policies. Userspace JITs will
153 * make use of *minLine
154 */
0710cfdb 155 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
3c739b57 156 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
0710cfdb 157 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
3c739b57
SP		 158 ARM64_FTR_END,
159};
160
675b0563
AB		 161struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
162 .name = "SYS_CTR_EL0",
163 .ftr_bits = ftr_ctr
164};
165
5e49d73c 166static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
0710cfdb 167 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */
3c739b57
SP		 168 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
169 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
170 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
171 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
0710cfdb 172 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */
3c739b57
SP		 173 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
174 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
175 ARM64_FTR_END,
176};
177
5e49d73c 178static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
3c739b57 179 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
0710cfdb
SP		 180 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
181 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
182 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
183 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
184 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
185 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 186 ARM64_FTR_END,
187};
188
5e49d73c 189static const struct arm64_ftr_bits ftr_mvfr2[] = {
3c739b57
SP		 190 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
191 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
192 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
193 ARM64_FTR_END,
194};
195
5e49d73c 196static const struct arm64_ftr_bits ftr_dczid[] = {
3c739b57
SP		 197 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
198 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
199 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
200 ARM64_FTR_END,
201};
202
203
5e49d73c 204static const struct arm64_ftr_bits ftr_id_isar5[] = {
3c739b57
SP		 205 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
206 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
207 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
208 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
209 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
211 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
212 ARM64_FTR_END,
213};
214
5e49d73c 215static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
3c739b57
SP		 216 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
217 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
218 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
219 ARM64_FTR_END,
220};
221
5e49d73c 222static const struct arm64_ftr_bits ftr_id_pfr0[] = {
3c739b57
SP		 223 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
224 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
225 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
226 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
227 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
228 ARM64_FTR_END,
229};
230
5e49d73c 231static const struct arm64_ftr_bits ftr_id_dfr0[] = {
e5343503 232 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
0710cfdb 233 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
e5343503
SP		 234 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
235 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
236 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
237 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
238 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
239 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
240 ARM64_FTR_END,
241};
242
3c739b57
SP		 243/*
244 * Common ftr bits for a 32bit register with all hidden, strict
245 * attributes, with 4bit feature fields and a default safe value of
246 * 0. Covers the following 32bit registers:
247 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
248 */
5e49d73c 249static const struct arm64_ftr_bits ftr_generic_32bits[] = {
3c739b57
SP		 250 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
251 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
252 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
253 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
254 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
255 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
256 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
257 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
258 ARM64_FTR_END,
259};
260
5e49d73c 261static const struct arm64_ftr_bits ftr_generic[] = {
3c739b57
SP		 262 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
263 ARM64_FTR_END,
264};
265
5e49d73c 266static const struct arm64_ftr_bits ftr_generic32[] = {
3c739b57
SP		 267 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
268 ARM64_FTR_END,
269};
270
5e49d73c 271static const struct arm64_ftr_bits ftr_aa64raz[] = {
3c739b57
SP		 272 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
273 ARM64_FTR_END,
274};
275
6f2b7eef
AB		 276#define ARM64_FTR_REG(id, table) { \
277 .sys_id = id, \
278 .reg = &(struct arm64_ftr_reg){ \
3c739b57
SP		 279 .name = #id, \
280 .ftr_bits = &((table)[0]), \
6f2b7eef 281 }}
3c739b57 282
6f2b7eef
AB		 283static const struct __ftr_reg_entry {
284 u32 sys_id;
285 struct arm64_ftr_reg *reg;
286} arm64_ftr_regs[] = {
3c739b57
SP		 287
288 /* Op1 = 0, CRn = 0, CRm = 1 */
289 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
290 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 291 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 292 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
293 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
294 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
295 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
296
297 /* Op1 = 0, CRn = 0, CRm = 2 */
298 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
299 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
300 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
301 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
302 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
303 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
304 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
305
306 /* Op1 = 0, CRn = 0, CRm = 3 */
307 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
308 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
309 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
310
311 /* Op1 = 0, CRn = 0, CRm = 4 */
312 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
313 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
314
315 /* Op1 = 0, CRn = 0, CRm = 5 */
316 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
317 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
318
319 /* Op1 = 0, CRn = 0, CRm = 6 */
320 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
321 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
322
323 /* Op1 = 0, CRn = 0, CRm = 7 */
324 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
325 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 326 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57
SP		 327
328 /* Op1 = 3, CRn = 0, CRm = 0 */
675b0563 329 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
3c739b57
SP		 330 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
331
332 /* Op1 = 3, CRn = 14, CRm = 0 */
333 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
334};
335
336static int search_cmp_ftr_reg(const void *id, const void *regp)
337{
6f2b7eef 338 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
3c739b57
SP		 339}
340
341/*
342 * get_arm64_ftr_reg - Lookup a feature register entry using its
343 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
344 * ascending order of sys_id , we use binary search to find a matching
345 * entry.
346 *
347 * returns - Upon success, matching ftr_reg entry for id.
348 * - NULL on failure. It is upto the caller to decide
349 * the impact of a failure.
350 */
351static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
352{
6f2b7eef
AB		 353 const struct __ftr_reg_entry *ret;
354
355 ret = bsearch((const void *)(unsigned long)sys_id,
3c739b57
SP		 356 arm64_ftr_regs,
357 ARRAY_SIZE(arm64_ftr_regs),
358 sizeof(arm64_ftr_regs[0]),
359 search_cmp_ftr_reg);
6f2b7eef
AB		 360 if (ret)
361 return ret->reg;
362 return NULL;
3c739b57
SP		 363}
364
5e49d73c
AB		 365static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
366 s64 ftr_val)
3c739b57
SP		 367{
368 u64 mask = arm64_ftr_mask(ftrp);
369
370 reg &= ~mask;
371 reg |= (ftr_val << ftrp->shift) & mask;
372 return reg;
373}
374
5e49d73c
AB		 375static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
376 s64 cur)
3c739b57
SP		 377{
378 s64 ret = 0;
379
380 switch (ftrp->type) {
381 case FTR_EXACT:
382 ret = ftrp->safe_val;
383 break;
384 case FTR_LOWER_SAFE:
385 ret = new < cur ? new : cur;
386 break;
387 case FTR_HIGHER_SAFE:
388 ret = new > cur ? new : cur;
389 break;
390 default:
391 BUG();
392 }
393
394 return ret;
395}
396
3c739b57
SP		 397static void __init sort_ftr_regs(void)
398{
6f2b7eef
AB		 399 int i;
400
401 /* Check that the array is sorted so that we can do the binary search */
402 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
403 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
3c739b57
SP		 404}
405
406/*
407 * Initialise the CPU feature register from Boot CPU values.
408 * Also initiliases the strict_mask for the register.
409 */
410static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
411{
412 u64 val = 0;
413 u64 strict_mask = ~0x0ULL;
5e49d73c 414 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 415 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
416
417 BUG_ON(!reg);
418
419 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
420 s64 ftr_new = arm64_ftr_value(ftrp, new);
421
422 val = arm64_ftr_set_value(ftrp, val, ftr_new);
423 if (!ftrp->strict)
424 strict_mask &= ~arm64_ftr_mask(ftrp);
425 }
426 reg->sys_val = val;
427 reg->strict_mask = strict_mask;
428}
429
430void __init init_cpu_features(struct cpuinfo_arm64 *info)
431{
432 /* Before we start using the tables, make sure it is sorted */
433 sort_ftr_regs();
434
435 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
436 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
437 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
438 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
439 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
440 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
441 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
442 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
443 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 444 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 445 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
446 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
a6dc3cd7
SP		 447
448 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
449 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
450 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
451 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
452 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
453 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
454 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
455 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
456 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
457 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
458 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
459 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
460 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
461 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
462 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
463 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
464 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
465 }
466
3c739b57
SP		 467}
468
3086d391 469static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57 470{
5e49d73c 471 const struct arm64_ftr_bits *ftrp;
3c739b57
SP		 472
473 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
474 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
475 s64 ftr_new = arm64_ftr_value(ftrp, new);
476
477 if (ftr_cur == ftr_new)
478 continue;
479 /* Find a safe value */
480 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
481 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
482 }
483
484}
485
3086d391 486static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 487{
3086d391
SP		 488 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
489
490 BUG_ON(!regp);
491 update_cpu_ftr_reg(regp, val);
492 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
493 return 0;
494 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
495 regp->name, boot, cpu, val);
496 return 1;
497}
498
499/*
500 * Update system wide CPU feature registers with the values from a
501 * non-boot CPU. Also performs SANITY checks to make sure that there
502 * aren't any insane variations from that of the boot CPU.
503 */
504void update_cpu_features(int cpu,
505 struct cpuinfo_arm64 *info,
506 struct cpuinfo_arm64 *boot)
507{
508 int taint = 0;
509
510 /*
511 * The kernel can handle differing I-cache policies, but otherwise
512 * caches should look identical. Userspace JITs will make use of
513 * *minLine.
514 */
515 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
516 info->reg_ctr, boot->reg_ctr);
517
518 /*
519 * Userspace may perform DC ZVA instructions. Mismatched block sizes
520 * could result in too much or too little memory being zeroed if a
521 * process is preempted and migrated between CPUs.
522 */
523 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
524 info->reg_dczid, boot->reg_dczid);
525
526 /* If different, timekeeping will be broken (especially with KVM) */
527 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
528 info->reg_cntfrq, boot->reg_cntfrq);
529
530 /*
531 * The kernel uses self-hosted debug features and expects CPUs to
532 * support identical debug features. We presently need CTX_CMPs, WRPs,
533 * and BRPs to be identical.
534 * ID_AA64DFR1 is currently RES0.
535 */
536 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
537 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
538 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
539 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
540 /*
541 * Even in big.LITTLE, processors should be identical instruction-set
542 * wise.
543 */
544 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
545 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
546 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
547 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
548
549 /*
550 * Differing PARange support is fine as long as all peripherals and
551 * memory are mapped within the minimum PARange of all CPUs.
552 * Linux should not care about secure memory.
553 */
554 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
555 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
556 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
557 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 558 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
559 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 560
561 /*
562 * EL3 is not our concern.
563 * ID_AA64PFR1 is currently RES0.
564 */
565 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
566 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
567 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
568 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
569
570 /*
a6dc3cd7
SP		 571 * If we have AArch32, we care about 32-bit features for compat.
572 * If the system doesn't support AArch32, don't update them.
3086d391 573 */
a6dc3cd7
SP		 574 if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1)) &&
575 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
576
577 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 578 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 579 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 580 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 581 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 582 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 583 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 584 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 585 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 586 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 587 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 588 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 589 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP		 590 info->reg_id_isar5, boot->reg_id_isar5);
591
a6dc3cd7
SP		 592 /*
593 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
594 * ACTLR formats could differ across CPUs and therefore would have to
595 * be trapped for virtualization anyway.
596 */
597 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 598 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 599 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 600 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 601 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 602 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 603 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 604 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 605 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 606 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 607 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 608 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 609 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 610 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 611 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 612 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 613 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 614 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 615 }
3086d391
SP		 616
617 /*
618 * Mismatched CPU features are a recipe for disaster. Don't even
619 * pretend to support them.
620 */
621 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
622 "Unsupported CPU feature variation.\n");
cdcf817b
SP		 623}
624
b3f15378
SP		 625u64 read_system_reg(u32 id)
626{
627 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
628
629 /* We shouldn't get a request for an unsupported register */
630 BUG_ON(!regp);
631 return regp->sys_val;
632}
359b7064 633
92406f0c
SP		 634/*
635 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
636 * Read the system register on the current CPU
637 */
638static u64 __raw_read_system_reg(u32 sys_id)
639{
640 switch (sys_id) {
641 case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1);
642 case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1);
643 case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1);
644 case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1);
645 case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1);
646 case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1);
647 case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1);
648 case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1);
649 case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1);
650 case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1);
651 case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1);
652 case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1);
653 case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR4_EL1);
654 case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1);
655 case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1);
656 case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1);
657
658 case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1);
659 case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR0_EL1);
660 case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1);
661 case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR0_EL1);
662 case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1);
663 case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1);
664 case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1);
665 case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1);
666 case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1);
667
668 case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0);
669 case SYS_CTR_EL0: return read_cpuid(CTR_EL0);
670 case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0);
671 default:
672 BUG();
673 return 0;
674 }
675}
676
963fcd40
MZ		 677#include <linux/irqchip/arm-gic-v3.h>
678
18ffa046
JM		 679static bool
680feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
681{
28c5dcb2 682 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 683
684 return val >= entry->min_field_value;
685}
686
da8d02d1 687static bool
92406f0c 688has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 689{
690 u64 val;
94a9e04a 691
92406f0c
SP		 692 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
693 if (scope == SCOPE_SYSTEM)
694 val = read_system_reg(entry->sys_reg);
695 else
696 val = __raw_read_system_reg(entry->sys_reg);
697
da8d02d1
SP		 698 return feature_matches(val, entry);
699}
338d4f49 700
92406f0c 701static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 702{
703 bool has_sre;
704
92406f0c 705 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 706 return false;
707
708 has_sre = gic_enable_sre();
709 if (!has_sre)
710 pr_warn_once("%s present but disabled by higher exception level\n",
711 entry->desc);
712
713 return has_sre;
714}
715
92406f0c 716static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 717{
718 u32 midr = read_cpuid_id();
719 u32 rv_min, rv_max;
720
721 /* Cavium ThunderX pass 1.x and 2.x */
722 rv_min = 0;
723 rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
724
725 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
726}
727
92406f0c 728static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
d88701be
MZ		 729{
730 return is_kernel_in_hyp_mode();
731}
732
d1745910
MZ		 733static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
734 int __unused)
735{
736 phys_addr_t idmap_addr = virt_to_phys(__hyp_idmap_text_start);
737
738 /*
739 * Activate the lower HYP offset only if:
740 * - the idmap doesn't clash with it,
741 * - the kernel is not running at EL2.
742 */
743 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
744}
745
359b7064 746static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 747 {
748 .desc = "GIC system register CPU interface",
749 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
92406f0c 750 .def_scope = SCOPE_SYSTEM,
963fcd40 751 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 752 .sys_reg = SYS_ID_AA64PFR0_EL1,
753 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 754 .sign = FTR_UNSIGNED,
18ffa046 755 .min_field_value = 1,
94a9e04a 756 },
338d4f49
JM		 757#ifdef CONFIG_ARM64_PAN
758 {
759 .desc = "Privileged Access Never",
760 .capability = ARM64_HAS_PAN,
92406f0c 761 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP		 762 .matches = has_cpuid_feature,
763 .sys_reg = SYS_ID_AA64MMFR1_EL1,
764 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 765 .sign = FTR_UNSIGNED,
338d4f49
JM		 766 .min_field_value = 1,
767 .enable = cpu_enable_pan,
768 },
769#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 770#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
771 {
772 .desc = "LSE atomic instructions",
773 .capability = ARM64_HAS_LSE_ATOMICS,
92406f0c 774 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP		 775 .matches = has_cpuid_feature,
776 .sys_reg = SYS_ID_AA64ISAR0_EL1,
777 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 778 .sign = FTR_UNSIGNED,
2e94da13
WD		 779 .min_field_value = 2,
780 },
781#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 782 {
783 .desc = "Software prefetching using PRFM",
784 .capability = ARM64_HAS_NO_HW_PREFETCH,
92406f0c 785 .def_scope = SCOPE_SYSTEM,
d5370f75
WD		 786 .matches = has_no_hw_prefetch,
787 },
57f4959b
JM		 788#ifdef CONFIG_ARM64_UAO
789 {
790 .desc = "User Access Override",
791 .capability = ARM64_HAS_UAO,
92406f0c 792 .def_scope = SCOPE_SYSTEM,
57f4959b
JM		 793 .matches = has_cpuid_feature,
794 .sys_reg = SYS_ID_AA64MMFR2_EL1,
795 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
796 .min_field_value = 1,
797 .enable = cpu_enable_uao,
798 },
799#endif /* CONFIG_ARM64_UAO */
70544196
JM		 800#ifdef CONFIG_ARM64_PAN
801 {
802 .capability = ARM64_ALT_PAN_NOT_UAO,
92406f0c 803 .def_scope = SCOPE_SYSTEM,
70544196
JM		 804 .matches = cpufeature_pan_not_uao,
805 },
806#endif /* CONFIG_ARM64_PAN */
d88701be
MZ		 807 {
808 .desc = "Virtualization Host Extensions",
809 .capability = ARM64_HAS_VIRT_HOST_EXTN,
92406f0c 810 .def_scope = SCOPE_SYSTEM,
d88701be
MZ		 811 .matches = runs_at_el2,
812 },
042446a3
SP		 813 {
814 .desc = "32-bit EL0 Support",
815 .capability = ARM64_HAS_32BIT_EL0,
92406f0c 816 .def_scope = SCOPE_SYSTEM,
042446a3
SP		 817 .matches = has_cpuid_feature,
818 .sys_reg = SYS_ID_AA64PFR0_EL1,
819 .sign = FTR_UNSIGNED,
820 .field_pos = ID_AA64PFR0_EL0_SHIFT,
821 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
822 },
d1745910
MZ		 823 {
824 .desc = "Reduced HYP mapping offset",
825 .capability = ARM64_HYP_OFFSET_LOW,
826 .def_scope = SCOPE_SYSTEM,
827 .matches = hyp_offset_low,
828 },
359b7064
MZ		 829 {},
830};
831
ff96f7bc 832#define HWCAP_CAP(reg, field, s, min_value, type, cap) \
37b01d53
SP		 833 { \
834 .desc = #cap, \
92406f0c 835 .def_scope = SCOPE_SYSTEM, \
37b01d53
SP		 836 .matches = has_cpuid_feature, \
837 .sys_reg = reg, \
838 .field_pos = field, \
ff96f7bc 839 .sign = s, \
37b01d53
SP		 840 .min_field_value = min_value, \
841 .hwcap_type = type, \
842 .hwcap = cap, \
843 }
844
f3efb675 845static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP		 846 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
847 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
848 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
849 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
850 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
851 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
852 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 853 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 854 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 855 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
75283501
SP		 856 {},
857};
858
859static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 860#ifdef CONFIG_COMPAT
ff96f7bc
SP		 861 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
862 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
863 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
864 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
865 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 866#endif
867 {},
868};
869
f3efb675 870static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 871{
872 switch (cap->hwcap_type) {
873 case CAP_HWCAP:
874 elf_hwcap |= cap->hwcap;
875 break;
876#ifdef CONFIG_COMPAT
877 case CAP_COMPAT_HWCAP:
878 compat_elf_hwcap |= (u32)cap->hwcap;
879 break;
880 case CAP_COMPAT_HWCAP2:
881 compat_elf_hwcap2 |= (u32)cap->hwcap;
882 break;
883#endif
884 default:
885 WARN_ON(1);
886 break;
887 }
888}
889
890/* Check if we have a particular HWCAP enabled */
f3efb675 891static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 892{
893 bool rc;
894
895 switch (cap->hwcap_type) {
896 case CAP_HWCAP:
897 rc = (elf_hwcap & cap->hwcap) != 0;
898 break;
899#ifdef CONFIG_COMPAT
900 case CAP_COMPAT_HWCAP:
901 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
902 break;
903 case CAP_COMPAT_HWCAP2:
904 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
905 break;
906#endif
907 default:
908 WARN_ON(1);
909 rc = false;
910 }
911
912 return rc;
913}
914
75283501 915static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 916{
75283501 917 for (; hwcaps->matches; hwcaps++)
92406f0c 918 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
75283501 919 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 920}
921
ce8b602c 922void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
359b7064
MZ		 923 const char *info)
924{
75283501 925 for (; caps->matches; caps++) {
92406f0c 926 if (!caps->matches(caps, caps->def_scope))
359b7064
MZ		 927 continue;
928
75283501
SP		 929 if (!cpus_have_cap(caps->capability) && caps->desc)
930 pr_info("%s %s\n", info, caps->desc);
931 cpus_set_cap(caps->capability);
359b7064 932 }
ce8b602c
SP		 933}
934
935/*
dbb4e152
SP		 936 * Run through the enabled capabilities and enable() it on all active
937 * CPUs
ce8b602c 938 */
8e231852 939void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
ce8b602c 940{
75283501
SP		 941 for (; caps->matches; caps++)
942 if (caps->enable && cpus_have_cap(caps->capability))
943 on_each_cpu(caps->enable, NULL, true);
dbb4e152
SP		 944}
945
dbb4e152
SP		 946/*
947 * Flag to indicate if we have computed the system wide
948 * capabilities based on the boot time active CPUs. This
949 * will be used to determine if a new booting CPU should
950 * go through the verification process to make sure that it
951 * supports the system capabilities, without using a hotplug
952 * notifier.
953 */
954static bool sys_caps_initialised;
955
956static inline void set_sys_caps_initialised(void)
957{
958 sys_caps_initialised = true;
959}
960
961/*
13f417f3
SP		 962 * Check for CPU features that are used in early boot
963 * based on the Boot CPU value.
dbb4e152 964 */
13f417f3 965static void check_early_cpu_features(void)
dbb4e152 966{
ac1ad20f 967 verify_cpu_run_el();
13f417f3 968 verify_cpu_asid_bits();
dbb4e152 969}
1c076303 970
75283501
SP		 971static void
972verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
973{
974
92406f0c
SP		 975 for (; caps->matches; caps++)
976 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 977 pr_crit("CPU%d: missing HWCAP: %s\n",
978 smp_processor_id(), caps->desc);
979 cpu_die_early();
980 }
75283501
SP		 981}
982
983static void
984verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
985{
986 for (; caps->matches; caps++) {
92406f0c 987 if (!cpus_have_cap(caps->capability))
75283501
SP		 988 continue;
989 /*
990 * If the new CPU misses an advertised feature, we cannot proceed
991 * further, park the cpu.
992 */
92406f0c 993 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 994 pr_crit("CPU%d: missing feature: %s\n",
995 smp_processor_id(), caps->desc);
996 cpu_die_early();
997 }
998 if (caps->enable)
999 caps->enable(NULL);
1000 }
1001}
1002
dbb4e152
SP		 1003/*
1004 * Run through the enabled system capabilities and enable() it on this CPU.
1005 * The capabilities were decided based on the available CPUs at the boot time.
1006 * Any new CPU should match the system wide status of the capability. If the
1007 * new CPU doesn't have a capability which the system now has enabled, we
1008 * cannot do anything to fix it up and could cause unexpected failures. So
1009 * we park the CPU.
1010 */
1011void verify_local_cpu_capabilities(void)
1012{
dbb4e152 1013
13f417f3
SP		 1014 check_early_cpu_features();
1015
dbb4e152
SP		 1016 /*
1017 * If we haven't computed the system capabilities, there is nothing
1018 * to verify.
1019 */
1020 if (!sys_caps_initialised)
1021 return;
1022
6a6efbb4 1023 verify_local_cpu_errata();
75283501
SP		 1024 verify_local_cpu_features(arm64_features);
1025 verify_local_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1026 if (system_supports_32bit_el0())
1027 verify_local_elf_hwcaps(compat_elf_hwcaps);
359b7064
MZ		 1028}
1029
a7c61a34 1030static void __init setup_feature_capabilities(void)
359b7064 1031{
ce8b602c
SP		 1032 update_cpu_capabilities(arm64_features, "detected feature:");
1033 enable_cpu_capabilities(arm64_features);
359b7064
MZ		 1034}
1035
e3661b12
MZ		 1036/*
1037 * Check if the current CPU has a given feature capability.
1038 * Should be called from non-preemptible context.
1039 */
1040bool this_cpu_has_cap(unsigned int cap)
1041{
1042 const struct arm64_cpu_capabilities *caps;
1043
1044 if (WARN_ON(preemptible()))
1045 return false;
1046
1047 for (caps = arm64_features; caps->desc; caps++)
1048 if (caps->capability == cap && caps->matches)
1049 return caps->matches(caps, SCOPE_LOCAL_CPU);
1050
1051 return false;
1052}
1053
9cdf8ec4 1054void __init setup_cpu_features(void)
359b7064 1055{
9cdf8ec4
SP		 1056 u32 cwg;
1057 int cls;
1058
dbb4e152
SP		 1059 /* Set the CPU feature capabilies */
1060 setup_feature_capabilities();
8e231852 1061 enable_errata_workarounds();
75283501 1062 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1063
1064 if (system_supports_32bit_el0())
1065 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152
SP		 1066
1067 /* Advertise that we have computed the system capabilities */
1068 set_sys_caps_initialised();
1069
9cdf8ec4
SP		 1070 /*
1071 * Check for sane CTR_EL0.CWG value.
1072 */
1073 cwg = cache_type_cwg();
1074 cls = cache_line_size();
1075 if (!cwg)
1076 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1077 cls);
1078 if (L1_CACHE_BYTES < cls)
1079 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1080 L1_CACHE_BYTES, cls);
359b7064 1081}
70544196
JM		 1082
1083static bool __maybe_unused
92406f0c 1084cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196
JM		 1085{
1086 return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
1087}
Linux kernel - Deliverables
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