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arm64: Add helper for extracting ASIDBits
[deliverable/linux.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57
SP		 21#include <linux/bsearch.h>
22#include <linux/sort.h>
359b7064
MZ		 23#include <linux/types.h>
24#include <asm/cpu.h>
25#include <asm/cpufeature.h>
dbb4e152 26#include <asm/cpu_ops.h>
338d4f49 27#include <asm/processor.h>
cdcf817b 28#include <asm/sysreg.h>
359b7064 29
9cdf8ec4
SP		 30unsigned long elf_hwcap __read_mostly;
31EXPORT_SYMBOL_GPL(elf_hwcap);
32
33#ifdef CONFIG_COMPAT
34#define COMPAT_ELF_HWCAP_DEFAULT \
35 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
36 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
37 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
38 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
39 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
40 COMPAT_HWCAP_LPAE)
41unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
42unsigned int compat_elf_hwcap2 __read_mostly;
43#endif
44
45DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
46
4f0a606b 47#define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 48 { \
4f0a606b 49 .sign = SIGNED, \
3c739b57
SP		 50 .strict = STRICT, \
51 .type = TYPE, \
52 .shift = SHIFT, \
53 .width = WIDTH, \
54 .safe_val = SAFE_VAL, \
55 }
56
4f0a606b
SP		 57/* Define a feature with signed values */
58#define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
59 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
60
61/* Define a feature with unsigned value */
62#define U_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
63 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
64
3c739b57
SP		 65#define ARM64_FTR_END \
66 { \
67 .width = 0, \
68 }
69
70544196
JM		 70/* meta feature for alternatives */
71static bool __maybe_unused
72cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry);
73
3c739b57
SP		 74static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
75 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
76 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
77 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
78 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
79 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
80 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
81 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
82 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
84 ARM64_FTR_END,
85};
86
87static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
88 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
89 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
90 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
91 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
92 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
93 /* Linux doesn't care about the EL3 */
94 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
95 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
96 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
97 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
98 ARM64_FTR_END,
99};
100
101static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
102 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
103 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
104 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
105 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
106 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
107 /* Linux shouldn't care about secure memory */
108 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
109 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
110 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
111 /*
112 * Differing PARange is fine as long as all peripherals and memory are mapped
113 * within the minimum PARange of all CPUs
114 */
4f0a606b 115 U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 116 ARM64_FTR_END,
117};
118
119static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
120 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
121 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
122 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
123 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
124 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
125 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
127 ARM64_FTR_END,
128};
129
406e3087
JM		 130static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
131 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
132 ARM64_FTR_END,
133};
134
3c739b57 135static struct arm64_ftr_bits ftr_ctr[] = {
4f0a606b 136 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
3c739b57 137 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
4f0a606b
SP		 138 U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
139 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
140 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
3c739b57
SP		 141 /*
142 * Linux can handle differing I-cache policies. Userspace JITs will
143 * make use of *minLine
144 */
4f0a606b 145 U_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
3c739b57 146 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
4f0a606b 147 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
3c739b57
SP		 148 ARM64_FTR_END,
149};
150
151static struct arm64_ftr_bits ftr_id_mmfr0[] = {
152 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0), /* InnerShr */
153 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
154 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
155 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
156 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
157 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* OuterShr */
158 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
159 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
160 ARM64_FTR_END,
161};
162
163static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
164 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
4f0a606b
SP		 165 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
166 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
167 U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
168 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
169 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
170 U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 171 ARM64_FTR_END,
172};
173
174static struct arm64_ftr_bits ftr_mvfr2[] = {
175 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
176 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
177 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
178 ARM64_FTR_END,
179};
180
181static struct arm64_ftr_bits ftr_dczid[] = {
182 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
183 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
184 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
185 ARM64_FTR_END,
186};
187
188
189static struct arm64_ftr_bits ftr_id_isar5[] = {
190 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
192 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
197 ARM64_FTR_END,
198};
199
200static struct arm64_ftr_bits ftr_id_mmfr4[] = {
201 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
202 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
203 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
204 ARM64_FTR_END,
205};
206
207static struct arm64_ftr_bits ftr_id_pfr0[] = {
208 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
209 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
210 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
211 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
212 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
213 ARM64_FTR_END,
214};
215
216/*
217 * Common ftr bits for a 32bit register with all hidden, strict
218 * attributes, with 4bit feature fields and a default safe value of
219 * 0. Covers the following 32bit registers:
220 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
221 */
222static struct arm64_ftr_bits ftr_generic_32bits[] = {
223 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
224 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
225 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
226 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
227 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
228 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
229 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
230 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
231 ARM64_FTR_END,
232};
233
234static struct arm64_ftr_bits ftr_generic[] = {
235 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
236 ARM64_FTR_END,
237};
238
239static struct arm64_ftr_bits ftr_generic32[] = {
240 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
241 ARM64_FTR_END,
242};
243
244static struct arm64_ftr_bits ftr_aa64raz[] = {
245 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
246 ARM64_FTR_END,
247};
248
249#define ARM64_FTR_REG(id, table) \
250 { \
251 .sys_id = id, \
252 .name = #id, \
253 .ftr_bits = &((table)[0]), \
254 }
255
256static struct arm64_ftr_reg arm64_ftr_regs[] = {
257
258 /* Op1 = 0, CRn = 0, CRm = 1 */
259 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
260 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
261 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_generic_32bits),
262 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
263 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
264 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
265 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
266
267 /* Op1 = 0, CRn = 0, CRm = 2 */
268 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
269 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
270 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
271 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
272 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
273 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
274 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
275
276 /* Op1 = 0, CRn = 0, CRm = 3 */
277 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
278 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
279 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
280
281 /* Op1 = 0, CRn = 0, CRm = 4 */
282 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
283 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
284
285 /* Op1 = 0, CRn = 0, CRm = 5 */
286 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
287 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
288
289 /* Op1 = 0, CRn = 0, CRm = 6 */
290 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
291 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
292
293 /* Op1 = 0, CRn = 0, CRm = 7 */
294 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
295 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 296 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57
SP		 297
298 /* Op1 = 3, CRn = 0, CRm = 0 */
299 ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
300 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
301
302 /* Op1 = 3, CRn = 14, CRm = 0 */
303 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
304};
305
306static int search_cmp_ftr_reg(const void *id, const void *regp)
307{
308 return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
309}
310
311/*
312 * get_arm64_ftr_reg - Lookup a feature register entry using its
313 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
314 * ascending order of sys_id , we use binary search to find a matching
315 * entry.
316 *
317 * returns - Upon success, matching ftr_reg entry for id.
318 * - NULL on failure. It is upto the caller to decide
319 * the impact of a failure.
320 */
321static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
322{
323 return bsearch((const void *)(unsigned long)sys_id,
324 arm64_ftr_regs,
325 ARRAY_SIZE(arm64_ftr_regs),
326 sizeof(arm64_ftr_regs[0]),
327 search_cmp_ftr_reg);
328}
329
330static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
331{
332 u64 mask = arm64_ftr_mask(ftrp);
333
334 reg &= ~mask;
335 reg |= (ftr_val << ftrp->shift) & mask;
336 return reg;
337}
338
339static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
340{
341 s64 ret = 0;
342
343 switch (ftrp->type) {
344 case FTR_EXACT:
345 ret = ftrp->safe_val;
346 break;
347 case FTR_LOWER_SAFE:
348 ret = new < cur ? new : cur;
349 break;
350 case FTR_HIGHER_SAFE:
351 ret = new > cur ? new : cur;
352 break;
353 default:
354 BUG();
355 }
356
357 return ret;
358}
359
360static int __init sort_cmp_ftr_regs(const void *a, const void *b)
361{
362 return ((const struct arm64_ftr_reg *)a)->sys_id -
363 ((const struct arm64_ftr_reg *)b)->sys_id;
364}
365
366static void __init swap_ftr_regs(void *a, void *b, int size)
367{
368 struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
369 *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
370 *(struct arm64_ftr_reg *)b = tmp;
371}
372
373static void __init sort_ftr_regs(void)
374{
375 /* Keep the array sorted so that we can do the binary search */
376 sort(arm64_ftr_regs,
377 ARRAY_SIZE(arm64_ftr_regs),
378 sizeof(arm64_ftr_regs[0]),
379 sort_cmp_ftr_regs,
380 swap_ftr_regs);
381}
382
383/*
384 * Initialise the CPU feature register from Boot CPU values.
385 * Also initiliases the strict_mask for the register.
386 */
387static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
388{
389 u64 val = 0;
390 u64 strict_mask = ~0x0ULL;
391 struct arm64_ftr_bits *ftrp;
392 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
393
394 BUG_ON(!reg);
395
396 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
397 s64 ftr_new = arm64_ftr_value(ftrp, new);
398
399 val = arm64_ftr_set_value(ftrp, val, ftr_new);
400 if (!ftrp->strict)
401 strict_mask &= ~arm64_ftr_mask(ftrp);
402 }
403 reg->sys_val = val;
404 reg->strict_mask = strict_mask;
405}
406
407void __init init_cpu_features(struct cpuinfo_arm64 *info)
408{
409 /* Before we start using the tables, make sure it is sorted */
410 sort_ftr_regs();
411
412 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
413 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
414 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
415 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
416 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
417 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
418 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
419 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
420 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 421 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 422 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
423 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
424 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
425 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
426 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
427 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
428 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
429 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
430 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
431 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
432 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
433 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
434 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
435 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
436 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
437 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
438 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
439 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
3c739b57
SP		 440}
441
3086d391 442static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57
SP		 443{
444 struct arm64_ftr_bits *ftrp;
3c739b57
SP		 445
446 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
447 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
448 s64 ftr_new = arm64_ftr_value(ftrp, new);
449
450 if (ftr_cur == ftr_new)
451 continue;
452 /* Find a safe value */
453 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
454 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
455 }
456
457}
458
3086d391 459static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 460{
3086d391
SP		 461 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
462
463 BUG_ON(!regp);
464 update_cpu_ftr_reg(regp, val);
465 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
466 return 0;
467 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
468 regp->name, boot, cpu, val);
469 return 1;
470}
471
472/*
473 * Update system wide CPU feature registers with the values from a
474 * non-boot CPU. Also performs SANITY checks to make sure that there
475 * aren't any insane variations from that of the boot CPU.
476 */
477void update_cpu_features(int cpu,
478 struct cpuinfo_arm64 *info,
479 struct cpuinfo_arm64 *boot)
480{
481 int taint = 0;
482
483 /*
484 * The kernel can handle differing I-cache policies, but otherwise
485 * caches should look identical. Userspace JITs will make use of
486 * *minLine.
487 */
488 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
489 info->reg_ctr, boot->reg_ctr);
490
491 /*
492 * Userspace may perform DC ZVA instructions. Mismatched block sizes
493 * could result in too much or too little memory being zeroed if a
494 * process is preempted and migrated between CPUs.
495 */
496 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
497 info->reg_dczid, boot->reg_dczid);
498
499 /* If different, timekeeping will be broken (especially with KVM) */
500 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
501 info->reg_cntfrq, boot->reg_cntfrq);
502
503 /*
504 * The kernel uses self-hosted debug features and expects CPUs to
505 * support identical debug features. We presently need CTX_CMPs, WRPs,
506 * and BRPs to be identical.
507 * ID_AA64DFR1 is currently RES0.
508 */
509 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
510 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
511 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
512 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
513 /*
514 * Even in big.LITTLE, processors should be identical instruction-set
515 * wise.
516 */
517 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
518 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
519 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
520 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
521
522 /*
523 * Differing PARange support is fine as long as all peripherals and
524 * memory are mapped within the minimum PARange of all CPUs.
525 * Linux should not care about secure memory.
526 */
527 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
528 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
529 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
530 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 531 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
532 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 533
534 /*
535 * EL3 is not our concern.
536 * ID_AA64PFR1 is currently RES0.
537 */
538 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
539 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
540 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
541 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
542
543 /*
544 * If we have AArch32, we care about 32-bit features for compat. These
545 * registers should be RES0 otherwise.
546 */
547 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
548 info->reg_id_dfr0, boot->reg_id_dfr0);
549 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
550 info->reg_id_isar0, boot->reg_id_isar0);
551 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
552 info->reg_id_isar1, boot->reg_id_isar1);
553 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
554 info->reg_id_isar2, boot->reg_id_isar2);
555 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
556 info->reg_id_isar3, boot->reg_id_isar3);
557 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
558 info->reg_id_isar4, boot->reg_id_isar4);
559 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
560 info->reg_id_isar5, boot->reg_id_isar5);
561
562 /*
563 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
564 * ACTLR formats could differ across CPUs and therefore would have to
565 * be trapped for virtualization anyway.
566 */
567 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
568 info->reg_id_mmfr0, boot->reg_id_mmfr0);
569 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
570 info->reg_id_mmfr1, boot->reg_id_mmfr1);
571 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
572 info->reg_id_mmfr2, boot->reg_id_mmfr2);
573 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
574 info->reg_id_mmfr3, boot->reg_id_mmfr3);
575 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
576 info->reg_id_pfr0, boot->reg_id_pfr0);
577 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
578 info->reg_id_pfr1, boot->reg_id_pfr1);
579 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
580 info->reg_mvfr0, boot->reg_mvfr0);
581 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
582 info->reg_mvfr1, boot->reg_mvfr1);
583 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
584 info->reg_mvfr2, boot->reg_mvfr2);
585
586 /*
587 * Mismatched CPU features are a recipe for disaster. Don't even
588 * pretend to support them.
589 */
590 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
591 "Unsupported CPU feature variation.\n");
cdcf817b
SP		 592}
593
b3f15378
SP		 594u64 read_system_reg(u32 id)
595{
596 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
597
598 /* We shouldn't get a request for an unsupported register */
599 BUG_ON(!regp);
600 return regp->sys_val;
601}
359b7064 602
963fcd40
MZ		 603#include <linux/irqchip/arm-gic-v3.h>
604
18ffa046
JM		 605static bool
606feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
607{
608 int val = cpuid_feature_extract_field(reg, entry->field_pos);
609
610 return val >= entry->min_field_value;
611}
612
da8d02d1
SP		 613static bool
614has_cpuid_feature(const struct arm64_cpu_capabilities *entry)
615{
616 u64 val;
94a9e04a 617
da8d02d1
SP		 618 val = read_system_reg(entry->sys_reg);
619 return feature_matches(val, entry);
620}
338d4f49 621
963fcd40
MZ		 622static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
623{
624 bool has_sre;
625
2dc10ad8 626 if (!has_cpuid_feature(entry))
963fcd40
MZ		 627 return false;
628
629 has_sre = gic_enable_sre();
630 if (!has_sre)
631 pr_warn_once("%s present but disabled by higher exception level\n",
632 entry->desc);
633
634 return has_sre;
635}
636
d5370f75
WD		 637static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry)
638{
639 u32 midr = read_cpuid_id();
640 u32 rv_min, rv_max;
641
642 /* Cavium ThunderX pass 1.x and 2.x */
643 rv_min = 0;
644 rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
645
646 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
647}
648
359b7064 649static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 650 {
651 .desc = "GIC system register CPU interface",
652 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
963fcd40 653 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 654 .sys_reg = SYS_ID_AA64PFR0_EL1,
655 .field_pos = ID_AA64PFR0_GIC_SHIFT,
18ffa046 656 .min_field_value = 1,
94a9e04a 657 },
338d4f49
JM		 658#ifdef CONFIG_ARM64_PAN
659 {
660 .desc = "Privileged Access Never",
661 .capability = ARM64_HAS_PAN,
da8d02d1
SP		 662 .matches = has_cpuid_feature,
663 .sys_reg = SYS_ID_AA64MMFR1_EL1,
664 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
338d4f49
JM		 665 .min_field_value = 1,
666 .enable = cpu_enable_pan,
667 },
668#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 669#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
670 {
671 .desc = "LSE atomic instructions",
672 .capability = ARM64_HAS_LSE_ATOMICS,
da8d02d1
SP		 673 .matches = has_cpuid_feature,
674 .sys_reg = SYS_ID_AA64ISAR0_EL1,
675 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
2e94da13
WD		 676 .min_field_value = 2,
677 },
678#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 679 {
680 .desc = "Software prefetching using PRFM",
681 .capability = ARM64_HAS_NO_HW_PREFETCH,
682 .matches = has_no_hw_prefetch,
683 },
57f4959b
JM		 684#ifdef CONFIG_ARM64_UAO
685 {
686 .desc = "User Access Override",
687 .capability = ARM64_HAS_UAO,
688 .matches = has_cpuid_feature,
689 .sys_reg = SYS_ID_AA64MMFR2_EL1,
690 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
691 .min_field_value = 1,
692 .enable = cpu_enable_uao,
693 },
694#endif /* CONFIG_ARM64_UAO */
70544196
JM		 695#ifdef CONFIG_ARM64_PAN
696 {
697 .capability = ARM64_ALT_PAN_NOT_UAO,
698 .matches = cpufeature_pan_not_uao,
699 },
700#endif /* CONFIG_ARM64_PAN */
359b7064
MZ		 701 {},
702};
703
37b01d53
SP		 704#define HWCAP_CAP(reg, field, min_value, type, cap) \
705 { \
706 .desc = #cap, \
707 .matches = has_cpuid_feature, \
708 .sys_reg = reg, \
709 .field_pos = field, \
710 .min_field_value = min_value, \
711 .hwcap_type = type, \
712 .hwcap = cap, \
713 }
714
715static const struct arm64_cpu_capabilities arm64_hwcaps[] = {
716 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 2, CAP_HWCAP, HWCAP_PMULL),
717 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 1, CAP_HWCAP, HWCAP_AES),
718 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 1, CAP_HWCAP, HWCAP_SHA1),
719 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 1, CAP_HWCAP, HWCAP_SHA2),
720 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 1, CAP_HWCAP, HWCAP_CRC32),
721 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 2, CAP_HWCAP, HWCAP_ATOMICS),
fe80f9f2
SP		 722 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 0, CAP_HWCAP, HWCAP_FP),
723 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 0, CAP_HWCAP, HWCAP_ASIMD),
37b01d53
SP		 724#ifdef CONFIG_COMPAT
725 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
726 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
727 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
728 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
729 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
730#endif
731 {},
732};
733
a7c61a34 734static void __init cap_set_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 735{
736 switch (cap->hwcap_type) {
737 case CAP_HWCAP:
738 elf_hwcap |= cap->hwcap;
739 break;
740#ifdef CONFIG_COMPAT
741 case CAP_COMPAT_HWCAP:
742 compat_elf_hwcap |= (u32)cap->hwcap;
743 break;
744 case CAP_COMPAT_HWCAP2:
745 compat_elf_hwcap2 |= (u32)cap->hwcap;
746 break;
747#endif
748 default:
749 WARN_ON(1);
750 break;
751 }
752}
753
754/* Check if we have a particular HWCAP enabled */
3d6d1035 755static bool __maybe_unused cpus_have_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 756{
757 bool rc;
758
759 switch (cap->hwcap_type) {
760 case CAP_HWCAP:
761 rc = (elf_hwcap & cap->hwcap) != 0;
762 break;
763#ifdef CONFIG_COMPAT
764 case CAP_COMPAT_HWCAP:
765 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
766 break;
767 case CAP_COMPAT_HWCAP2:
768 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
769 break;
770#endif
771 default:
772 WARN_ON(1);
773 rc = false;
774 }
775
776 return rc;
777}
778
a7c61a34 779static void __init setup_cpu_hwcaps(void)
37b01d53
SP		 780{
781 int i;
782 const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps;
783
644c2ae1 784 for (i = 0; hwcaps[i].matches; i++)
37b01d53
SP		 785 if (hwcaps[i].matches(&hwcaps[i]))
786 cap_set_hwcap(&hwcaps[i]);
787}
788
ce8b602c 789void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
359b7064
MZ		 790 const char *info)
791{
792 int i;
793
644c2ae1 794 for (i = 0; caps[i].matches; i++) {
359b7064
MZ		 795 if (!caps[i].matches(&caps[i]))
796 continue;
797
644c2ae1 798 if (!cpus_have_cap(caps[i].capability) && caps[i].desc)
359b7064
MZ		 799 pr_info("%s %s\n", info, caps[i].desc);
800 cpus_set_cap(caps[i].capability);
801 }
ce8b602c
SP		 802}
803
804/*
dbb4e152
SP		 805 * Run through the enabled capabilities and enable() it on all active
806 * CPUs
ce8b602c 807 */
a7c61a34
JZ		 808static void __init
809enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
ce8b602c
SP		 810{
811 int i;
1c076303 812
644c2ae1 813 for (i = 0; caps[i].matches; i++)
dbb4e152
SP		 814 if (caps[i].enable && cpus_have_cap(caps[i].capability))
815 on_each_cpu(caps[i].enable, NULL, true);
816}
817
dbb4e152
SP		 818/*
819 * Flag to indicate if we have computed the system wide
820 * capabilities based on the boot time active CPUs. This
821 * will be used to determine if a new booting CPU should
822 * go through the verification process to make sure that it
823 * supports the system capabilities, without using a hotplug
824 * notifier.
825 */
826static bool sys_caps_initialised;
827
828static inline void set_sys_caps_initialised(void)
829{
830 sys_caps_initialised = true;
831}
832
da8d02d1
SP		 833/*
834 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
835 */
836static u64 __raw_read_system_reg(u32 sys_id)
837{
838 switch (sys_id) {
0f54b14e
JM		 839 case SYS_ID_PFR0_EL1: return read_cpuid(SYS_ID_PFR0_EL1);
840 case SYS_ID_PFR1_EL1: return read_cpuid(SYS_ID_PFR1_EL1);
841 case SYS_ID_DFR0_EL1: return read_cpuid(SYS_ID_DFR0_EL1);
842 case SYS_ID_MMFR0_EL1: return read_cpuid(SYS_ID_MMFR0_EL1);
843 case SYS_ID_MMFR1_EL1: return read_cpuid(SYS_ID_MMFR1_EL1);
844 case SYS_ID_MMFR2_EL1: return read_cpuid(SYS_ID_MMFR2_EL1);
845 case SYS_ID_MMFR3_EL1: return read_cpuid(SYS_ID_MMFR3_EL1);
846 case SYS_ID_ISAR0_EL1: return read_cpuid(SYS_ID_ISAR0_EL1);
847 case SYS_ID_ISAR1_EL1: return read_cpuid(SYS_ID_ISAR1_EL1);
848 case SYS_ID_ISAR2_EL1: return read_cpuid(SYS_ID_ISAR2_EL1);
849 case SYS_ID_ISAR3_EL1: return read_cpuid(SYS_ID_ISAR3_EL1);
850 case SYS_ID_ISAR4_EL1: return read_cpuid(SYS_ID_ISAR4_EL1);
851 case SYS_ID_ISAR5_EL1: return read_cpuid(SYS_ID_ISAR4_EL1);
852 case SYS_MVFR0_EL1: return read_cpuid(SYS_MVFR0_EL1);
853 case SYS_MVFR1_EL1: return read_cpuid(SYS_MVFR1_EL1);
854 case SYS_MVFR2_EL1: return read_cpuid(SYS_MVFR2_EL1);
855
856 case SYS_ID_AA64PFR0_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1);
857 case SYS_ID_AA64PFR1_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1);
858 case SYS_ID_AA64DFR0_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1);
859 case SYS_ID_AA64DFR1_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1);
860 case SYS_ID_AA64MMFR0_EL1: return read_cpuid(SYS_ID_AA64MMFR0_EL1);
861 case SYS_ID_AA64MMFR1_EL1: return read_cpuid(SYS_ID_AA64MMFR1_EL1);
406e3087 862 case SYS_ID_AA64MMFR2_EL1: return read_cpuid(SYS_ID_AA64MMFR2_EL1);
0f54b14e
JM		 863 case SYS_ID_AA64ISAR0_EL1: return read_cpuid(SYS_ID_AA64ISAR0_EL1);
864 case SYS_ID_AA64ISAR1_EL1: return read_cpuid(SYS_ID_AA64ISAR1_EL1);
865
866 case SYS_CNTFRQ_EL0: return read_cpuid(SYS_CNTFRQ_EL0);
867 case SYS_CTR_EL0: return read_cpuid(SYS_CTR_EL0);
868 case SYS_DCZID_EL0: return read_cpuid(SYS_DCZID_EL0);
da8d02d1
SP		 869 default:
870 BUG();
871 return 0;
872 }
873}
874
dbb4e152
SP		 875/*
876 * Run through the enabled system capabilities and enable() it on this CPU.
877 * The capabilities were decided based on the available CPUs at the boot time.
878 * Any new CPU should match the system wide status of the capability. If the
879 * new CPU doesn't have a capability which the system now has enabled, we
880 * cannot do anything to fix it up and could cause unexpected failures. So
881 * we park the CPU.
882 */
883void verify_local_cpu_capabilities(void)
884{
885 int i;
886 const struct arm64_cpu_capabilities *caps;
887
888 /*
889 * If we haven't computed the system capabilities, there is nothing
890 * to verify.
891 */
892 if (!sys_caps_initialised)
893 return;
894
895 caps = arm64_features;
644c2ae1 896 for (i = 0; caps[i].matches; i++) {
da8d02d1 897 if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg)
dbb4e152
SP		 898 continue;
899 /*
900 * If the new CPU misses an advertised feature, we cannot proceed
901 * further, park the cpu.
902 */
ee02a159
SP		 903 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) {
904 pr_crit("CPU%d: missing feature: %s\n",
905 smp_processor_id(), caps[i].desc);
906 cpu_die_early();
907 }
dbb4e152
SP		 908 if (caps[i].enable)
909 caps[i].enable(NULL);
1c076303 910 }
37b01d53 911
644c2ae1 912 for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) {
37b01d53
SP		 913 if (!cpus_have_hwcap(&caps[i]))
914 continue;
ee02a159
SP		 915 if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) {
916 pr_crit("CPU%d: missing HWCAP: %s\n",
917 smp_processor_id(), caps[i].desc);
918 cpu_die_early();
919 }
37b01d53 920 }
359b7064
MZ		 921}
922
a7c61a34 923static void __init setup_feature_capabilities(void)
359b7064 924{
ce8b602c
SP		 925 update_cpu_capabilities(arm64_features, "detected feature:");
926 enable_cpu_capabilities(arm64_features);
359b7064
MZ		 927}
928
9cdf8ec4 929void __init setup_cpu_features(void)
359b7064 930{
9cdf8ec4
SP		 931 u32 cwg;
932 int cls;
933
dbb4e152
SP		 934 /* Set the CPU feature capabilies */
935 setup_feature_capabilities();
37b01d53 936 setup_cpu_hwcaps();
dbb4e152
SP		 937
938 /* Advertise that we have computed the system capabilities */
939 set_sys_caps_initialised();
940
9cdf8ec4
SP		 941 /*
942 * Check for sane CTR_EL0.CWG value.
943 */
944 cwg = cache_type_cwg();
945 cls = cache_line_size();
946 if (!cwg)
947 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
948 cls);
949 if (L1_CACHE_BYTES < cls)
950 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
951 L1_CACHE_BYTES, cls);
359b7064 952}
70544196
JM		 953
954static bool __maybe_unused
955cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry)
956{
957 return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
958}
Linux kernel - Deliverables
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