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arm/arm64: KVM: Export __hyp_text_start/end symbols
[deliverable/linux.git] / arch / arm64 / kernel / cpufeature.c
CommitLineData
359b7064
MZ		 1/*
2 * Contains CPU feature definitions
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
9cdf8ec4 19#define pr_fmt(fmt) "CPU features: " fmt
359b7064 20
3c739b57
SP		 21#include <linux/bsearch.h>
22#include <linux/sort.h>
359b7064
MZ		 23#include <linux/types.h>
24#include <asm/cpu.h>
25#include <asm/cpufeature.h>
dbb4e152 26#include <asm/cpu_ops.h>
13f417f3 27#include <asm/mmu_context.h>
338d4f49 28#include <asm/processor.h>
cdcf817b 29#include <asm/sysreg.h>
d88701be 30#include <asm/virt.h>
359b7064 31
9cdf8ec4
SP		 32unsigned long elf_hwcap __read_mostly;
33EXPORT_SYMBOL_GPL(elf_hwcap);
34
35#ifdef CONFIG_COMPAT
36#define COMPAT_ELF_HWCAP_DEFAULT \
37 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
38 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
39 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
40 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
41 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
42 COMPAT_HWCAP_LPAE)
43unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
44unsigned int compat_elf_hwcap2 __read_mostly;
45#endif
46
47DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
48
4f0a606b 49#define __ARM64_FTR_BITS(SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
3c739b57 50 { \
4f0a606b 51 .sign = SIGNED, \
3c739b57
SP		 52 .strict = STRICT, \
53 .type = TYPE, \
54 .shift = SHIFT, \
55 .width = WIDTH, \
56 .safe_val = SAFE_VAL, \
57 }
58
0710cfdb 59/* Define a feature with unsigned values */
4f0a606b 60#define ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
4f0a606b
SP		 61 __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
62
0710cfdb
SP		 63/* Define a feature with a signed value */
64#define S_ARM64_FTR_BITS(STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
65 __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
66
3c739b57
SP		 67#define ARM64_FTR_END \
68 { \
69 .width = 0, \
70 }
71
70544196
JM		 72/* meta feature for alternatives */
73static bool __maybe_unused
92406f0c
SP		 74cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
75
70544196 76
3c739b57
SP		 77static struct arm64_ftr_bits ftr_id_aa64isar0[] = {
78 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
79 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
80 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0),
81 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
82 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
83 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
84 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
85 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
86 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
87 ARM64_FTR_END,
88};
89
90static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
91 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
92 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0),
93 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
0710cfdb
SP		 94 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
95 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
3c739b57
SP		 96 /* Linux doesn't care about the EL3 */
97 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
98 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
99 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
100 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
101 ARM64_FTR_END,
102};
103
104static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
105 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
0710cfdb
SP		 106 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
107 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
3c739b57
SP		 108 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
109 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
110 /* Linux shouldn't care about secure memory */
111 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
112 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
113 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
114 /*
115 * Differing PARange is fine as long as all peripherals and memory are mapped
116 * within the minimum PARange of all CPUs
117 */
0710cfdb 118 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
3c739b57
SP		 119 ARM64_FTR_END,
120};
121
122static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
123 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
124 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
125 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
130 ARM64_FTR_END,
131};
132
406e3087 133static struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
7d7b4ae4
KW		 134 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
136 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
406e3087 137 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
7d7b4ae4 138 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
406e3087
JM		 139 ARM64_FTR_END,
140};
141
3c739b57 142static struct arm64_ftr_bits ftr_ctr[] = {
0710cfdb 143 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */
3c739b57 144 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0),
0710cfdb
SP		 145 ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
146 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */
147 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */
3c739b57
SP		 148 /*
149 * Linux can handle differing I-cache policies. Userspace JITs will
150 * make use of *minLine
151 */
0710cfdb 152 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, 14, 2, 0), /* L1Ip */
3c739b57 153 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 10, 0), /* RAZ */
0710cfdb 154 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
3c739b57
SP		 155 ARM64_FTR_END,
156};
157
158static struct arm64_ftr_bits ftr_id_mmfr0[] = {
0710cfdb 159 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0xf), /* InnerShr */
3c739b57
SP		 160 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 24, 4, 0), /* FCSE */
161 ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
162 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 4, 0), /* TCM */
163 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* ShareLvl */
0710cfdb 164 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */
3c739b57
SP		 165 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* PMSA */
166 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* VMSA */
167 ARM64_FTR_END,
168};
169
170static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
171 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0),
0710cfdb
SP		 172 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
173 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
174 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
175 S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
176 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
177 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
3c739b57
SP		 178 ARM64_FTR_END,
179};
180
181static struct arm64_ftr_bits ftr_mvfr2[] = {
182 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
183 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* FPMisc */
184 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* SIMDMisc */
185 ARM64_FTR_END,
186};
187
188static struct arm64_ftr_bits ftr_dczid[] = {
189 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 5, 27, 0), /* RAZ */
190 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
191 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
192 ARM64_FTR_END,
193};
194
195
196static struct arm64_ftr_bits ftr_id_isar5[] = {
197 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 20, 4, 0), /* RAZ */
199 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
203 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
204 ARM64_FTR_END,
205};
206
207static struct arm64_ftr_bits ftr_id_mmfr4[] = {
208 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 24, 0), /* RAZ */
209 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* ac2 */
210 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* RAZ */
211 ARM64_FTR_END,
212};
213
214static struct arm64_ftr_bits ftr_id_pfr0[] = {
215 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 16, 16, 0), /* RAZ */
216 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 12, 4, 0), /* State3 */
217 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 8, 4, 0), /* State2 */
218 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 4, 4, 0), /* State1 */
219 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 4, 0), /* State0 */
220 ARM64_FTR_END,
221};
222
e5343503
SP		 223static struct arm64_ftr_bits ftr_id_dfr0[] = {
224 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
0710cfdb 225 S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
e5343503
SP		 226 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
227 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
228 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
229 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
230 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
231 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
232 ARM64_FTR_END,
233};
234
3c739b57
SP		 235/*
236 * Common ftr bits for a 32bit register with all hidden, strict
237 * attributes, with 4bit feature fields and a default safe value of
238 * 0. Covers the following 32bit registers:
239 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
240 */
241static struct arm64_ftr_bits ftr_generic_32bits[] = {
242 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
243 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
244 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
245 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
246 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
247 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
248 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
249 ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
250 ARM64_FTR_END,
251};
252
253static struct arm64_ftr_bits ftr_generic[] = {
254 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
255 ARM64_FTR_END,
256};
257
258static struct arm64_ftr_bits ftr_generic32[] = {
259 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 32, 0),
260 ARM64_FTR_END,
261};
262
263static struct arm64_ftr_bits ftr_aa64raz[] = {
264 ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 0, 64, 0),
265 ARM64_FTR_END,
266};
267
268#define ARM64_FTR_REG(id, table) \
269 { \
270 .sys_id = id, \
271 .name = #id, \
272 .ftr_bits = &((table)[0]), \
273 }
274
275static struct arm64_ftr_reg arm64_ftr_regs[] = {
276
277 /* Op1 = 0, CRn = 0, CRm = 1 */
278 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
279 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
e5343503 280 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
3c739b57
SP		 281 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
282 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
283 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
284 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
285
286 /* Op1 = 0, CRn = 0, CRm = 2 */
287 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
288 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
289 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
290 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
291 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
292 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
293 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
294
295 /* Op1 = 0, CRn = 0, CRm = 3 */
296 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
297 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
298 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
299
300 /* Op1 = 0, CRn = 0, CRm = 4 */
301 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
302 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_aa64raz),
303
304 /* Op1 = 0, CRn = 0, CRm = 5 */
305 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
306 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_generic),
307
308 /* Op1 = 0, CRn = 0, CRm = 6 */
309 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
310 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_aa64raz),
311
312 /* Op1 = 0, CRn = 0, CRm = 7 */
313 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
314 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
406e3087 315 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
3c739b57
SP		 316
317 /* Op1 = 3, CRn = 0, CRm = 0 */
318 ARM64_FTR_REG(SYS_CTR_EL0, ftr_ctr),
319 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
320
321 /* Op1 = 3, CRn = 14, CRm = 0 */
322 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_generic32),
323};
324
325static int search_cmp_ftr_reg(const void *id, const void *regp)
326{
327 return (int)(unsigned long)id - (int)((const struct arm64_ftr_reg *)regp)->sys_id;
328}
329
330/*
331 * get_arm64_ftr_reg - Lookup a feature register entry using its
332 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
333 * ascending order of sys_id , we use binary search to find a matching
334 * entry.
335 *
336 * returns - Upon success, matching ftr_reg entry for id.
337 * - NULL on failure. It is upto the caller to decide
338 * the impact of a failure.
339 */
340static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
341{
342 return bsearch((const void *)(unsigned long)sys_id,
343 arm64_ftr_regs,
344 ARRAY_SIZE(arm64_ftr_regs),
345 sizeof(arm64_ftr_regs[0]),
346 search_cmp_ftr_reg);
347}
348
349static u64 arm64_ftr_set_value(struct arm64_ftr_bits *ftrp, s64 reg, s64 ftr_val)
350{
351 u64 mask = arm64_ftr_mask(ftrp);
352
353 reg &= ~mask;
354 reg |= (ftr_val << ftrp->shift) & mask;
355 return reg;
356}
357
358static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur)
359{
360 s64 ret = 0;
361
362 switch (ftrp->type) {
363 case FTR_EXACT:
364 ret = ftrp->safe_val;
365 break;
366 case FTR_LOWER_SAFE:
367 ret = new < cur ? new : cur;
368 break;
369 case FTR_HIGHER_SAFE:
370 ret = new > cur ? new : cur;
371 break;
372 default:
373 BUG();
374 }
375
376 return ret;
377}
378
379static int __init sort_cmp_ftr_regs(const void *a, const void *b)
380{
381 return ((const struct arm64_ftr_reg *)a)->sys_id -
382 ((const struct arm64_ftr_reg *)b)->sys_id;
383}
384
385static void __init swap_ftr_regs(void *a, void *b, int size)
386{
387 struct arm64_ftr_reg tmp = *(struct arm64_ftr_reg *)a;
388 *(struct arm64_ftr_reg *)a = *(struct arm64_ftr_reg *)b;
389 *(struct arm64_ftr_reg *)b = tmp;
390}
391
392static void __init sort_ftr_regs(void)
393{
394 /* Keep the array sorted so that we can do the binary search */
395 sort(arm64_ftr_regs,
396 ARRAY_SIZE(arm64_ftr_regs),
397 sizeof(arm64_ftr_regs[0]),
398 sort_cmp_ftr_regs,
399 swap_ftr_regs);
400}
401
402/*
403 * Initialise the CPU feature register from Boot CPU values.
404 * Also initiliases the strict_mask for the register.
405 */
406static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
407{
408 u64 val = 0;
409 u64 strict_mask = ~0x0ULL;
410 struct arm64_ftr_bits *ftrp;
411 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
412
413 BUG_ON(!reg);
414
415 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
416 s64 ftr_new = arm64_ftr_value(ftrp, new);
417
418 val = arm64_ftr_set_value(ftrp, val, ftr_new);
419 if (!ftrp->strict)
420 strict_mask &= ~arm64_ftr_mask(ftrp);
421 }
422 reg->sys_val = val;
423 reg->strict_mask = strict_mask;
424}
425
426void __init init_cpu_features(struct cpuinfo_arm64 *info)
427{
428 /* Before we start using the tables, make sure it is sorted */
429 sort_ftr_regs();
430
431 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
432 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
433 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
434 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
435 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
436 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
437 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
438 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
439 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
406e3087 440 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
3c739b57
SP		 441 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
442 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
a6dc3cd7
SP		 443
444 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
445 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
446 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
447 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
448 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
449 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
450 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
451 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
452 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
453 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
454 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
455 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
456 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
457 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
458 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
459 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
460 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
461 }
462
3c739b57
SP		 463}
464
3086d391 465static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
3c739b57
SP		 466{
467 struct arm64_ftr_bits *ftrp;
3c739b57
SP		 468
469 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
470 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
471 s64 ftr_new = arm64_ftr_value(ftrp, new);
472
473 if (ftr_cur == ftr_new)
474 continue;
475 /* Find a safe value */
476 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
477 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
478 }
479
480}
481
3086d391 482static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
cdcf817b 483{
3086d391
SP		 484 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
485
486 BUG_ON(!regp);
487 update_cpu_ftr_reg(regp, val);
488 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
489 return 0;
490 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
491 regp->name, boot, cpu, val);
492 return 1;
493}
494
495/*
496 * Update system wide CPU feature registers with the values from a
497 * non-boot CPU. Also performs SANITY checks to make sure that there
498 * aren't any insane variations from that of the boot CPU.
499 */
500void update_cpu_features(int cpu,
501 struct cpuinfo_arm64 *info,
502 struct cpuinfo_arm64 *boot)
503{
504 int taint = 0;
505
506 /*
507 * The kernel can handle differing I-cache policies, but otherwise
508 * caches should look identical. Userspace JITs will make use of
509 * *minLine.
510 */
511 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
512 info->reg_ctr, boot->reg_ctr);
513
514 /*
515 * Userspace may perform DC ZVA instructions. Mismatched block sizes
516 * could result in too much or too little memory being zeroed if a
517 * process is preempted and migrated between CPUs.
518 */
519 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
520 info->reg_dczid, boot->reg_dczid);
521
522 /* If different, timekeeping will be broken (especially with KVM) */
523 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
524 info->reg_cntfrq, boot->reg_cntfrq);
525
526 /*
527 * The kernel uses self-hosted debug features and expects CPUs to
528 * support identical debug features. We presently need CTX_CMPs, WRPs,
529 * and BRPs to be identical.
530 * ID_AA64DFR1 is currently RES0.
531 */
532 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
533 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
534 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
535 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
536 /*
537 * Even in big.LITTLE, processors should be identical instruction-set
538 * wise.
539 */
540 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
541 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
542 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
543 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
544
545 /*
546 * Differing PARange support is fine as long as all peripherals and
547 * memory are mapped within the minimum PARange of all CPUs.
548 * Linux should not care about secure memory.
549 */
550 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
551 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
552 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
553 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
406e3087
JM		 554 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
555 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
3086d391
SP		 556
557 /*
558 * EL3 is not our concern.
559 * ID_AA64PFR1 is currently RES0.
560 */
561 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
562 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
563 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
564 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
565
566 /*
a6dc3cd7
SP		 567 * If we have AArch32, we care about 32-bit features for compat.
568 * If the system doesn't support AArch32, don't update them.
3086d391 569 */
a6dc3cd7
SP		 570 if (id_aa64pfr0_32bit_el0(read_system_reg(SYS_ID_AA64PFR0_EL1)) &&
571 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
572
573 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
3086d391 574 info->reg_id_dfr0, boot->reg_id_dfr0);
a6dc3cd7 575 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
3086d391 576 info->reg_id_isar0, boot->reg_id_isar0);
a6dc3cd7 577 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
3086d391 578 info->reg_id_isar1, boot->reg_id_isar1);
a6dc3cd7 579 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
3086d391 580 info->reg_id_isar2, boot->reg_id_isar2);
a6dc3cd7 581 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
3086d391 582 info->reg_id_isar3, boot->reg_id_isar3);
a6dc3cd7 583 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
3086d391 584 info->reg_id_isar4, boot->reg_id_isar4);
a6dc3cd7 585 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
3086d391
SP		 586 info->reg_id_isar5, boot->reg_id_isar5);
587
a6dc3cd7
SP		 588 /*
589 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
590 * ACTLR formats could differ across CPUs and therefore would have to
591 * be trapped for virtualization anyway.
592 */
593 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
3086d391 594 info->reg_id_mmfr0, boot->reg_id_mmfr0);
a6dc3cd7 595 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
3086d391 596 info->reg_id_mmfr1, boot->reg_id_mmfr1);
a6dc3cd7 597 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
3086d391 598 info->reg_id_mmfr2, boot->reg_id_mmfr2);
a6dc3cd7 599 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
3086d391 600 info->reg_id_mmfr3, boot->reg_id_mmfr3);
a6dc3cd7 601 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
3086d391 602 info->reg_id_pfr0, boot->reg_id_pfr0);
a6dc3cd7 603 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
3086d391 604 info->reg_id_pfr1, boot->reg_id_pfr1);
a6dc3cd7 605 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
3086d391 606 info->reg_mvfr0, boot->reg_mvfr0);
a6dc3cd7 607 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
3086d391 608 info->reg_mvfr1, boot->reg_mvfr1);
a6dc3cd7 609 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
3086d391 610 info->reg_mvfr2, boot->reg_mvfr2);
a6dc3cd7 611 }
3086d391
SP		 612
613 /*
614 * Mismatched CPU features are a recipe for disaster. Don't even
615 * pretend to support them.
616 */
617 WARN_TAINT_ONCE(taint, TAINT_CPU_OUT_OF_SPEC,
618 "Unsupported CPU feature variation.\n");
cdcf817b
SP		 619}
620
b3f15378
SP		 621u64 read_system_reg(u32 id)
622{
623 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
624
625 /* We shouldn't get a request for an unsupported register */
626 BUG_ON(!regp);
627 return regp->sys_val;
628}
359b7064 629
92406f0c
SP		 630/*
631 * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated.
632 * Read the system register on the current CPU
633 */
634static u64 __raw_read_system_reg(u32 sys_id)
635{
636 switch (sys_id) {
637 case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1);
638 case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1);
639 case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1);
640 case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1);
641 case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1);
642 case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1);
643 case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1);
644 case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1);
645 case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1);
646 case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1);
647 case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1);
648 case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1);
649 case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR4_EL1);
650 case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1);
651 case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1);
652 case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1);
653
654 case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1);
655 case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR0_EL1);
656 case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1);
657 case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR0_EL1);
658 case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1);
659 case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1);
660 case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1);
661 case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1);
662 case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1);
663
664 case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0);
665 case SYS_CTR_EL0: return read_cpuid(CTR_EL0);
666 case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0);
667 default:
668 BUG();
669 return 0;
670 }
671}
672
963fcd40
MZ		 673#include <linux/irqchip/arm-gic-v3.h>
674
18ffa046
JM		 675static bool
676feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
677{
28c5dcb2 678 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
18ffa046
JM		 679
680 return val >= entry->min_field_value;
681}
682
da8d02d1 683static bool
92406f0c 684has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
da8d02d1
SP		 685{
686 u64 val;
94a9e04a 687
92406f0c
SP		 688 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
689 if (scope == SCOPE_SYSTEM)
690 val = read_system_reg(entry->sys_reg);
691 else
692 val = __raw_read_system_reg(entry->sys_reg);
693
da8d02d1
SP		 694 return feature_matches(val, entry);
695}
338d4f49 696
92406f0c 697static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
963fcd40
MZ		 698{
699 bool has_sre;
700
92406f0c 701 if (!has_cpuid_feature(entry, scope))
963fcd40
MZ		 702 return false;
703
704 has_sre = gic_enable_sre();
705 if (!has_sre)
706 pr_warn_once("%s present but disabled by higher exception level\n",
707 entry->desc);
708
709 return has_sre;
710}
711
92406f0c 712static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
d5370f75
WD		 713{
714 u32 midr = read_cpuid_id();
715 u32 rv_min, rv_max;
716
717 /* Cavium ThunderX pass 1.x and 2.x */
718 rv_min = 0;
719 rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK;
720
721 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
722}
723
92406f0c 724static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
d88701be
MZ		 725{
726 return is_kernel_in_hyp_mode();
727}
728
359b7064 729static const struct arm64_cpu_capabilities arm64_features[] = {
94a9e04a
MZ		 730 {
731 .desc = "GIC system register CPU interface",
732 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
92406f0c 733 .def_scope = SCOPE_SYSTEM,
963fcd40 734 .matches = has_useable_gicv3_cpuif,
da8d02d1
SP		 735 .sys_reg = SYS_ID_AA64PFR0_EL1,
736 .field_pos = ID_AA64PFR0_GIC_SHIFT,
ff96f7bc 737 .sign = FTR_UNSIGNED,
18ffa046 738 .min_field_value = 1,
94a9e04a 739 },
338d4f49
JM		 740#ifdef CONFIG_ARM64_PAN
741 {
742 .desc = "Privileged Access Never",
743 .capability = ARM64_HAS_PAN,
92406f0c 744 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP		 745 .matches = has_cpuid_feature,
746 .sys_reg = SYS_ID_AA64MMFR1_EL1,
747 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
ff96f7bc 748 .sign = FTR_UNSIGNED,
338d4f49
JM		 749 .min_field_value = 1,
750 .enable = cpu_enable_pan,
751 },
752#endif /* CONFIG_ARM64_PAN */
2e94da13
WD		 753#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
754 {
755 .desc = "LSE atomic instructions",
756 .capability = ARM64_HAS_LSE_ATOMICS,
92406f0c 757 .def_scope = SCOPE_SYSTEM,
da8d02d1
SP		 758 .matches = has_cpuid_feature,
759 .sys_reg = SYS_ID_AA64ISAR0_EL1,
760 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
ff96f7bc 761 .sign = FTR_UNSIGNED,
2e94da13
WD		 762 .min_field_value = 2,
763 },
764#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
d5370f75
WD		 765 {
766 .desc = "Software prefetching using PRFM",
767 .capability = ARM64_HAS_NO_HW_PREFETCH,
92406f0c 768 .def_scope = SCOPE_SYSTEM,
d5370f75
WD		 769 .matches = has_no_hw_prefetch,
770 },
57f4959b
JM		 771#ifdef CONFIG_ARM64_UAO
772 {
773 .desc = "User Access Override",
774 .capability = ARM64_HAS_UAO,
92406f0c 775 .def_scope = SCOPE_SYSTEM,
57f4959b
JM		 776 .matches = has_cpuid_feature,
777 .sys_reg = SYS_ID_AA64MMFR2_EL1,
778 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
779 .min_field_value = 1,
780 .enable = cpu_enable_uao,
781 },
782#endif /* CONFIG_ARM64_UAO */
70544196
JM		 783#ifdef CONFIG_ARM64_PAN
784 {
785 .capability = ARM64_ALT_PAN_NOT_UAO,
92406f0c 786 .def_scope = SCOPE_SYSTEM,
70544196
JM		 787 .matches = cpufeature_pan_not_uao,
788 },
789#endif /* CONFIG_ARM64_PAN */
d88701be
MZ		 790 {
791 .desc = "Virtualization Host Extensions",
792 .capability = ARM64_HAS_VIRT_HOST_EXTN,
92406f0c 793 .def_scope = SCOPE_SYSTEM,
d88701be
MZ		 794 .matches = runs_at_el2,
795 },
042446a3
SP		 796 {
797 .desc = "32-bit EL0 Support",
798 .capability = ARM64_HAS_32BIT_EL0,
92406f0c 799 .def_scope = SCOPE_SYSTEM,
042446a3
SP		 800 .matches = has_cpuid_feature,
801 .sys_reg = SYS_ID_AA64PFR0_EL1,
802 .sign = FTR_UNSIGNED,
803 .field_pos = ID_AA64PFR0_EL0_SHIFT,
804 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
805 },
359b7064
MZ		 806 {},
807};
808
ff96f7bc 809#define HWCAP_CAP(reg, field, s, min_value, type, cap) \
37b01d53
SP		 810 { \
811 .desc = #cap, \
92406f0c 812 .def_scope = SCOPE_SYSTEM, \
37b01d53
SP		 813 .matches = has_cpuid_feature, \
814 .sys_reg = reg, \
815 .field_pos = field, \
ff96f7bc 816 .sign = s, \
37b01d53
SP		 817 .min_field_value = min_value, \
818 .hwcap_type = type, \
819 .hwcap = cap, \
820 }
821
f3efb675 822static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
ff96f7bc
SP		 823 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
824 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
825 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
826 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
827 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
828 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
829 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
bf500618 830 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
ff96f7bc 831 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
bf500618 832 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
75283501
SP		 833 {},
834};
835
836static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
37b01d53 837#ifdef CONFIG_COMPAT
ff96f7bc
SP		 838 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
839 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
840 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
841 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
842 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
37b01d53
SP		 843#endif
844 {},
845};
846
f3efb675 847static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 848{
849 switch (cap->hwcap_type) {
850 case CAP_HWCAP:
851 elf_hwcap |= cap->hwcap;
852 break;
853#ifdef CONFIG_COMPAT
854 case CAP_COMPAT_HWCAP:
855 compat_elf_hwcap |= (u32)cap->hwcap;
856 break;
857 case CAP_COMPAT_HWCAP2:
858 compat_elf_hwcap2 |= (u32)cap->hwcap;
859 break;
860#endif
861 default:
862 WARN_ON(1);
863 break;
864 }
865}
866
867/* Check if we have a particular HWCAP enabled */
f3efb675 868static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
37b01d53
SP		 869{
870 bool rc;
871
872 switch (cap->hwcap_type) {
873 case CAP_HWCAP:
874 rc = (elf_hwcap & cap->hwcap) != 0;
875 break;
876#ifdef CONFIG_COMPAT
877 case CAP_COMPAT_HWCAP:
878 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
879 break;
880 case CAP_COMPAT_HWCAP2:
881 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
882 break;
883#endif
884 default:
885 WARN_ON(1);
886 rc = false;
887 }
888
889 return rc;
890}
891
75283501 892static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
37b01d53 893{
75283501 894 for (; hwcaps->matches; hwcaps++)
92406f0c 895 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
75283501 896 cap_set_elf_hwcap(hwcaps);
37b01d53
SP		 897}
898
ce8b602c 899void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
359b7064
MZ		 900 const char *info)
901{
75283501 902 for (; caps->matches; caps++) {
92406f0c 903 if (!caps->matches(caps, caps->def_scope))
359b7064
MZ		 904 continue;
905
75283501
SP		 906 if (!cpus_have_cap(caps->capability) && caps->desc)
907 pr_info("%s %s\n", info, caps->desc);
908 cpus_set_cap(caps->capability);
359b7064 909 }
ce8b602c
SP		 910}
911
912/*
dbb4e152
SP		 913 * Run through the enabled capabilities and enable() it on all active
914 * CPUs
ce8b602c 915 */
a7c61a34
JZ		 916static void __init
917enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
ce8b602c 918{
75283501
SP		 919 for (; caps->matches; caps++)
920 if (caps->enable && cpus_have_cap(caps->capability))
921 on_each_cpu(caps->enable, NULL, true);
dbb4e152
SP		 922}
923
dbb4e152
SP		 924/*
925 * Flag to indicate if we have computed the system wide
926 * capabilities based on the boot time active CPUs. This
927 * will be used to determine if a new booting CPU should
928 * go through the verification process to make sure that it
929 * supports the system capabilities, without using a hotplug
930 * notifier.
931 */
932static bool sys_caps_initialised;
933
934static inline void set_sys_caps_initialised(void)
935{
936 sys_caps_initialised = true;
937}
938
939/*
13f417f3
SP		 940 * Check for CPU features that are used in early boot
941 * based on the Boot CPU value.
dbb4e152 942 */
13f417f3 943static void check_early_cpu_features(void)
dbb4e152 944{
ac1ad20f 945 verify_cpu_run_el();
13f417f3 946 verify_cpu_asid_bits();
dbb4e152 947}
1c076303 948
75283501
SP		 949static void
950verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
951{
952
92406f0c
SP		 953 for (; caps->matches; caps++)
954 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 955 pr_crit("CPU%d: missing HWCAP: %s\n",
956 smp_processor_id(), caps->desc);
957 cpu_die_early();
958 }
75283501
SP		 959}
960
961static void
962verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
963{
964 for (; caps->matches; caps++) {
92406f0c 965 if (!cpus_have_cap(caps->capability))
75283501
SP		 966 continue;
967 /*
968 * If the new CPU misses an advertised feature, we cannot proceed
969 * further, park the cpu.
970 */
92406f0c 971 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
75283501
SP		 972 pr_crit("CPU%d: missing feature: %s\n",
973 smp_processor_id(), caps->desc);
974 cpu_die_early();
975 }
976 if (caps->enable)
977 caps->enable(NULL);
978 }
979}
980
dbb4e152
SP		 981/*
982 * Run through the enabled system capabilities and enable() it on this CPU.
983 * The capabilities were decided based on the available CPUs at the boot time.
984 * Any new CPU should match the system wide status of the capability. If the
985 * new CPU doesn't have a capability which the system now has enabled, we
986 * cannot do anything to fix it up and could cause unexpected failures. So
987 * we park the CPU.
988 */
989void verify_local_cpu_capabilities(void)
990{
dbb4e152 991
13f417f3
SP		 992 check_early_cpu_features();
993
dbb4e152
SP		 994 /*
995 * If we haven't computed the system capabilities, there is nothing
996 * to verify.
997 */
998 if (!sys_caps_initialised)
999 return;
1000
6a6efbb4 1001 verify_local_cpu_errata();
75283501
SP		 1002 verify_local_cpu_features(arm64_features);
1003 verify_local_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1004 if (system_supports_32bit_el0())
1005 verify_local_elf_hwcaps(compat_elf_hwcaps);
359b7064
MZ		 1006}
1007
a7c61a34 1008static void __init setup_feature_capabilities(void)
359b7064 1009{
ce8b602c
SP		 1010 update_cpu_capabilities(arm64_features, "detected feature:");
1011 enable_cpu_capabilities(arm64_features);
359b7064
MZ		 1012}
1013
e3661b12
MZ		 1014/*
1015 * Check if the current CPU has a given feature capability.
1016 * Should be called from non-preemptible context.
1017 */
1018bool this_cpu_has_cap(unsigned int cap)
1019{
1020 const struct arm64_cpu_capabilities *caps;
1021
1022 if (WARN_ON(preemptible()))
1023 return false;
1024
1025 for (caps = arm64_features; caps->desc; caps++)
1026 if (caps->capability == cap && caps->matches)
1027 return caps->matches(caps, SCOPE_LOCAL_CPU);
1028
1029 return false;
1030}
1031
9cdf8ec4 1032void __init setup_cpu_features(void)
359b7064 1033{
9cdf8ec4
SP		 1034 u32 cwg;
1035 int cls;
1036
dbb4e152
SP		 1037 /* Set the CPU feature capabilies */
1038 setup_feature_capabilities();
75283501 1039 setup_elf_hwcaps(arm64_elf_hwcaps);
643d703d
SP		 1040
1041 if (system_supports_32bit_el0())
1042 setup_elf_hwcaps(compat_elf_hwcaps);
dbb4e152
SP		 1043
1044 /* Advertise that we have computed the system capabilities */
1045 set_sys_caps_initialised();
1046
9cdf8ec4
SP		 1047 /*
1048 * Check for sane CTR_EL0.CWG value.
1049 */
1050 cwg = cache_type_cwg();
1051 cls = cache_line_size();
1052 if (!cwg)
1053 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1054 cls);
1055 if (L1_CACHE_BYTES < cls)
1056 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1057 L1_CACHE_BYTES, cls);
359b7064 1058}
70544196
JM		 1059
1060static bool __maybe_unused
92406f0c 1061cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
70544196
JM		 1062{
1063 return (cpus_have_cap(ARM64_HAS_PAN) && !cpus_have_cap(ARM64_HAS_UAO));
1064}
Linux kernel - Deliverables
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