[deliverable/linux.git] / arch / arm64 / kernel / cpuinfo.c

/*
 * Record and handle CPU attributes.
 *
 * Copyright (C) 2014 ARM Ltd.
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#include <asm/arch_timer.h>
#include <asm/cachetype.h>
#include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/cpufeature.h>

#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/preempt.h>
#include <linux/printk.h>
#include <linux/smp.h>

/*
 * In case the boot CPU is hotpluggable, we record its initial state and
 * current state separately. Certain system registers may contain different
 * values depending on configuration at or after reset.
 */
DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
static struct cpuinfo_arm64 boot_cpu_data;

static char *icache_policy_str[] = {
	[ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
	[ICACHE_POLICY_AIVIVT] = "AIVIVT",
	[ICACHE_POLICY_VIPT] = "VIPT",
	[ICACHE_POLICY_PIPT] = "PIPT",
};

unsigned long __icache_flags;

static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
{
	unsigned int cpu = smp_processor_id();
	u32 l1ip = CTR_L1IP(info->reg_ctr);

	if (l1ip != ICACHE_POLICY_PIPT) {
		/*
		 * VIPT caches are non-aliasing if the VA always equals the PA
		 * in all bit positions that are covered by the index. This is
		 * the case if the size of a way (# of sets * line size) does
		 * not exceed PAGE_SIZE.
		 */
		u32 waysize = icache_get_numsets() * icache_get_linesize();

		if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE)
			set_bit(ICACHEF_ALIASING, &__icache_flags);
	}
	if (l1ip == ICACHE_POLICY_AIVIVT)
		set_bit(ICACHEF_AIVIVT, &__icache_flags);

	pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
}

static int check_reg_mask(char *name, u64 mask, u64 boot, u64 cur, int cpu)
{
	if ((boot & mask) == (cur & mask))
		return 0;

	pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016lx, CPU%d: %#016lx\n",
		name, (unsigned long)boot, cpu, (unsigned long)cur);

	return 1;
}

#define CHECK_MASK(field, mask, boot, cur, cpu) \
	check_reg_mask(#field, mask, (boot)->reg_ ## field, (cur)->reg_ ## field, cpu)

#define CHECK(field, boot, cur, cpu) \
	CHECK_MASK(field, ~0ULL, boot, cur, cpu)

/*
 * Verify that CPUs don't have unexpected differences that will cause problems.
 */
static void cpuinfo_sanity_check(struct cpuinfo_arm64 *cur)
{
	unsigned int cpu = smp_processor_id();
	struct cpuinfo_arm64 *boot = &boot_cpu_data;
	unsigned int diff = 0;

	/*
	 * The kernel can handle differing I-cache policies, but otherwise
	 * caches should look identical. Userspace JITs will make use of
	 * *minLine.
	 */
	diff |= CHECK_MASK(ctr, 0xffff3fff, boot, cur, cpu);

	/*
	 * Userspace may perform DC ZVA instructions. Mismatched block sizes
	 * could result in too much or too little memory being zeroed if a
	 * process is preempted and migrated between CPUs.
	 */
	diff |= CHECK(dczid, boot, cur, cpu);

	/* If different, timekeeping will be broken (especially with KVM) */
	diff |= CHECK(cntfrq, boot, cur, cpu);

	/*
	 * Even in big.LITTLE, processors should be identical instruction-set
	 * wise.
	 */
	diff |= CHECK(id_aa64isar0, boot, cur, cpu);
	diff |= CHECK(id_aa64isar1, boot, cur, cpu);

	/*
	 * Differing PARange support is fine as long as all peripherals and
	 * memory are mapped within the minimum PARange of all CPUs.
	 * Linux should not care about secure memory.
	 * ID_AA64MMFR1 is currently RES0.
	 */
	diff |= CHECK_MASK(id_aa64mmfr0, 0xffffffffffff0ff0, boot, cur, cpu);
	diff |= CHECK(id_aa64mmfr1, boot, cur, cpu);

	/*
	 * EL3 is not our concern.
	 * ID_AA64PFR1 is currently RES0.
	 */
	diff |= CHECK_MASK(id_aa64pfr0, 0xffffffffffff0fff, boot, cur, cpu);
	diff |= CHECK(id_aa64pfr1, boot, cur, cpu);

	/*
	 * If we have AArch32, we care about 32-bit features for compat. These
	 * registers should be RES0 otherwise.
	 */
	diff |= CHECK(id_isar0, boot, cur, cpu);
	diff |= CHECK(id_isar1, boot, cur, cpu);
	diff |= CHECK(id_isar2, boot, cur, cpu);
	diff |= CHECK(id_isar3, boot, cur, cpu);
	diff |= CHECK(id_isar4, boot, cur, cpu);
	diff |= CHECK(id_isar5, boot, cur, cpu);
	/*
	 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
	 * ACTLR formats could differ across CPUs and therefore would have to
	 * be trapped for virtualization anyway.
	 */
	diff |= CHECK_MASK(id_mmfr0, 0xff0fffff, boot, cur, cpu);
	diff |= CHECK(id_mmfr1, boot, cur, cpu);
	diff |= CHECK(id_mmfr2, boot, cur, cpu);
	diff |= CHECK(id_mmfr3, boot, cur, cpu);
	diff |= CHECK(id_pfr0, boot, cur, cpu);
	diff |= CHECK(id_pfr1, boot, cur, cpu);

	/*
	 * Mismatched CPU features are a recipe for disaster. Don't even
	 * pretend to support them.
	 */
	WARN_TAINT_ONCE(diff, TAINT_CPU_OUT_OF_SPEC,
			"Unsupported CPU feature variation.\n");
}

static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
{
	info->reg_cntfrq = arch_timer_get_cntfrq();
	info->reg_ctr = read_cpuid_cachetype();
	info->reg_dczid = read_cpuid(DCZID_EL0);
	info->reg_midr = read_cpuid_id();

	info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
	info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
	info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
	info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
	info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);

	info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
	info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
	info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
	info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
	info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
	info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
	info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
	info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
	info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
	info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
	info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
	info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);

	cpuinfo_detect_icache_policy(info);

	check_local_cpu_errata();
}

void cpuinfo_store_cpu(void)
{
	struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
	__cpuinfo_store_cpu(info);
	cpuinfo_sanity_check(info);
}

void __init cpuinfo_store_boot_cpu(void)
{
	struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
	__cpuinfo_store_cpu(info);

	boot_cpu_data = *info;
}

u64 __attribute_const__ icache_get_ccsidr(void)
{
	u64 ccsidr;

	WARN_ON(preemptible());

	/* Select L1 I-cache and read its size ID register */
	asm("msr csselr_el1, %1; isb; mrs %0, ccsidr_el1"
	    : "=r"(ccsidr) : "r"(1L));
	return ccsidr;
}
Commit	Line	Data
df857416 MR	1	/*
	2	* Record and handle CPU attributes.
	3	*
	4	* Copyright (C) 2014 ARM Ltd.
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17	#include <asm/arch_timer.h>
	18	#include <asm/cachetype.h>
	19	#include <asm/cpu.h>
	20	#include <asm/cputype.h>
e116a375	21	#include <asm/cpufeature.h>
df857416	22
59ccc0d4	23	#include <linux/bitops.h>
80c517b0	24	#include <linux/bug.h>
df857416	25	#include <linux/init.h>
127161aa	26	#include <linux/kernel.h>
80c517b0	27	#include <linux/preempt.h>
59ccc0d4	28	#include <linux/printk.h>
df857416 MR	29	#include <linux/smp.h>
	30
	31	/*
	32	* In case the boot CPU is hotpluggable, we record its initial state and
	33	* current state separately. Certain system registers may contain different
	34	* values depending on configuration at or after reset.
	35	*/
	36	DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
	37	static struct cpuinfo_arm64 boot_cpu_data;
	38
59ccc0d4 MR	39	static char *icache_policy_str[] = {
	40	[ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
	41	[ICACHE_POLICY_AIVIVT] = "AIVIVT",
	42	[ICACHE_POLICY_VIPT] = "VIPT",
	43	[ICACHE_POLICY_PIPT] = "PIPT",
	44	};
	45
	46	unsigned long __icache_flags;
	47
	48	static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
	49	{
	50	unsigned int cpu = smp_processor_id();
	51	u32 l1ip = CTR_L1IP(info->reg_ctr);
	52
169c018d AB	53	if (l1ip != ICACHE_POLICY_PIPT) {
	54	/*
	55	* VIPT caches are non-aliasing if the VA always equals the PA
	56	* in all bit positions that are covered by the index. This is
	57	* the case if the size of a way (# of sets * line size) does
	58	* not exceed PAGE_SIZE.
	59	*/
	60	u32 waysize = icache_get_numsets() * icache_get_linesize();
	61
	62	if (l1ip != ICACHE_POLICY_VIPT \|\| waysize > PAGE_SIZE)
	63	set_bit(ICACHEF_ALIASING, &__icache_flags);
	64	}
a3a80544	65	if (l1ip == ICACHE_POLICY_AIVIVT)
59ccc0d4 MR	66	set_bit(ICACHEF_AIVIVT, &__icache_flags);
59ccc0d4 MR	67
ea171967	68	pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
59ccc0d4 MR	69	}
59ccc0d4 MR	70
127161aa MR	71	static int check_reg_mask(char *name, u64 mask, u64 boot, u64 cur, int cpu)
	72	{
	73	if ((boot & mask) == (cur & mask))
	74	return 0;
	75
	76	pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016lx, CPU%d: %#016lx\n",
	77	name, (unsigned long)boot, cpu, (unsigned long)cur);
	78
	79	return 1;
	80	}
	81
	82	#define CHECK_MASK(field, mask, boot, cur, cpu) \
	83	check_reg_mask(#field, mask, (boot)->reg_ ## field, (cur)->reg_ ## field, cpu)
	84
	85	#define CHECK(field, boot, cur, cpu) \
	86	CHECK_MASK(field, ~0ULL, boot, cur, cpu)
	87
	88	/*
	89	* Verify that CPUs don't have unexpected differences that will cause problems.
	90	*/
	91	static void cpuinfo_sanity_check(struct cpuinfo_arm64 *cur)
	92	{
	93	unsigned int cpu = smp_processor_id();
	94	struct cpuinfo_arm64 *boot = &boot_cpu_data;
	95	unsigned int diff = 0;
	96
	97	/*
	98	* The kernel can handle differing I-cache policies, but otherwise
	99	* caches should look identical. Userspace JITs will make use of
	100	* *minLine.
	101	*/
	102	diff \|= CHECK_MASK(ctr, 0xffff3fff, boot, cur, cpu);
	103
	104	/*
	105	* Userspace may perform DC ZVA instructions. Mismatched block sizes
	106	* could result in too much or too little memory being zeroed if a
	107	* process is preempted and migrated between CPUs.
	108	*/
	109	diff \|= CHECK(dczid, boot, cur, cpu);
	110
	111	/* If different, timekeeping will be broken (especially with KVM) */
	112	diff \|= CHECK(cntfrq, boot, cur, cpu);
	113
	114	/*
	115	* Even in big.LITTLE, processors should be identical instruction-set
	116	* wise.
	117	*/
	118	diff \|= CHECK(id_aa64isar0, boot, cur, cpu);
	119	diff \|= CHECK(id_aa64isar1, boot, cur, cpu);
	120
	121	/*
	122	* Differing PARange support is fine as long as all peripherals and
	123	* memory are mapped within the minimum PARange of all CPUs.
	124	* Linux should not care about secure memory.
	125	* ID_AA64MMFR1 is currently RES0.
	126	*/
	127	diff \|= CHECK_MASK(id_aa64mmfr0, 0xffffffffffff0ff0, boot, cur, cpu);
	128	diff \|= CHECK(id_aa64mmfr1, boot, cur, cpu);
	129
	130	/*
	131	* EL3 is not our concern.
	132	* ID_AA64PFR1 is currently RES0.
	133	*/
	134	diff \|= CHECK_MASK(id_aa64pfr0, 0xffffffffffff0fff, boot, cur, cpu);
135	diff \|= CHECK(id_aa64pfr1, boot, cur, cpu);
136
137	/*
138	* If we have AArch32, we care about 32-bit features for compat. These
139	* registers should be RES0 otherwise.
140	*/
141	diff \|= CHECK(id_isar0, boot, cur, cpu);
142	diff \|= CHECK(id_isar1, boot, cur, cpu);
143	diff \|= CHECK(id_isar2, boot, cur, cpu);
144	diff \|= CHECK(id_isar3, boot, cur, cpu);
145	diff \|= CHECK(id_isar4, boot, cur, cpu);
146	diff \|= CHECK(id_isar5, boot, cur, cpu);
9760270c MR	147	/*
	148	* Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
	149	* ACTLR formats could differ across CPUs and therefore would have to
	150	* be trapped for virtualization anyway.
	151	*/
	152	diff \|= CHECK_MASK(id_mmfr0, 0xff0fffff, boot, cur, cpu);
127161aa MR	153	diff \|= CHECK(id_mmfr1, boot, cur, cpu);
	154	diff \|= CHECK(id_mmfr2, boot, cur, cpu);
	155	diff \|= CHECK(id_mmfr3, boot, cur, cpu);
	156	diff \|= CHECK(id_pfr0, boot, cur, cpu);
	157	diff \|= CHECK(id_pfr1, boot, cur, cpu);
	158
	159	/*
	160	* Mismatched CPU features are a recipe for disaster. Don't even
	161	* pretend to support them.
	162	*/
	163	WARN_TAINT_ONCE(diff, TAINT_CPU_OUT_OF_SPEC,
efdf4211	164	"Unsupported CPU feature variation.\n");
127161aa MR	165	}
127161aa MR	166
df857416 MR	167	static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
	168	{
	169	info->reg_cntfrq = arch_timer_get_cntfrq();
	170	info->reg_ctr = read_cpuid_cachetype();
	171	info->reg_dczid = read_cpuid(DCZID_EL0);
	172	info->reg_midr = read_cpuid_id();
	173
	174	info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
	175	info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
	176	info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
	177	info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
	178	info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
	179	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
	180
	181	info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
	182	info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
	183	info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
	184	info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
	185	info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
	186	info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
	187	info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
	188	info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
	189	info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
	190	info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
	191	info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
	192	info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
59ccc0d4 MR	193
59ccc0d4 MR	194	cpuinfo_detect_icache_policy(info);
e116a375 AP	195
e116a375 AP	196	check_local_cpu_errata();
df857416 MR	197	}
	198
	199	void cpuinfo_store_cpu(void)
	200	{
	201	struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
	202	__cpuinfo_store_cpu(info);
127161aa	203	cpuinfo_sanity_check(info);
df857416 MR	204	}
	205
	206	void __init cpuinfo_store_boot_cpu(void)
	207	{
	208	struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
	209	__cpuinfo_store_cpu(info);
	210
	211	boot_cpu_data = *info;
	212	}
80c517b0 AB	213
	214	u64 __attribute_const__ icache_get_ccsidr(void)
	215	{
	216	u64 ccsidr;
	217
	218	WARN_ON(preemptible());
	219
	220	/* Select L1 I-cache and read its size ID register */
	221	asm("msr csselr_el1, %1; isb; mrs %0, ccsidr_el1"
	222	: "=r"(ccsidr) : "r"(1L));
	223	return ccsidr;
	224	}