Commit | Line | Data |
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478fcb2c WD |
1 | /* |
2 | * ARMv8 single-step debug support and mdscr context switching. | |
3 | * | |
4 | * Copyright (C) 2012 ARM Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: Will Deacon <will.deacon@arm.com> | |
19 | */ | |
20 | ||
21 | #include <linux/cpu.h> | |
22 | #include <linux/debugfs.h> | |
23 | #include <linux/hardirq.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/ptrace.h> | |
2dd0e8d2 | 26 | #include <linux/kprobes.h> |
478fcb2c | 27 | #include <linux/stat.h> |
1442b6ed | 28 | #include <linux/uaccess.h> |
478fcb2c | 29 | |
3085bb01 | 30 | #include <asm/cpufeature.h> |
478fcb2c | 31 | #include <asm/cputype.h> |
3085bb01 | 32 | #include <asm/debug-monitors.h> |
478fcb2c WD |
33 | #include <asm/system_misc.h> |
34 | ||
478fcb2c WD |
35 | /* Determine debug architecture. */ |
36 | u8 debug_monitors_arch(void) | |
37 | { | |
28c5dcb2 | 38 | return cpuid_feature_extract_unsigned_field(read_system_reg(SYS_ID_AA64DFR0_EL1), |
3085bb01 | 39 | ID_AA64DFR0_DEBUGVER_SHIFT); |
478fcb2c WD |
40 | } |
41 | ||
42 | /* | |
43 | * MDSCR access routines. | |
44 | */ | |
45 | static void mdscr_write(u32 mdscr) | |
46 | { | |
47 | unsigned long flags; | |
48 | local_dbg_save(flags); | |
adf75899 | 49 | write_sysreg(mdscr, mdscr_el1); |
478fcb2c WD |
50 | local_dbg_restore(flags); |
51 | } | |
44b53f67 | 52 | NOKPROBE_SYMBOL(mdscr_write); |
478fcb2c WD |
53 | |
54 | static u32 mdscr_read(void) | |
55 | { | |
adf75899 | 56 | return read_sysreg(mdscr_el1); |
478fcb2c | 57 | } |
44b53f67 | 58 | NOKPROBE_SYMBOL(mdscr_read); |
478fcb2c WD |
59 | |
60 | /* | |
61 | * Allow root to disable self-hosted debug from userspace. | |
62 | * This is useful if you want to connect an external JTAG debugger. | |
63 | */ | |
621a5f7a | 64 | static bool debug_enabled = true; |
478fcb2c WD |
65 | |
66 | static int create_debug_debugfs_entry(void) | |
67 | { | |
68 | debugfs_create_bool("debug_enabled", 0644, NULL, &debug_enabled); | |
69 | return 0; | |
70 | } | |
71 | fs_initcall(create_debug_debugfs_entry); | |
72 | ||
73 | static int __init early_debug_disable(char *buf) | |
74 | { | |
621a5f7a | 75 | debug_enabled = false; |
478fcb2c WD |
76 | return 0; |
77 | } | |
78 | ||
79 | early_param("nodebugmon", early_debug_disable); | |
80 | ||
81 | /* | |
82 | * Keep track of debug users on each core. | |
83 | * The ref counts are per-cpu so we use a local_t type. | |
84 | */ | |
1436c1aa CL |
85 | static DEFINE_PER_CPU(int, mde_ref_count); |
86 | static DEFINE_PER_CPU(int, kde_ref_count); | |
478fcb2c | 87 | |
6f883d10 | 88 | void enable_debug_monitors(enum dbg_active_el el) |
478fcb2c WD |
89 | { |
90 | u32 mdscr, enable = 0; | |
91 | ||
92 | WARN_ON(preemptible()); | |
93 | ||
1436c1aa | 94 | if (this_cpu_inc_return(mde_ref_count) == 1) |
478fcb2c WD |
95 | enable = DBG_MDSCR_MDE; |
96 | ||
97 | if (el == DBG_ACTIVE_EL1 && | |
1436c1aa | 98 | this_cpu_inc_return(kde_ref_count) == 1) |
478fcb2c WD |
99 | enable |= DBG_MDSCR_KDE; |
100 | ||
101 | if (enable && debug_enabled) { | |
102 | mdscr = mdscr_read(); | |
103 | mdscr |= enable; | |
104 | mdscr_write(mdscr); | |
105 | } | |
106 | } | |
44b53f67 | 107 | NOKPROBE_SYMBOL(enable_debug_monitors); |
478fcb2c | 108 | |
6f883d10 | 109 | void disable_debug_monitors(enum dbg_active_el el) |
478fcb2c WD |
110 | { |
111 | u32 mdscr, disable = 0; | |
112 | ||
113 | WARN_ON(preemptible()); | |
114 | ||
1436c1aa | 115 | if (this_cpu_dec_return(mde_ref_count) == 0) |
478fcb2c WD |
116 | disable = ~DBG_MDSCR_MDE; |
117 | ||
118 | if (el == DBG_ACTIVE_EL1 && | |
1436c1aa | 119 | this_cpu_dec_return(kde_ref_count) == 0) |
478fcb2c WD |
120 | disable &= ~DBG_MDSCR_KDE; |
121 | ||
122 | if (disable) { | |
123 | mdscr = mdscr_read(); | |
124 | mdscr &= disable; | |
125 | mdscr_write(mdscr); | |
126 | } | |
127 | } | |
44b53f67 | 128 | NOKPROBE_SYMBOL(disable_debug_monitors); |
478fcb2c WD |
129 | |
130 | /* | |
131 | * OS lock clearing. | |
132 | */ | |
e937dd57 | 133 | static int clear_os_lock(unsigned int cpu) |
478fcb2c | 134 | { |
adf75899 | 135 | write_sysreg(0, oslar_el1); |
e937dd57 WD |
136 | isb(); |
137 | return 0; | |
478fcb2c WD |
138 | } |
139 | ||
b8c6453a | 140 | static int debug_monitors_init(void) |
478fcb2c | 141 | { |
e937dd57 WD |
142 | return cpuhp_setup_state(CPUHP_AP_ARM64_DEBUG_MONITORS_STARTING, |
143 | "CPUHP_AP_ARM64_DEBUG_MONITORS_STARTING", | |
144 | clear_os_lock, NULL); | |
478fcb2c WD |
145 | } |
146 | postcore_initcall(debug_monitors_init); | |
147 | ||
148 | /* | |
149 | * Single step API and exception handling. | |
150 | */ | |
151 | static void set_regs_spsr_ss(struct pt_regs *regs) | |
152 | { | |
6b68e14e | 153 | regs->pstate |= DBG_SPSR_SS; |
478fcb2c | 154 | } |
44b53f67 | 155 | NOKPROBE_SYMBOL(set_regs_spsr_ss); |
478fcb2c WD |
156 | |
157 | static void clear_regs_spsr_ss(struct pt_regs *regs) | |
158 | { | |
6b68e14e | 159 | regs->pstate &= ~DBG_SPSR_SS; |
478fcb2c | 160 | } |
44b53f67 | 161 | NOKPROBE_SYMBOL(clear_regs_spsr_ss); |
478fcb2c | 162 | |
ee6214ce SP |
163 | /* EL1 Single Step Handler hooks */ |
164 | static LIST_HEAD(step_hook); | |
cf0a2543 | 165 | static DEFINE_SPINLOCK(step_hook_lock); |
ee6214ce SP |
166 | |
167 | void register_step_hook(struct step_hook *hook) | |
168 | { | |
cf0a2543 YS |
169 | spin_lock(&step_hook_lock); |
170 | list_add_rcu(&hook->node, &step_hook); | |
171 | spin_unlock(&step_hook_lock); | |
ee6214ce SP |
172 | } |
173 | ||
174 | void unregister_step_hook(struct step_hook *hook) | |
175 | { | |
cf0a2543 YS |
176 | spin_lock(&step_hook_lock); |
177 | list_del_rcu(&hook->node); | |
178 | spin_unlock(&step_hook_lock); | |
179 | synchronize_rcu(); | |
ee6214ce SP |
180 | } |
181 | ||
182 | /* | |
95485fdc | 183 | * Call registered single step handlers |
ee6214ce SP |
184 | * There is no Syndrome info to check for determining the handler. |
185 | * So we call all the registered handlers, until the right handler is | |
186 | * found which returns zero. | |
187 | */ | |
188 | static int call_step_hook(struct pt_regs *regs, unsigned int esr) | |
189 | { | |
190 | struct step_hook *hook; | |
191 | int retval = DBG_HOOK_ERROR; | |
192 | ||
cf0a2543 | 193 | rcu_read_lock(); |
ee6214ce | 194 | |
cf0a2543 | 195 | list_for_each_entry_rcu(hook, &step_hook, node) { |
ee6214ce SP |
196 | retval = hook->fn(regs, esr); |
197 | if (retval == DBG_HOOK_HANDLED) | |
198 | break; | |
199 | } | |
200 | ||
cf0a2543 | 201 | rcu_read_unlock(); |
ee6214ce SP |
202 | |
203 | return retval; | |
204 | } | |
44b53f67 | 205 | NOKPROBE_SYMBOL(call_step_hook); |
ee6214ce | 206 | |
e04a28d4 WD |
207 | static void send_user_sigtrap(int si_code) |
208 | { | |
209 | struct pt_regs *regs = current_pt_regs(); | |
210 | siginfo_t info = { | |
211 | .si_signo = SIGTRAP, | |
212 | .si_errno = 0, | |
213 | .si_code = si_code, | |
214 | .si_addr = (void __user *)instruction_pointer(regs), | |
215 | }; | |
216 | ||
217 | if (WARN_ON(!user_mode(regs))) | |
218 | return; | |
219 | ||
220 | if (interrupts_enabled(regs)) | |
221 | local_irq_enable(); | |
222 | ||
223 | force_sig_info(SIGTRAP, &info, current); | |
224 | } | |
225 | ||
478fcb2c WD |
226 | static int single_step_handler(unsigned long addr, unsigned int esr, |
227 | struct pt_regs *regs) | |
228 | { | |
478fcb2c WD |
229 | /* |
230 | * If we are stepping a pending breakpoint, call the hw_breakpoint | |
231 | * handler first. | |
232 | */ | |
233 | if (!reinstall_suspended_bps(regs)) | |
234 | return 0; | |
235 | ||
236 | if (user_mode(regs)) { | |
adeb68ef | 237 | send_user_sigtrap(TRAP_TRACE); |
478fcb2c WD |
238 | |
239 | /* | |
240 | * ptrace will disable single step unless explicitly | |
241 | * asked to re-enable it. For other clients, it makes | |
242 | * sense to leave it enabled (i.e. rewind the controls | |
243 | * to the active-not-pending state). | |
244 | */ | |
245 | user_rewind_single_step(current); | |
246 | } else { | |
2dd0e8d2 SP |
247 | #ifdef CONFIG_KPROBES |
248 | if (kprobe_single_step_handler(regs, esr) == DBG_HOOK_HANDLED) | |
249 | return 0; | |
250 | #endif | |
ee6214ce SP |
251 | if (call_step_hook(regs, esr) == DBG_HOOK_HANDLED) |
252 | return 0; | |
253 | ||
478fcb2c WD |
254 | pr_warning("Unexpected kernel single-step exception at EL1\n"); |
255 | /* | |
256 | * Re-enable stepping since we know that we will be | |
257 | * returning to regs. | |
258 | */ | |
259 | set_regs_spsr_ss(regs); | |
260 | } | |
261 | ||
262 | return 0; | |
263 | } | |
44b53f67 | 264 | NOKPROBE_SYMBOL(single_step_handler); |
478fcb2c | 265 | |
ee6214ce SP |
266 | /* |
267 | * Breakpoint handler is re-entrant as another breakpoint can | |
268 | * hit within breakpoint handler, especically in kprobes. | |
269 | * Use reader/writer locks instead of plain spinlock. | |
270 | */ | |
271 | static LIST_HEAD(break_hook); | |
62c6c61a | 272 | static DEFINE_SPINLOCK(break_hook_lock); |
ee6214ce SP |
273 | |
274 | void register_break_hook(struct break_hook *hook) | |
275 | { | |
62c6c61a YS |
276 | spin_lock(&break_hook_lock); |
277 | list_add_rcu(&hook->node, &break_hook); | |
278 | spin_unlock(&break_hook_lock); | |
ee6214ce SP |
279 | } |
280 | ||
281 | void unregister_break_hook(struct break_hook *hook) | |
282 | { | |
62c6c61a YS |
283 | spin_lock(&break_hook_lock); |
284 | list_del_rcu(&hook->node); | |
285 | spin_unlock(&break_hook_lock); | |
286 | synchronize_rcu(); | |
ee6214ce SP |
287 | } |
288 | ||
289 | static int call_break_hook(struct pt_regs *regs, unsigned int esr) | |
290 | { | |
291 | struct break_hook *hook; | |
292 | int (*fn)(struct pt_regs *regs, unsigned int esr) = NULL; | |
293 | ||
62c6c61a YS |
294 | rcu_read_lock(); |
295 | list_for_each_entry_rcu(hook, &break_hook, node) | |
ee6214ce SP |
296 | if ((esr & hook->esr_mask) == hook->esr_val) |
297 | fn = hook->fn; | |
62c6c61a | 298 | rcu_read_unlock(); |
ee6214ce SP |
299 | |
300 | return fn ? fn(regs, esr) : DBG_HOOK_ERROR; | |
301 | } | |
44b53f67 | 302 | NOKPROBE_SYMBOL(call_break_hook); |
ee6214ce | 303 | |
1442b6ed WD |
304 | static int brk_handler(unsigned long addr, unsigned int esr, |
305 | struct pt_regs *regs) | |
306 | { | |
c878e0cf | 307 | if (user_mode(regs)) { |
e04a28d4 | 308 | send_user_sigtrap(TRAP_BRKPT); |
2dd0e8d2 SP |
309 | } |
310 | #ifdef CONFIG_KPROBES | |
311 | else if ((esr & BRK64_ESR_MASK) == BRK64_ESR_KPROBES) { | |
312 | if (kprobe_breakpoint_handler(regs, esr) != DBG_HOOK_HANDLED) | |
313 | return -EFAULT; | |
314 | } | |
315 | #endif | |
316 | else if (call_break_hook(regs, esr) != DBG_HOOK_HANDLED) { | |
317 | pr_warn("Unexpected kernel BRK exception at EL1\n"); | |
1442b6ed | 318 | return -EFAULT; |
c878e0cf | 319 | } |
1442b6ed | 320 | |
1442b6ed WD |
321 | return 0; |
322 | } | |
44b53f67 | 323 | NOKPROBE_SYMBOL(brk_handler); |
1442b6ed WD |
324 | |
325 | int aarch32_break_handler(struct pt_regs *regs) | |
326 | { | |
2dacab73 ML |
327 | u32 arm_instr; |
328 | u16 thumb_instr; | |
1442b6ed WD |
329 | bool bp = false; |
330 | void __user *pc = (void __user *)instruction_pointer(regs); | |
331 | ||
332 | if (!compat_user_mode(regs)) | |
333 | return -EFAULT; | |
334 | ||
335 | if (compat_thumb_mode(regs)) { | |
336 | /* get 16-bit Thumb instruction */ | |
2dacab73 ML |
337 | get_user(thumb_instr, (u16 __user *)pc); |
338 | thumb_instr = le16_to_cpu(thumb_instr); | |
339 | if (thumb_instr == AARCH32_BREAK_THUMB2_LO) { | |
1442b6ed | 340 | /* get second half of 32-bit Thumb-2 instruction */ |
2dacab73 ML |
341 | get_user(thumb_instr, (u16 __user *)(pc + 2)); |
342 | thumb_instr = le16_to_cpu(thumb_instr); | |
343 | bp = thumb_instr == AARCH32_BREAK_THUMB2_HI; | |
1442b6ed | 344 | } else { |
2dacab73 | 345 | bp = thumb_instr == AARCH32_BREAK_THUMB; |
1442b6ed WD |
346 | } |
347 | } else { | |
348 | /* 32-bit ARM instruction */ | |
2dacab73 ML |
349 | get_user(arm_instr, (u32 __user *)pc); |
350 | arm_instr = le32_to_cpu(arm_instr); | |
351 | bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM; | |
1442b6ed WD |
352 | } |
353 | ||
354 | if (!bp) | |
355 | return -EFAULT; | |
356 | ||
e04a28d4 | 357 | send_user_sigtrap(TRAP_BRKPT); |
1442b6ed WD |
358 | return 0; |
359 | } | |
44b53f67 | 360 | NOKPROBE_SYMBOL(aarch32_break_handler); |
1442b6ed WD |
361 | |
362 | static int __init debug_traps_init(void) | |
478fcb2c WD |
363 | { |
364 | hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP, | |
adeb68ef | 365 | TRAP_TRACE, "single-step handler"); |
1442b6ed WD |
366 | hook_debug_fault_code(DBG_ESR_EVT_BRK, brk_handler, SIGTRAP, |
367 | TRAP_BRKPT, "ptrace BRK handler"); | |
478fcb2c WD |
368 | return 0; |
369 | } | |
1442b6ed | 370 | arch_initcall(debug_traps_init); |
478fcb2c WD |
371 | |
372 | /* Re-enable single step for syscall restarting. */ | |
373 | void user_rewind_single_step(struct task_struct *task) | |
374 | { | |
375 | /* | |
376 | * If single step is active for this thread, then set SPSR.SS | |
377 | * to 1 to avoid returning to the active-pending state. | |
378 | */ | |
379 | if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) | |
380 | set_regs_spsr_ss(task_pt_regs(task)); | |
381 | } | |
44b53f67 | 382 | NOKPROBE_SYMBOL(user_rewind_single_step); |
478fcb2c WD |
383 | |
384 | void user_fastforward_single_step(struct task_struct *task) | |
385 | { | |
386 | if (test_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP)) | |
387 | clear_regs_spsr_ss(task_pt_regs(task)); | |
388 | } | |
389 | ||
390 | /* Kernel API */ | |
391 | void kernel_enable_single_step(struct pt_regs *regs) | |
392 | { | |
393 | WARN_ON(!irqs_disabled()); | |
394 | set_regs_spsr_ss(regs); | |
395 | mdscr_write(mdscr_read() | DBG_MDSCR_SS); | |
396 | enable_debug_monitors(DBG_ACTIVE_EL1); | |
397 | } | |
44b53f67 | 398 | NOKPROBE_SYMBOL(kernel_enable_single_step); |
478fcb2c WD |
399 | |
400 | void kernel_disable_single_step(void) | |
401 | { | |
402 | WARN_ON(!irqs_disabled()); | |
403 | mdscr_write(mdscr_read() & ~DBG_MDSCR_SS); | |
404 | disable_debug_monitors(DBG_ACTIVE_EL1); | |
405 | } | |
44b53f67 | 406 | NOKPROBE_SYMBOL(kernel_disable_single_step); |
478fcb2c WD |
407 | |
408 | int kernel_active_single_step(void) | |
409 | { | |
410 | WARN_ON(!irqs_disabled()); | |
411 | return mdscr_read() & DBG_MDSCR_SS; | |
412 | } | |
44b53f67 | 413 | NOKPROBE_SYMBOL(kernel_active_single_step); |
478fcb2c WD |
414 | |
415 | /* ptrace API */ | |
416 | void user_enable_single_step(struct task_struct *task) | |
417 | { | |
3a402a70 WD |
418 | struct thread_info *ti = task_thread_info(task); |
419 | ||
420 | if (!test_and_set_ti_thread_flag(ti, TIF_SINGLESTEP)) | |
421 | set_regs_spsr_ss(task_pt_regs(task)); | |
478fcb2c | 422 | } |
44b53f67 | 423 | NOKPROBE_SYMBOL(user_enable_single_step); |
478fcb2c WD |
424 | |
425 | void user_disable_single_step(struct task_struct *task) | |
426 | { | |
427 | clear_ti_thread_flag(task_thread_info(task), TIF_SINGLESTEP); | |
428 | } | |
44b53f67 | 429 | NOKPROBE_SYMBOL(user_disable_single_step); |