Commit | Line | Data |
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b3901d54 CM |
1 | /* |
2 | * Based on arch/arm/kernel/process.c | |
3 | * | |
4 | * Original Copyright (C) 1995 Linus Torvalds | |
5 | * Copyright (C) 1996-2000 Russell King - Converted to ARM. | |
6 | * Copyright (C) 2012 ARM Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <stdarg.h> | |
22 | ||
fd92d4a5 | 23 | #include <linux/compat.h> |
60c0d45a | 24 | #include <linux/efi.h> |
b3901d54 CM |
25 | #include <linux/export.h> |
26 | #include <linux/sched.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/mm.h> | |
29 | #include <linux/stddef.h> | |
30 | #include <linux/unistd.h> | |
31 | #include <linux/user.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/reboot.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/kallsyms.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/cpu.h> | |
38 | #include <linux/elfcore.h> | |
39 | #include <linux/pm.h> | |
40 | #include <linux/tick.h> | |
41 | #include <linux/utsname.h> | |
42 | #include <linux/uaccess.h> | |
43 | #include <linux/random.h> | |
44 | #include <linux/hw_breakpoint.h> | |
45 | #include <linux/personality.h> | |
46 | #include <linux/notifier.h> | |
096b3224 | 47 | #include <trace/events/power.h> |
b3901d54 | 48 | |
57f4959b | 49 | #include <asm/alternative.h> |
b3901d54 CM |
50 | #include <asm/compat.h> |
51 | #include <asm/cacheflush.h> | |
ec45d1cf WD |
52 | #include <asm/fpsimd.h> |
53 | #include <asm/mmu_context.h> | |
b3901d54 CM |
54 | #include <asm/processor.h> |
55 | #include <asm/stacktrace.h> | |
b3901d54 | 56 | |
c0c264ae LA |
57 | #ifdef CONFIG_CC_STACKPROTECTOR |
58 | #include <linux/stackprotector.h> | |
59 | unsigned long __stack_chk_guard __read_mostly; | |
60 | EXPORT_SYMBOL(__stack_chk_guard); | |
61 | #endif | |
62 | ||
b3901d54 CM |
63 | /* |
64 | * Function pointers to optional machine specific functions | |
65 | */ | |
66 | void (*pm_power_off)(void); | |
67 | EXPORT_SYMBOL_GPL(pm_power_off); | |
68 | ||
b0946fc8 | 69 | void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); |
b3901d54 | 70 | |
b3901d54 CM |
71 | /* |
72 | * This is our default idle handler. | |
73 | */ | |
0087298f | 74 | void arch_cpu_idle(void) |
b3901d54 CM |
75 | { |
76 | /* | |
77 | * This should do all the clock switching and wait for interrupt | |
78 | * tricks | |
79 | */ | |
096b3224 | 80 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
6990566b NP |
81 | cpu_do_idle(); |
82 | local_irq_enable(); | |
096b3224 | 83 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
b3901d54 CM |
84 | } |
85 | ||
9327e2c6 MR |
86 | #ifdef CONFIG_HOTPLUG_CPU |
87 | void arch_cpu_idle_dead(void) | |
88 | { | |
89 | cpu_die(); | |
90 | } | |
91 | #endif | |
92 | ||
90f51a09 AK |
93 | /* |
94 | * Called by kexec, immediately prior to machine_kexec(). | |
95 | * | |
96 | * This must completely disable all secondary CPUs; simply causing those CPUs | |
97 | * to execute e.g. a RAM-based pin loop is not sufficient. This allows the | |
98 | * kexec'd kernel to use any and all RAM as it sees fit, without having to | |
99 | * avoid any code or data used by any SW CPU pin loop. The CPU hotplug | |
100 | * functionality embodied in disable_nonboot_cpus() to achieve this. | |
101 | */ | |
b3901d54 CM |
102 | void machine_shutdown(void) |
103 | { | |
90f51a09 | 104 | disable_nonboot_cpus(); |
b3901d54 CM |
105 | } |
106 | ||
90f51a09 AK |
107 | /* |
108 | * Halting simply requires that the secondary CPUs stop performing any | |
109 | * activity (executing tasks, handling interrupts). smp_send_stop() | |
110 | * achieves this. | |
111 | */ | |
b3901d54 CM |
112 | void machine_halt(void) |
113 | { | |
b9acc49e | 114 | local_irq_disable(); |
90f51a09 | 115 | smp_send_stop(); |
b3901d54 CM |
116 | while (1); |
117 | } | |
118 | ||
90f51a09 AK |
119 | /* |
120 | * Power-off simply requires that the secondary CPUs stop performing any | |
121 | * activity (executing tasks, handling interrupts). smp_send_stop() | |
122 | * achieves this. When the system power is turned off, it will take all CPUs | |
123 | * with it. | |
124 | */ | |
b3901d54 CM |
125 | void machine_power_off(void) |
126 | { | |
b9acc49e | 127 | local_irq_disable(); |
90f51a09 | 128 | smp_send_stop(); |
b3901d54 CM |
129 | if (pm_power_off) |
130 | pm_power_off(); | |
131 | } | |
132 | ||
90f51a09 AK |
133 | /* |
134 | * Restart requires that the secondary CPUs stop performing any activity | |
68234df4 | 135 | * while the primary CPU resets the system. Systems with multiple CPUs must |
90f51a09 AK |
136 | * provide a HW restart implementation, to ensure that all CPUs reset at once. |
137 | * This is required so that any code running after reset on the primary CPU | |
138 | * doesn't have to co-ordinate with other CPUs to ensure they aren't still | |
139 | * executing pre-reset code, and using RAM that the primary CPU's code wishes | |
140 | * to use. Implementing such co-ordination would be essentially impossible. | |
141 | */ | |
b3901d54 CM |
142 | void machine_restart(char *cmd) |
143 | { | |
b3901d54 CM |
144 | /* Disable interrupts first */ |
145 | local_irq_disable(); | |
b9acc49e | 146 | smp_send_stop(); |
b3901d54 | 147 | |
60c0d45a AB |
148 | /* |
149 | * UpdateCapsule() depends on the system being reset via | |
150 | * ResetSystem(). | |
151 | */ | |
152 | if (efi_enabled(EFI_RUNTIME_SERVICES)) | |
153 | efi_reboot(reboot_mode, NULL); | |
154 | ||
b3901d54 | 155 | /* Now call the architecture specific reboot code. */ |
aa1e8ec1 | 156 | if (arm_pm_restart) |
ff701306 | 157 | arm_pm_restart(reboot_mode, cmd); |
1c7ffc32 GR |
158 | else |
159 | do_kernel_restart(cmd); | |
b3901d54 CM |
160 | |
161 | /* | |
162 | * Whoops - the architecture was unable to reboot. | |
163 | */ | |
164 | printk("Reboot failed -- System halted\n"); | |
165 | while (1); | |
166 | } | |
167 | ||
168 | void __show_regs(struct pt_regs *regs) | |
169 | { | |
6ca68e80 CM |
170 | int i, top_reg; |
171 | u64 lr, sp; | |
172 | ||
173 | if (compat_user_mode(regs)) { | |
174 | lr = regs->compat_lr; | |
175 | sp = regs->compat_sp; | |
176 | top_reg = 12; | |
177 | } else { | |
178 | lr = regs->regs[30]; | |
179 | sp = regs->sp; | |
180 | top_reg = 29; | |
181 | } | |
b3901d54 | 182 | |
a43cb95d | 183 | show_regs_print_info(KERN_DEFAULT); |
b3901d54 | 184 | print_symbol("PC is at %s\n", instruction_pointer(regs)); |
6ca68e80 | 185 | print_symbol("LR is at %s\n", lr); |
b3901d54 | 186 | printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n", |
6ca68e80 CM |
187 | regs->pc, lr, regs->pstate); |
188 | printk("sp : %016llx\n", sp); | |
189 | for (i = top_reg; i >= 0; i--) { | |
b3901d54 CM |
190 | printk("x%-2d: %016llx ", i, regs->regs[i]); |
191 | if (i % 2 == 0) | |
192 | printk("\n"); | |
193 | } | |
194 | printk("\n"); | |
195 | } | |
196 | ||
197 | void show_regs(struct pt_regs * regs) | |
198 | { | |
199 | printk("\n"); | |
b3901d54 CM |
200 | __show_regs(regs); |
201 | } | |
202 | ||
eb35bdd7 WD |
203 | static void tls_thread_flush(void) |
204 | { | |
205 | asm ("msr tpidr_el0, xzr"); | |
206 | ||
207 | if (is_compat_task()) { | |
208 | current->thread.tp_value = 0; | |
209 | ||
210 | /* | |
211 | * We need to ensure ordering between the shadow state and the | |
212 | * hardware state, so that we don't corrupt the hardware state | |
213 | * with a stale shadow state during context switch. | |
214 | */ | |
215 | barrier(); | |
216 | asm ("msr tpidrro_el0, xzr"); | |
217 | } | |
218 | } | |
219 | ||
b3901d54 CM |
220 | void flush_thread(void) |
221 | { | |
222 | fpsimd_flush_thread(); | |
eb35bdd7 | 223 | tls_thread_flush(); |
b3901d54 CM |
224 | flush_ptrace_hw_breakpoint(current); |
225 | } | |
226 | ||
227 | void release_thread(struct task_struct *dead_task) | |
228 | { | |
229 | } | |
230 | ||
231 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) | |
232 | { | |
6eb6c801 JL |
233 | if (current->mm) |
234 | fpsimd_preserve_current_state(); | |
b3901d54 CM |
235 | *dst = *src; |
236 | return 0; | |
237 | } | |
238 | ||
239 | asmlinkage void ret_from_fork(void) asm("ret_from_fork"); | |
240 | ||
241 | int copy_thread(unsigned long clone_flags, unsigned long stack_start, | |
afa86fc4 | 242 | unsigned long stk_sz, struct task_struct *p) |
b3901d54 CM |
243 | { |
244 | struct pt_regs *childregs = task_pt_regs(p); | |
b3901d54 | 245 | |
c34501d2 | 246 | memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context)); |
b3901d54 | 247 | |
9ac08002 AV |
248 | if (likely(!(p->flags & PF_KTHREAD))) { |
249 | *childregs = *current_pt_regs(); | |
c34501d2 | 250 | childregs->regs[0] = 0; |
d00a3810 WD |
251 | |
252 | /* | |
253 | * Read the current TLS pointer from tpidr_el0 as it may be | |
254 | * out-of-sync with the saved value. | |
255 | */ | |
256 | asm("mrs %0, tpidr_el0" : "=r" (*task_user_tls(p))); | |
257 | ||
258 | if (stack_start) { | |
259 | if (is_compat_thread(task_thread_info(p))) | |
e0fd18ce | 260 | childregs->compat_sp = stack_start; |
d00a3810 | 261 | else |
e0fd18ce | 262 | childregs->sp = stack_start; |
c34501d2 | 263 | } |
d00a3810 | 264 | |
b3901d54 | 265 | /* |
c34501d2 CM |
266 | * If a TLS pointer was passed to clone (4th argument), use it |
267 | * for the new thread. | |
b3901d54 | 268 | */ |
c34501d2 | 269 | if (clone_flags & CLONE_SETTLS) |
d00a3810 | 270 | p->thread.tp_value = childregs->regs[3]; |
c34501d2 CM |
271 | } else { |
272 | memset(childregs, 0, sizeof(struct pt_regs)); | |
273 | childregs->pstate = PSR_MODE_EL1h; | |
57f4959b JM |
274 | if (IS_ENABLED(CONFIG_ARM64_UAO) && |
275 | cpus_have_cap(ARM64_HAS_UAO)) | |
276 | childregs->pstate |= PSR_UAO_BIT; | |
c34501d2 CM |
277 | p->thread.cpu_context.x19 = stack_start; |
278 | p->thread.cpu_context.x20 = stk_sz; | |
b3901d54 | 279 | } |
b3901d54 | 280 | p->thread.cpu_context.pc = (unsigned long)ret_from_fork; |
c34501d2 | 281 | p->thread.cpu_context.sp = (unsigned long)childregs; |
b3901d54 CM |
282 | |
283 | ptrace_hw_copy_thread(p); | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | static void tls_thread_switch(struct task_struct *next) | |
289 | { | |
290 | unsigned long tpidr, tpidrro; | |
291 | ||
d00a3810 WD |
292 | asm("mrs %0, tpidr_el0" : "=r" (tpidr)); |
293 | *task_user_tls(current) = tpidr; | |
b3901d54 | 294 | |
d00a3810 WD |
295 | tpidr = *task_user_tls(next); |
296 | tpidrro = is_compat_thread(task_thread_info(next)) ? | |
297 | next->thread.tp_value : 0; | |
b3901d54 CM |
298 | |
299 | asm( | |
300 | " msr tpidr_el0, %0\n" | |
301 | " msr tpidrro_el0, %1" | |
302 | : : "r" (tpidr), "r" (tpidrro)); | |
303 | } | |
304 | ||
57f4959b JM |
305 | /* Restore the UAO state depending on next's addr_limit */ |
306 | static void uao_thread_switch(struct task_struct *next) | |
307 | { | |
e950631e CM |
308 | if (IS_ENABLED(CONFIG_ARM64_UAO)) { |
309 | if (task_thread_info(next)->addr_limit == KERNEL_DS) | |
310 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO)); | |
311 | else | |
312 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO)); | |
313 | } | |
57f4959b JM |
314 | } |
315 | ||
b3901d54 CM |
316 | /* |
317 | * Thread switching. | |
318 | */ | |
319 | struct task_struct *__switch_to(struct task_struct *prev, | |
320 | struct task_struct *next) | |
321 | { | |
322 | struct task_struct *last; | |
323 | ||
324 | fpsimd_thread_switch(next); | |
325 | tls_thread_switch(next); | |
326 | hw_breakpoint_thread_switch(next); | |
3325732f | 327 | contextidr_thread_switch(next); |
57f4959b | 328 | uao_thread_switch(next); |
b3901d54 | 329 | |
5108c67c CM |
330 | /* |
331 | * Complete any pending TLB or cache maintenance on this CPU in case | |
332 | * the thread migrates to a different CPU. | |
333 | */ | |
98f7685e | 334 | dsb(ish); |
b3901d54 CM |
335 | |
336 | /* the actual thread switch */ | |
337 | last = cpu_switch_to(prev, next); | |
338 | ||
339 | return last; | |
340 | } | |
341 | ||
b3901d54 CM |
342 | unsigned long get_wchan(struct task_struct *p) |
343 | { | |
344 | struct stackframe frame; | |
408c3658 | 345 | unsigned long stack_page; |
b3901d54 CM |
346 | int count = 0; |
347 | if (!p || p == current || p->state == TASK_RUNNING) | |
348 | return 0; | |
349 | ||
350 | frame.fp = thread_saved_fp(p); | |
351 | frame.sp = thread_saved_sp(p); | |
352 | frame.pc = thread_saved_pc(p); | |
20380bb3 AT |
353 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
354 | frame.graph = p->curr_ret_stack; | |
355 | #endif | |
408c3658 | 356 | stack_page = (unsigned long)task_stack_page(p); |
b3901d54 | 357 | do { |
408c3658 KK |
358 | if (frame.sp < stack_page || |
359 | frame.sp >= stack_page + THREAD_SIZE || | |
fe13f95b | 360 | unwind_frame(p, &frame)) |
b3901d54 CM |
361 | return 0; |
362 | if (!in_sched_functions(frame.pc)) | |
363 | return frame.pc; | |
364 | } while (count ++ < 16); | |
365 | return 0; | |
366 | } | |
367 | ||
368 | unsigned long arch_align_stack(unsigned long sp) | |
369 | { | |
370 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
371 | sp -= get_random_int() & ~PAGE_MASK; | |
372 | return sp & ~0xf; | |
373 | } | |
374 | ||
b3901d54 CM |
375 | unsigned long arch_randomize_brk(struct mm_struct *mm) |
376 | { | |
61462c8a KC |
377 | unsigned long range_end = mm->brk; |
378 | ||
379 | if (is_compat_task()) | |
380 | range_end += 0x02000000; | |
381 | else | |
382 | range_end += 0x40000000; | |
383 | ||
384 | return randomize_range(mm->brk, range_end, 0) ? : mm->brk; | |
b3901d54 | 385 | } |