[deliverable/linux.git] / arch / arm64 / kernel / setup.c

/*
 * Based on arch/arm/kernel/setup.c
 *
 * Copyright (C) 1995-2001 Russell King
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/utsname.h>
#include <linux/initrd.h>
#include <linux/console.h>
#include <linux/cache.h>
#include <linux/bootmem.h>
#include <linux/seq_file.h>
#include <linux/screen_info.h>
#include <linux/init.h>
#include <linux/kexec.h>
#include <linux/crash_dump.h>
#include <linux/root_dev.h>
#include <linux/clk-provider.h>
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <linux/fs.h>
#include <linux/proc_fs.h>
#include <linux/memblock.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <linux/efi.h>

#include <asm/fixmap.h>
#include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/elf.h>
#include <asm/cputable.h>
#include <asm/cpu_ops.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/smp_plat.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/traps.h>
#include <asm/memblock.h>
#include <asm/psci.h>
#include <asm/efi.h>

unsigned int processor_id;
EXPORT_SYMBOL(processor_id);

unsigned long elf_hwcap __read_mostly;
EXPORT_SYMBOL_GPL(elf_hwcap);

#ifdef CONFIG_COMPAT
#define COMPAT_ELF_HWCAP_DEFAULT	\
				(COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
				 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
				 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
				 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
				 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
unsigned int compat_elf_hwcap2 __read_mostly;
#endif

static const char *cpu_name;
static const char *machine_name;
phys_addr_t __fdt_pointer __initdata;

/*
 * Standard memory resources
 */
static struct resource mem_res[] = {
	{
		.name = "Kernel code",
		.start = 0,
		.end = 0,
		.flags = IORESOURCE_MEM
	},
	{
		.name = "Kernel data",
		.start = 0,
		.end = 0,
		.flags = IORESOURCE_MEM
	}
};

#define kernel_code mem_res[0]
#define kernel_data mem_res[1]

void __init early_print(const char *str, ...)
{
	char buf[256];
	va_list ap;

	va_start(ap, str);
	vsnprintf(buf, sizeof(buf), str, ap);
	va_end(ap);

	printk("%s", buf);
}

void __init smp_setup_processor_id(void)
{
	u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
	cpu_logical_map(0) = mpidr;

	/*
	 * clear __my_cpu_offset on boot CPU to avoid hang caused by
	 * using percpu variable early, for example, lockdep will
	 * access percpu variable inside lock_release
	 */
	set_my_cpu_offset(0);
	pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr);
}

bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
{
	return phys_id == cpu_logical_map(cpu);
}

struct mpidr_hash mpidr_hash;
#ifdef CONFIG_SMP
/**
 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
 *			  level in order to build a linear index from an
 *			  MPIDR value. Resulting algorithm is a collision
 *			  free hash carried out through shifting and ORing
 */
static void __init smp_build_mpidr_hash(void)
{
	u32 i, affinity, fs[4], bits[4], ls;
	u64 mask = 0;
	/*
	 * Pre-scan the list of MPIDRS and filter out bits that do
	 * not contribute to affinity levels, ie they never toggle.
	 */
	for_each_possible_cpu(i)
		mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
	pr_debug("mask of set bits %#llx\n", mask);
	/*
	 * Find and stash the last and first bit set at all affinity levels to
	 * check how many bits are required to represent them.
	 */
	for (i = 0; i < 4; i++) {
		affinity = MPIDR_AFFINITY_LEVEL(mask, i);
		/*
		 * Find the MSB bit and LSB bits position
		 * to determine how many bits are required
		 * to express the affinity level.
		 */
		ls = fls(affinity);
		fs[i] = affinity ? ffs(affinity) - 1 : 0;
		bits[i] = ls - fs[i];
	}
	/*
	 * An index can be created from the MPIDR_EL1 by isolating the
	 * significant bits at each affinity level and by shifting
	 * them in order to compress the 32 bits values space to a
	 * compressed set of values. This is equivalent to hashing
	 * the MPIDR_EL1 through shifting and ORing. It is a collision free
	 * hash though not minimal since some levels might contain a number
	 * of CPUs that is not an exact power of 2 and their bit
	 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
	 */
	mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
	mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
	mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
						(bits[1] + bits[0]);
	mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
				  fs[3] - (bits[2] + bits[1] + bits[0]);
	mpidr_hash.mask = mask;
	mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
	pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
		mpidr_hash.shift_aff[0],
		mpidr_hash.shift_aff[1],
		mpidr_hash.shift_aff[2],
		mpidr_hash.shift_aff[3],
		mpidr_hash.mask,
		mpidr_hash.bits);
	/*
	 * 4x is an arbitrary value used to warn on a hash table much bigger
	 * than expected on most systems.
	 */
	if (mpidr_hash_size() > 4 * num_possible_cpus())
		pr_warn("Large number of MPIDR hash buckets detected\n");
	__flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
}
#endif

static void __init setup_processor(void)
{
	struct cpu_info *cpu_info;
	u64 features, block;
	u32 cwg;
	int cls;

	cpu_info = lookup_processor_type(read_cpuid_id());
	if (!cpu_info) {
		printk("CPU configuration botched (ID %08x), unable to continue.\n",
		       read_cpuid_id());
		while (1);
	}

	cpu_name = cpu_info->cpu_name;

	printk("CPU: %s [%08x] revision %d\n",
	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15);

	sprintf(init_utsname()->machine, ELF_PLATFORM);
	elf_hwcap = 0;

	cpuinfo_store_boot_cpu();

	/*
	 * Check for sane CTR_EL0.CWG value.
	 */
	cwg = cache_type_cwg();
	cls = cache_line_size();
	if (!cwg)
		pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
			cls);
	if (L1_CACHE_BYTES < cls)
		pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
			L1_CACHE_BYTES, cls);

	/*
	 * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
	 * The blocks we test below represent incremental functionality
	 * for non-negative values. Negative values are reserved.
	 */
	features = read_cpuid(ID_AA64ISAR0_EL1);
	block = (features >> 4) & 0xf;
	if (!(block & 0x8)) {
		switch (block) {
		default:
		case 2:
			elf_hwcap |= HWCAP_PMULL;
		case 1:
			elf_hwcap |= HWCAP_AES;
		case 0:
			break;
		}
	}

	block = (features >> 8) & 0xf;
	if (block && !(block & 0x8))
		elf_hwcap |= HWCAP_SHA1;

	block = (features >> 12) & 0xf;
	if (block && !(block & 0x8))
		elf_hwcap |= HWCAP_SHA2;

	block = (features >> 16) & 0xf;
	if (block && !(block & 0x8))
		elf_hwcap |= HWCAP_CRC32;

#ifdef CONFIG_COMPAT
	/*
	 * ID_ISAR5_EL1 carries similar information as above, but pertaining to
	 * the Aarch32 32-bit execution state.
	 */
	features = read_cpuid(ID_ISAR5_EL1);
	block = (features >> 4) & 0xf;
	if (!(block & 0x8)) {
		switch (block) {
		default:
		case 2:
			compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
		case 1:
			compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
		case 0:
			break;
		}
	}

	block = (features >> 8) & 0xf;
	if (block && !(block & 0x8))
		compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;

	block = (features >> 12) & 0xf;
	if (block && !(block & 0x8))
		compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;

	block = (features >> 16) & 0xf;
	if (block && !(block & 0x8))
		compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
#endif
}

static void __init setup_machine_fdt(phys_addr_t dt_phys)
{
	if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
		early_print("\n"
			"Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
			"The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
			"\nPlease check your bootloader.\n",
			dt_phys, phys_to_virt(dt_phys));

		while (true)
			cpu_relax();
	}

	machine_name = of_flat_dt_get_machine_name();
	dump_stack_set_arch_desc("%s (DT)", machine_name);
}

/*
 * Limit the memory size that was specified via FDT.
 */
static int __init early_mem(char *p)
{
	phys_addr_t limit;

	if (!p)
		return 1;

	limit = memparse(p, &p) & PAGE_MASK;
	pr_notice("Memory limited to %lldMB\n", limit >> 20);

	memblock_enforce_memory_limit(limit);

	return 0;
}
early_param("mem", early_mem);

static void __init request_standard_resources(void)
{
	struct memblock_region *region;
	struct resource *res;

	kernel_code.start   = virt_to_phys(_text);
	kernel_code.end     = virt_to_phys(_etext - 1);
	kernel_data.start   = virt_to_phys(_sdata);
	kernel_data.end     = virt_to_phys(_end - 1);

	for_each_memblock(memory, region) {
		res = alloc_bootmem_low(sizeof(*res));
		res->name  = "System RAM";
		res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
		res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
		res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;

		request_resource(&iomem_resource, res);

		if (kernel_code.start >= res->start &&
		    kernel_code.end <= res->end)
			request_resource(res, &kernel_code);
		if (kernel_data.start >= res->start &&
		    kernel_data.end <= res->end)
			request_resource(res, &kernel_data);
	}
}

u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };

void __init setup_arch(char **cmdline_p)
{
	setup_processor();

	setup_machine_fdt(__fdt_pointer);

	init_mm.start_code = (unsigned long) _text;
	init_mm.end_code   = (unsigned long) _etext;
	init_mm.end_data   = (unsigned long) _edata;
	init_mm.brk	   = (unsigned long) _end;

	*cmdline_p = boot_command_line;

	early_ioremap_init();

	parse_early_param();

	/*
	 *  Unmask asynchronous aborts after bringing up possible earlycon.
	 * (Report possible System Errors once we can report this occurred)
	 */
	local_async_enable();

	efi_init();
	arm64_memblock_init();

	paging_init();
	request_standard_resources();

	efi_idmap_init();

	unflatten_device_tree();

	psci_init();

	cpu_read_bootcpu_ops();
#ifdef CONFIG_SMP
	smp_init_cpus();
	smp_build_mpidr_hash();
#endif

#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
	conswitchp = &vga_con;
#elif defined(CONFIG_DUMMY_CONSOLE)
	conswitchp = &dummy_con;
#endif
#endif
}

static int __init arm64_device_init(void)
{
	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
	return 0;
}
arch_initcall_sync(arm64_device_init);

static int __init topology_init(void)
{
	int i;

	for_each_possible_cpu(i) {
		struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
		cpu->hotpluggable = 1;
		register_cpu(cpu, i);
	}

	return 0;
}
subsys_initcall(topology_init);

static const char *hwcap_str[] = {
	"fp",
	"asimd",
	"evtstrm",
	"aes",
	"pmull",
	"sha1",
	"sha2",
	"crc32",
	NULL
};

static int c_show(struct seq_file *m, void *v)
{
	int i;

	seq_printf(m, "Processor\t: %s rev %d (%s)\n",
		   cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);

	for_each_online_cpu(i) {
		/*
		 * glibc reads /proc/cpuinfo to determine the number of
		 * online processors, looking for lines beginning with
		 * "processor".  Give glibc what it expects.
		 */
#ifdef CONFIG_SMP
		seq_printf(m, "processor\t: %d\n", i);
#endif
	}

	/* dump out the processor features */
	seq_puts(m, "Features\t: ");

	for (i = 0; hwcap_str[i]; i++)
		if (elf_hwcap & (1 << i))
			seq_printf(m, "%s ", hwcap_str[i]);

	seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
	seq_printf(m, "CPU architecture: AArch64\n");
	seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
	seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
	seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);

	seq_puts(m, "\n");

	seq_printf(m, "Hardware\t: %s\n", machine_name);

	return 0;
}

static void *c_start(struct seq_file *m, loff_t *pos)
{
	return *pos < 1 ? (void *)1 : NULL;
}

static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
	++*pos;
	return NULL;
}

static void c_stop(struct seq_file *m, void *v)
{
}

const struct seq_operations cpuinfo_op = {
	.start	= c_start,
	.next	= c_next,
	.stop	= c_stop,
	.show	= c_show
};
Commit	Line	Data
9703d9d7 CM	1	/*
	2	* Based on arch/arm/kernel/setup.c
	3	*
	4	* Copyright (C) 1995-2001 Russell King
	5	* Copyright (C) 2012 ARM Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/export.h>
	21	#include <linux/kernel.h>
	22	#include <linux/stddef.h>
	23	#include <linux/ioport.h>
	24	#include <linux/delay.h>
	25	#include <linux/utsname.h>
	26	#include <linux/initrd.h>
	27	#include <linux/console.h>
a41dc0e8	28	#include <linux/cache.h>
9703d9d7 CM	29	#include <linux/bootmem.h>
	30	#include <linux/seq_file.h>
	31	#include <linux/screen_info.h>
	32	#include <linux/init.h>
	33	#include <linux/kexec.h>
	34	#include <linux/crash_dump.h>
	35	#include <linux/root_dev.h>
de79a64d	36	#include <linux/clk-provider.h>
9703d9d7 CM	37	#include <linux/cpu.h>
	38	#include <linux/interrupt.h>
	39	#include <linux/smp.h>
	40	#include <linux/fs.h>
	41	#include <linux/proc_fs.h>
	42	#include <linux/memblock.h>
	43	#include <linux/of_fdt.h>
d6bafb9b	44	#include <linux/of_platform.h>
f84d0275	45	#include <linux/efi.h>
9703d9d7	46
bf4b558e	47	#include <asm/fixmap.h>
df857416	48	#include <asm/cpu.h>
9703d9d7 CM	49	#include <asm/cputype.h>
	50	#include <asm/elf.h>
	51	#include <asm/cputable.h>
e8765b26	52	#include <asm/cpu_ops.h>
9703d9d7 CM	53	#include <asm/sections.h>
9703d9d7 CM	54	#include <asm/setup.h>
4c7aa002	55	#include <asm/smp_plat.h>
9703d9d7 CM	56	#include <asm/cacheflush.h>
	57	#include <asm/tlbflush.h>
	58	#include <asm/traps.h>
	59	#include <asm/memblock.h>
e790f1de	60	#include <asm/psci.h>
f84d0275	61	#include <asm/efi.h>
9703d9d7 CM	62
	63	unsigned int processor_id;
	64	EXPORT_SYMBOL(processor_id);
	65
25804e6a	66	unsigned long elf_hwcap __read_mostly;
9703d9d7 CM	67	EXPORT_SYMBOL_GPL(elf_hwcap);
9703d9d7 CM	68
46efe547 SK	69	#ifdef CONFIG_COMPAT
	70	#define COMPAT_ELF_HWCAP_DEFAULT \
	71	(COMPAT_HWCAP_HALF\|COMPAT_HWCAP_THUMB\|\
	72	COMPAT_HWCAP_FAST_MULT\|COMPAT_HWCAP_EDSP\|\
	73	COMPAT_HWCAP_TLS\|COMPAT_HWCAP_VFP\|\
	74	COMPAT_HWCAP_VFPv3\|COMPAT_HWCAP_VFPv4\|\
	75	COMPAT_HWCAP_NEON\|COMPAT_HWCAP_IDIV)
	76	unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
28964d32	77	unsigned int compat_elf_hwcap2 __read_mostly;
46efe547 SK	78	#endif
46efe547 SK	79
9703d9d7	80	static const char *cpu_name;
5e39977e	81	static const char *machine_name;
9703d9d7 CM	82	phys_addr_t __fdt_pointer __initdata;
	83
	84	/*
	85	* Standard memory resources
	86	*/
	87	static struct resource mem_res[] = {
	88	{
	89	.name = "Kernel code",
	90	.start = 0,
	91	.end = 0,
	92	.flags = IORESOURCE_MEM
	93	},
	94	{
	95	.name = "Kernel data",
	96	.start = 0,
	97	.end = 0,
	98	.flags = IORESOURCE_MEM
	99	}
	100	};
	101
	102	#define kernel_code mem_res[0]
	103	#define kernel_data mem_res[1]
	104
	105	void __init early_print(const char *str, ...)
	106	{
	107	char buf[256];
	108	va_list ap;
	109
	110	va_start(ap, str);
	111	vsnprintf(buf, sizeof(buf), str, ap);
	112	va_end(ap);
	113
	114	printk("%s", buf);
	115	}
	116
71586276 WD	117	void __init smp_setup_processor_id(void)
71586276 WD	118	{
80708677 MR	119	u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
	120	cpu_logical_map(0) = mpidr;
	121
71586276 WD	122	/*
	123	* clear __my_cpu_offset on boot CPU to avoid hang caused by
	124	* using percpu variable early, for example, lockdep will
	125	* access percpu variable inside lock_release
	126	*/
	127	set_my_cpu_offset(0);
80708677	128	pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr);
71586276 WD	129	}
71586276 WD	130
6e15d0e0 SK	131	bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
	132	{
	133	return phys_id == cpu_logical_map(cpu);
	134	}
	135
976d7d3f LP	136	struct mpidr_hash mpidr_hash;
	137	#ifdef CONFIG_SMP
	138	/**
	139	* smp_build_mpidr_hash - Pre-compute shifts required at each affinity
	140	* level in order to build a linear index from an
	141	* MPIDR value. Resulting algorithm is a collision
	142	* free hash carried out through shifting and ORing
	143	*/
	144	static void __init smp_build_mpidr_hash(void)
	145	{
	146	u32 i, affinity, fs[4], bits[4], ls;
	147	u64 mask = 0;
	148	/*
	149	* Pre-scan the list of MPIDRS and filter out bits that do
	150	* not contribute to affinity levels, ie they never toggle.
	151	*/
	152	for_each_possible_cpu(i)
	153	mask \|= (cpu_logical_map(i) ^ cpu_logical_map(0));
	154	pr_debug("mask of set bits %#llx\n", mask);
	155	/*
	156	* Find and stash the last and first bit set at all affinity levels to
	157	* check how many bits are required to represent them.
	158	*/
	159	for (i = 0; i < 4; i++) {
	160	affinity = MPIDR_AFFINITY_LEVEL(mask, i);
	161	/*
	162	* Find the MSB bit and LSB bits position
	163	* to determine how many bits are required
	164	* to express the affinity level.
	165	*/
	166	ls = fls(affinity);
	167	fs[i] = affinity ? ffs(affinity) - 1 : 0;
	168	bits[i] = ls - fs[i];
	169	}
	170	/*
	171	* An index can be created from the MPIDR_EL1 by isolating the
	172	* significant bits at each affinity level and by shifting
	173	* them in order to compress the 32 bits values space to a
	174	* compressed set of values. This is equivalent to hashing
	175	* the MPIDR_EL1 through shifting and ORing. It is a collision free
	176	* hash though not minimal since some levels might contain a number
	177	* of CPUs that is not an exact power of 2 and their bit
	178	* representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
	179	*/
	180	mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
	181	mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
	182	mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
	183	(bits[1] + bits[0]);
	184	mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
	185	fs[3] - (bits[2] + bits[1] + bits[0]);
	186	mpidr_hash.mask = mask;
	187	mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
	188	pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
	189	mpidr_hash.shift_aff[0],
	190	mpidr_hash.shift_aff[1],
	191	mpidr_hash.shift_aff[2],
	192	mpidr_hash.shift_aff[3],
	193	mpidr_hash.mask,
	194	mpidr_hash.bits);
	195	/*
	196	* 4x is an arbitrary value used to warn on a hash table much bigger
	197	* than expected on most systems.
	198	*/
	199	if (mpidr_hash_size() > 4 * num_possible_cpus())
200	pr_warn("Large number of MPIDR hash buckets detected\n");
201	__flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
202	}
203	#endif
204
9703d9d7 CM	205	static void __init setup_processor(void)
	206	{
	207	struct cpu_info *cpu_info;
4bff28cc	208	u64 features, block;
a41dc0e8 CM	209	u32 cwg;
a41dc0e8 CM	210	int cls;
9703d9d7	211
9703d9d7 CM	212	cpu_info = lookup_processor_type(read_cpuid_id());
	213	if (!cpu_info) {
	214	printk("CPU configuration botched (ID %08x), unable to continue.\n",
	215	read_cpuid_id());
	216	while (1);
	217	}
	218
	219	cpu_name = cpu_info->cpu_name;
	220
	221	printk("CPU: %s [%08x] revision %d\n",
	222	cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
	223
94ed1f2c	224	sprintf(init_utsname()->machine, ELF_PLATFORM);
9703d9d7	225	elf_hwcap = 0;
4bff28cc	226
df857416 MR	227	cpuinfo_store_boot_cpu();
df857416 MR	228
a41dc0e8 CM	229	/*
	230	* Check for sane CTR_EL0.CWG value.
	231	*/
	232	cwg = cache_type_cwg();
	233	cls = cache_line_size();
	234	if (!cwg)
	235	pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
	236	cls);
	237	if (L1_CACHE_BYTES < cls)
	238	pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
	239	L1_CACHE_BYTES, cls);
	240
4bff28cc SC	241	/*
	242	* ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
	243	* The blocks we test below represent incremental functionality
	244	* for non-negative values. Negative values are reserved.
	245	*/
	246	features = read_cpuid(ID_AA64ISAR0_EL1);
	247	block = (features >> 4) & 0xf;
	248	if (!(block & 0x8)) {
	249	switch (block) {
	250	default:
	251	case 2:
	252	elf_hwcap \|= HWCAP_PMULL;
	253	case 1:
	254	elf_hwcap \|= HWCAP_AES;
	255	case 0:
	256	break;
	257	}
	258	}
	259
	260	block = (features >> 8) & 0xf;
	261	if (block && !(block & 0x8))
	262	elf_hwcap \|= HWCAP_SHA1;
	263
	264	block = (features >> 12) & 0xf;
	265	if (block && !(block & 0x8))
	266	elf_hwcap \|= HWCAP_SHA2;
	267
	268	block = (features >> 16) & 0xf;
	269	if (block && !(block & 0x8))
	270	elf_hwcap \|= HWCAP_CRC32;
4cf761cd AB	271
	272	#ifdef CONFIG_COMPAT
	273	/*
	274	* ID_ISAR5_EL1 carries similar information as above, but pertaining to
	275	* the Aarch32 32-bit execution state.
	276	*/
	277	features = read_cpuid(ID_ISAR5_EL1);
	278	block = (features >> 4) & 0xf;
	279	if (!(block & 0x8)) {
	280	switch (block) {
	281	default:
	282	case 2:
	283	compat_elf_hwcap2 \|= COMPAT_HWCAP2_PMULL;
	284	case 1:
	285	compat_elf_hwcap2 \|= COMPAT_HWCAP2_AES;
	286	case 0:
	287	break;
	288	}
	289	}
	290
	291	block = (features >> 8) & 0xf;
	292	if (block && !(block & 0x8))
	293	compat_elf_hwcap2 \|= COMPAT_HWCAP2_SHA1;
	294
	295	block = (features >> 12) & 0xf;
	296	if (block && !(block & 0x8))
	297	compat_elf_hwcap2 \|= COMPAT_HWCAP2_SHA2;
	298
	299	block = (features >> 16) & 0xf;
	300	if (block && !(block & 0x8))
	301	compat_elf_hwcap2 \|= COMPAT_HWCAP2_CRC32;
	302	#endif
9703d9d7 CM	303	}
	304
	305	static void __init setup_machine_fdt(phys_addr_t dt_phys)
	306	{
d5189cc5	307	if (!dt_phys \|\| !early_init_dt_scan(phys_to_virt(dt_phys))) {
9703d9d7 CM	308	early_print("\n"
9703d9d7 CM	309	"Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
d5189cc5	310	"The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
9703d9d7	311	"\nPlease check your bootloader.\n",
d5189cc5	312	dt_phys, phys_to_virt(dt_phys));
9703d9d7 CM	313
	314	while (true)
	315	cpu_relax();
	316	}
5e39977e WD	317
5e39977e WD	318	machine_name = of_flat_dt_get_machine_name();
d8c6d8b8	319	dump_stack_set_arch_desc("%s (DT)", machine_name);
9703d9d7 CM	320	}
9703d9d7 CM	321
9703d9d7 CM	322	/*
	323	* Limit the memory size that was specified via FDT.
	324	*/
	325	static int __init early_mem(char *p)
	326	{
	327	phys_addr_t limit;
	328
	329	if (!p)
	330	return 1;
	331
	332	limit = memparse(p, &p) & PAGE_MASK;
	333	pr_notice("Memory limited to %lldMB\n", limit >> 20);
	334
	335	memblock_enforce_memory_limit(limit);
	336
	337	return 0;
	338	}
	339	early_param("mem", early_mem);
	340
	341	static void __init request_standard_resources(void)
	342	{
	343	struct memblock_region *region;
	344	struct resource *res;
	345
	346	kernel_code.start = virt_to_phys(_text);
	347	kernel_code.end = virt_to_phys(_etext - 1);
	348	kernel_data.start = virt_to_phys(_sdata);
	349	kernel_data.end = virt_to_phys(_end - 1);
	350
	351	for_each_memblock(memory, region) {
	352	res = alloc_bootmem_low(sizeof(*res));
	353	res->name = "System RAM";
	354	res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
	355	res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
	356	res->flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
	357
	358	request_resource(&iomem_resource, res);
	359
	360	if (kernel_code.start >= res->start &&
	361	kernel_code.end <= res->end)
	362	request_resource(res, &kernel_code);
	363	if (kernel_data.start >= res->start &&
	364	kernel_data.end <= res->end)
	365	request_resource(res, &kernel_data);
	366	}
	367	}
	368
4c7aa002 JM	369	u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
4c7aa002 JM	370
9703d9d7 CM	371	void __init setup_arch(char **cmdline_p)
	372	{
	373	setup_processor();
	374
	375	setup_machine_fdt(__fdt_pointer);
	376
	377	init_mm.start_code = (unsigned long) _text;
	378	init_mm.end_code = (unsigned long) _etext;
	379	init_mm.end_data = (unsigned long) _edata;
	380	init_mm.brk = (unsigned long) _end;
	381
	382	*cmdline_p = boot_command_line;
	383
bf4b558e	384	early_ioremap_init();
0bf757c7	385
9703d9d7 CM	386	parse_early_param();
9703d9d7 CM	387
7a9c43be JM	388	/*
	389	* Unmask asynchronous aborts after bringing up possible earlycon.
	390	* (Report possible System Errors once we can report this occurred)
	391	*/
	392	local_async_enable();
	393
f84d0275	394	efi_init();
9703d9d7 CM	395	arm64_memblock_init();
	396
	397	paging_init();
	398	request_standard_resources();
	399
f84d0275 MS	400	efi_idmap_init();
f84d0275 MS	401
9703d9d7 CM	402	unflatten_device_tree();
9703d9d7 CM	403
e790f1de WD	404	psci_init();
e790f1de WD	405
e8765b26	406	cpu_read_bootcpu_ops();
9703d9d7 CM	407	#ifdef CONFIG_SMP
9703d9d7 CM	408	smp_init_cpus();
976d7d3f	409	smp_build_mpidr_hash();
9703d9d7 CM	410	#endif
	411
	412	#ifdef CONFIG_VT
	413	#if defined(CONFIG_VGA_CONSOLE)
	414	conswitchp = &vga_con;
	415	#elif defined(CONFIG_DUMMY_CONSOLE)
	416	conswitchp = &dummy_con;
	417	#endif
	418	#endif
	419	}
	420
c560ecfe	421	static int __init arm64_device_init(void)
de79a64d	422	{
c560ecfe	423	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
de79a64d CM	424	return 0;
de79a64d CM	425	}
6ecba8eb	426	arch_initcall_sync(arm64_device_init);
de79a64d	427
9703d9d7 CM	428	static int __init topology_init(void)
	429	{
	430	int i;
	431
	432	for_each_possible_cpu(i) {
df857416	433	struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
9703d9d7 CM	434	cpu->hotpluggable = 1;
	435	register_cpu(cpu, i);
	436	}
	437
	438	return 0;
	439	}
	440	subsys_initcall(topology_init);
	441
	442	static const char *hwcap_str[] = {
	443	"fp",
	444	"asimd",
46efe547	445	"evtstrm",
4bff28cc SC	446	"aes",
	447	"pmull",
	448	"sha1",
	449	"sha2",
	450	"crc32",
9703d9d7 CM	451	NULL
	452	};
	453
	454	static int c_show(struct seq_file m, void v)
	455	{
	456	int i;
	457
5e39977e WD	458	seq_printf(m, "Processor\t: %s rev %d (%s)\n",
5e39977e WD	459	cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
9703d9d7 CM	460
	461	for_each_online_cpu(i) {
	462	/*
	463	* glibc reads /proc/cpuinfo to determine the number of
	464	* online processors, looking for lines beginning with
	465	* "processor". Give glibc what it expects.
	466	*/
	467	#ifdef CONFIG_SMP
	468	seq_printf(m, "processor\t: %d\n", i);
	469	#endif
9703d9d7 CM	470	}
9703d9d7 CM	471
5e39977e WD	472	/* dump out the processor features */
	473	seq_puts(m, "Features\t: ");
	474
	475	for (i = 0; hwcap_str[i]; i++)
	476	if (elf_hwcap & (1 << i))
	477	seq_printf(m, "%s ", hwcap_str[i]);
	478
	479	seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
	480	seq_printf(m, "CPU architecture: AArch64\n");
	481	seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
	482	seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
	483	seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
	484
	485	seq_puts(m, "\n");
	486
	487	seq_printf(m, "Hardware\t: %s\n", machine_name);
	488
9703d9d7 CM	489	return 0;
	490	}
	491
	492	static void c_start(struct seq_file m, loff_t *pos)
	493	{
	494	return pos < 1 ? (void )1 : NULL;
	495	}
	496
	497	static void c_next(struct seq_file m, void v, loff_t pos)
	498	{
	499	++*pos;
	500	return NULL;
	501	}
	502
	503	static void c_stop(struct seq_file m, void v)
	504	{
	505	}
	506
	507	const struct seq_operations cpuinfo_op = {
	508	.start = c_start,
	509	.next = c_next,
	510	.stop = c_stop,
	511	.show = c_show
	512	};