Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / arch / arm64 / kernel / smp.c
CommitLineData
08e875c1
CM
1/*
2 * SMP initialisation and IPI support
3 * Based on arch/arm/kernel/smp.c
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/delay.h>
21#include <linux/init.h>
22#include <linux/spinlock.h>
23#include <linux/sched.h>
24#include <linux/interrupt.h>
25#include <linux/cache.h>
26#include <linux/profile.h>
27#include <linux/errno.h>
28#include <linux/mm.h>
29#include <linux/err.h>
30#include <linux/cpu.h>
31#include <linux/smp.h>
32#include <linux/seq_file.h>
33#include <linux/irq.h>
34#include <linux/percpu.h>
35#include <linux/clockchips.h>
36#include <linux/completion.h>
37#include <linux/of.h>
eb631bb5 38#include <linux/irq_work.h>
08e875c1
CM
39
40#include <asm/atomic.h>
41#include <asm/cacheflush.h>
df857416 42#include <asm/cpu.h>
08e875c1 43#include <asm/cputype.h>
cd1aebf5 44#include <asm/cpu_ops.h>
08e875c1
CM
45#include <asm/mmu_context.h>
46#include <asm/pgtable.h>
47#include <asm/pgalloc.h>
48#include <asm/processor.h>
4c7aa002 49#include <asm/smp_plat.h>
08e875c1
CM
50#include <asm/sections.h>
51#include <asm/tlbflush.h>
52#include <asm/ptrace.h>
08e875c1
CM
53
54/*
55 * as from 2.5, kernels no longer have an init_tasks structure
56 * so we need some other way of telling a new secondary core
57 * where to place its SVC stack
58 */
59struct secondary_data secondary_data;
08e875c1
CM
60
61enum ipi_msg_type {
62 IPI_RESCHEDULE,
63 IPI_CALL_FUNC,
64 IPI_CALL_FUNC_SINGLE,
65 IPI_CPU_STOP,
1f85008e 66 IPI_TIMER,
eb631bb5 67 IPI_IRQ_WORK,
08e875c1
CM
68};
69
08e875c1
CM
70/*
71 * Boot a secondary CPU, and assign it the specified idle task.
72 * This also gives us the initial stack to use for this CPU.
73 */
b8c6453a 74static int boot_secondary(unsigned int cpu, struct task_struct *idle)
08e875c1 75{
652af899
MR
76 if (cpu_ops[cpu]->cpu_boot)
77 return cpu_ops[cpu]->cpu_boot(cpu);
08e875c1 78
652af899 79 return -EOPNOTSUPP;
08e875c1
CM
80}
81
82static DECLARE_COMPLETION(cpu_running);
83
b8c6453a 84int __cpu_up(unsigned int cpu, struct task_struct *idle)
08e875c1
CM
85{
86 int ret;
87
88 /*
89 * We need to tell the secondary core where to find its stack and the
90 * page tables.
91 */
92 secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
93 __flush_dcache_area(&secondary_data, sizeof(secondary_data));
94
95 /*
96 * Now bring the CPU into our world.
97 */
98 ret = boot_secondary(cpu, idle);
99 if (ret == 0) {
100 /*
101 * CPU was successfully started, wait for it to come online or
102 * time out.
103 */
104 wait_for_completion_timeout(&cpu_running,
105 msecs_to_jiffies(1000));
106
107 if (!cpu_online(cpu)) {
108 pr_crit("CPU%u: failed to come online\n", cpu);
109 ret = -EIO;
110 }
111 } else {
112 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
113 }
114
115 secondary_data.stack = NULL;
116
117 return ret;
118}
119
f6e763b9
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120static void smp_store_cpu_info(unsigned int cpuid)
121{
122 store_cpu_topology(cpuid);
123}
124
08e875c1
CM
125/*
126 * This is the secondary CPU boot entry. We're using this CPUs
127 * idle thread stack, but a set of temporary page tables.
128 */
b8c6453a 129asmlinkage void secondary_start_kernel(void)
08e875c1
CM
130{
131 struct mm_struct *mm = &init_mm;
132 unsigned int cpu = smp_processor_id();
133
08e875c1
CM
134 /*
135 * All kernel threads share the same mm context; grab a
136 * reference and switch to it.
137 */
138 atomic_inc(&mm->mm_count);
139 current->active_mm = mm;
140 cpumask_set_cpu(cpu, mm_cpumask(mm));
141
71586276
WD
142 set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
143 printk("CPU%u: Booted secondary processor\n", cpu);
144
08e875c1
CM
145 /*
146 * TTBR0 is only used for the identity mapping at this stage. Make it
147 * point to zero page to avoid speculatively fetching new entries.
148 */
149 cpu_set_reserved_ttbr0();
150 flush_tlb_all();
151
152 preempt_disable();
153 trace_hardirqs_off();
154
652af899
MR
155 if (cpu_ops[cpu]->cpu_postboot)
156 cpu_ops[cpu]->cpu_postboot();
08e875c1 157
df857416
MR
158 /*
159 * Log the CPU info before it is marked online and might get read.
160 */
161 cpuinfo_store_cpu();
162
7ade67b5
MZ
163 /*
164 * Enable GIC and timers.
165 */
166 notify_cpu_starting(cpu);
167
f6e763b9
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168 smp_store_cpu_info(cpu);
169
08e875c1
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170 /*
171 * OK, now it's safe to let the boot CPU continue. Wait for
172 * the CPU migration code to notice that the CPU is online
173 * before we continue.
174 */
175 set_cpu_online(cpu, true);
b3770b32 176 complete(&cpu_running);
08e875c1 177
d8ed442a 178 local_dbg_enable();
53ae3acd 179 local_irq_enable();
b3bf6aa7 180 local_async_enable();
53ae3acd 181
08e875c1
CM
182 /*
183 * OK, it's off to the idle thread for us
184 */
0087298f 185 cpu_startup_entry(CPUHP_ONLINE);
08e875c1
CM
186}
187
9327e2c6
MR
188#ifdef CONFIG_HOTPLUG_CPU
189static int op_cpu_disable(unsigned int cpu)
190{
191 /*
192 * If we don't have a cpu_die method, abort before we reach the point
193 * of no return. CPU0 may not have an cpu_ops, so test for it.
194 */
195 if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die)
196 return -EOPNOTSUPP;
197
198 /*
199 * We may need to abort a hot unplug for some other mechanism-specific
200 * reason.
201 */
202 if (cpu_ops[cpu]->cpu_disable)
203 return cpu_ops[cpu]->cpu_disable(cpu);
204
205 return 0;
206}
207
208/*
209 * __cpu_disable runs on the processor to be shutdown.
210 */
211int __cpu_disable(void)
212{
213 unsigned int cpu = smp_processor_id();
214 int ret;
215
216 ret = op_cpu_disable(cpu);
217 if (ret)
218 return ret;
219
220 /*
221 * Take this CPU offline. Once we clear this, we can't return,
222 * and we must not schedule until we're ready to give up the cpu.
223 */
224 set_cpu_online(cpu, false);
225
226 /*
227 * OK - migrate IRQs away from this CPU
228 */
229 migrate_irqs();
230
231 /*
232 * Remove this CPU from the vm mask set of all processes.
233 */
234 clear_tasks_mm_cpumask(cpu);
235
236 return 0;
237}
238
c814ca02
AC
239static int op_cpu_kill(unsigned int cpu)
240{
241 /*
242 * If we have no means of synchronising with the dying CPU, then assume
243 * that it is really dead. We can only wait for an arbitrary length of
244 * time and hope that it's dead, so let's skip the wait and just hope.
245 */
246 if (!cpu_ops[cpu]->cpu_kill)
247 return 1;
248
249 return cpu_ops[cpu]->cpu_kill(cpu);
250}
251
9327e2c6
MR
252static DECLARE_COMPLETION(cpu_died);
253
254/*
255 * called on the thread which is asking for a CPU to be shutdown -
256 * waits until shutdown has completed, or it is timed out.
257 */
258void __cpu_die(unsigned int cpu)
259{
260 if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
261 pr_crit("CPU%u: cpu didn't die\n", cpu);
262 return;
263 }
264 pr_notice("CPU%u: shutdown\n", cpu);
c814ca02
AC
265
266 /*
267 * Now that the dying CPU is beyond the point of no return w.r.t.
268 * in-kernel synchronisation, try to get the firwmare to help us to
269 * verify that it has really left the kernel before we consider
270 * clobbering anything it might still be using.
271 */
272 if (!op_cpu_kill(cpu))
273 pr_warn("CPU%d may not have shut down cleanly\n", cpu);
9327e2c6
MR
274}
275
276/*
277 * Called from the idle thread for the CPU which has been shutdown.
278 *
279 * Note that we disable IRQs here, but do not re-enable them
280 * before returning to the caller. This is also the behaviour
281 * of the other hotplug-cpu capable cores, so presumably coming
282 * out of idle fixes this.
283 */
284void cpu_die(void)
285{
286 unsigned int cpu = smp_processor_id();
287
288 idle_task_exit();
289
290 local_irq_disable();
291
292 /* Tell __cpu_die() that this CPU is now safe to dispose of */
293 complete(&cpu_died);
294
295 /*
296 * Actually shutdown the CPU. This must never fail. The specific hotplug
297 * mechanism must perform all required cache maintenance to ensure that
298 * no dirty lines are lost in the process of shutting down the CPU.
299 */
300 cpu_ops[cpu]->cpu_die(cpu);
301
302 BUG();
303}
304#endif
305
08e875c1
CM
306void __init smp_cpus_done(unsigned int max_cpus)
307{
326b16db 308 pr_info("SMP: Total of %d processors activated.\n", num_online_cpus());
08e875c1
CM
309}
310
311void __init smp_prepare_boot_cpu(void)
312{
71586276 313 set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
08e875c1
CM
314}
315
316static void (*smp_cross_call)(const struct cpumask *, unsigned int);
d329de3f 317
08e875c1 318/*
4c7aa002
JM
319 * Enumerate the possible CPU set from the device tree and build the
320 * cpu logical map array containing MPIDR values related to logical
321 * cpus. Assumes that cpu_logical_map(0) has already been initialized.
08e875c1
CM
322 */
323void __init smp_init_cpus(void)
324{
08e875c1 325 struct device_node *dn = NULL;
cd1aebf5 326 unsigned int i, cpu = 1;
4c7aa002 327 bool bootcpu_valid = false;
08e875c1
CM
328
329 while ((dn = of_find_node_by_type(dn, "cpu"))) {
72aea393 330 const u32 *cell;
4c7aa002
JM
331 u64 hwid;
332
333 /*
334 * A cpu node with missing "reg" property is
335 * considered invalid to build a cpu_logical_map
336 * entry.
337 */
72aea393
WD
338 cell = of_get_property(dn, "reg", NULL);
339 if (!cell) {
4c7aa002
JM
340 pr_err("%s: missing reg property\n", dn->full_name);
341 goto next;
342 }
72aea393 343 hwid = of_read_number(cell, of_n_addr_cells(dn));
4c7aa002
JM
344
345 /*
346 * Non affinity bits must be set to 0 in the DT
347 */
348 if (hwid & ~MPIDR_HWID_BITMASK) {
349 pr_err("%s: invalid reg property\n", dn->full_name);
350 goto next;
351 }
352
353 /*
354 * Duplicate MPIDRs are a recipe for disaster. Scan
355 * all initialized entries and check for
356 * duplicates. If any is found just ignore the cpu.
357 * cpu_logical_map was initialized to INVALID_HWID to
358 * avoid matching valid MPIDR values.
359 */
360 for (i = 1; (i < cpu) && (i < NR_CPUS); i++) {
361 if (cpu_logical_map(i) == hwid) {
362 pr_err("%s: duplicate cpu reg properties in the DT\n",
363 dn->full_name);
364 goto next;
365 }
366 }
367
368 /*
369 * The numbering scheme requires that the boot CPU
370 * must be assigned logical id 0. Record it so that
371 * the logical map built from DT is validated and can
372 * be used.
373 */
374 if (hwid == cpu_logical_map(0)) {
375 if (bootcpu_valid) {
376 pr_err("%s: duplicate boot cpu reg property in DT\n",
377 dn->full_name);
378 goto next;
379 }
380
381 bootcpu_valid = true;
382
383 /*
384 * cpu_logical_map has already been
385 * initialized and the boot cpu doesn't need
386 * the enable-method so continue without
387 * incrementing cpu.
388 */
389 continue;
390 }
391
08e875c1
CM
392 if (cpu >= NR_CPUS)
393 goto next;
394
e8765b26 395 if (cpu_read_ops(dn, cpu) != 0)
08e875c1 396 goto next;
08e875c1 397
cd1aebf5 398 if (cpu_ops[cpu]->cpu_init(dn, cpu))
d329de3f
MZ
399 goto next;
400
4c7aa002
JM
401 pr_debug("cpu logical map 0x%llx\n", hwid);
402 cpu_logical_map(cpu) = hwid;
08e875c1
CM
403next:
404 cpu++;
405 }
406
407 /* sanity check */
408 if (cpu > NR_CPUS)
409 pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n",
410 cpu, NR_CPUS);
4c7aa002
JM
411
412 if (!bootcpu_valid) {
413 pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n");
414 return;
415 }
416
417 /*
418 * All the cpus that made it to the cpu_logical_map have been
419 * validated so set them as possible cpus.
420 */
421 for (i = 0; i < NR_CPUS; i++)
422 if (cpu_logical_map(i) != INVALID_HWID)
423 set_cpu_possible(i, true);
08e875c1
CM
424}
425
426void __init smp_prepare_cpus(unsigned int max_cpus)
427{
cd1aebf5
MR
428 int err;
429 unsigned int cpu, ncores = num_possible_cpus();
08e875c1 430
f6e763b9
MB
431 init_cpu_topology();
432
433 smp_store_cpu_info(smp_processor_id());
434
08e875c1
CM
435 /*
436 * are we trying to boot more cores than exist?
437 */
438 if (max_cpus > ncores)
439 max_cpus = ncores;
440
d329de3f
MZ
441 /* Don't bother if we're effectively UP */
442 if (max_cpus <= 1)
443 return;
444
08e875c1
CM
445 /*
446 * Initialise the present map (which describes the set of CPUs
447 * actually populated at the present time) and release the
448 * secondaries from the bootloader.
d329de3f
MZ
449 *
450 * Make sure we online at most (max_cpus - 1) additional CPUs.
08e875c1 451 */
d329de3f 452 max_cpus--;
08e875c1
CM
453 for_each_possible_cpu(cpu) {
454 if (max_cpus == 0)
455 break;
456
d329de3f
MZ
457 if (cpu == smp_processor_id())
458 continue;
459
cd1aebf5 460 if (!cpu_ops[cpu])
08e875c1
CM
461 continue;
462
cd1aebf5 463 err = cpu_ops[cpu]->cpu_prepare(cpu);
d329de3f
MZ
464 if (err)
465 continue;
08e875c1
CM
466
467 set_cpu_present(cpu, true);
468 max_cpus--;
469 }
08e875c1
CM
470}
471
472
473void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
474{
475 smp_cross_call = fn;
476}
477
478void arch_send_call_function_ipi_mask(const struct cpumask *mask)
479{
480 smp_cross_call(mask, IPI_CALL_FUNC);
481}
482
483void arch_send_call_function_single_ipi(int cpu)
484{
485 smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
486}
487
eb631bb5
LB
488#ifdef CONFIG_IRQ_WORK
489void arch_irq_work_raise(void)
490{
491 if (smp_cross_call)
492 smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
493}
494#endif
495
08e875c1
CM
496static const char *ipi_types[NR_IPI] = {
497#define S(x,s) [x - IPI_RESCHEDULE] = s
498 S(IPI_RESCHEDULE, "Rescheduling interrupts"),
499 S(IPI_CALL_FUNC, "Function call interrupts"),
500 S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
501 S(IPI_CPU_STOP, "CPU stop interrupts"),
1f85008e 502 S(IPI_TIMER, "Timer broadcast interrupts"),
eb631bb5 503 S(IPI_IRQ_WORK, "IRQ work interrupts"),
08e875c1
CM
504};
505
506void show_ipi_list(struct seq_file *p, int prec)
507{
508 unsigned int cpu, i;
509
510 for (i = 0; i < NR_IPI; i++) {
511 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i + IPI_RESCHEDULE,
512 prec >= 4 ? " " : "");
67317c26 513 for_each_online_cpu(cpu)
08e875c1
CM
514 seq_printf(p, "%10u ",
515 __get_irq_stat(cpu, ipi_irqs[i]));
516 seq_printf(p, " %s\n", ipi_types[i]);
517 }
518}
519
520u64 smp_irq_stat_cpu(unsigned int cpu)
521{
522 u64 sum = 0;
523 int i;
524
525 for (i = 0; i < NR_IPI; i++)
526 sum += __get_irq_stat(cpu, ipi_irqs[i]);
527
528 return sum;
529}
530
531static DEFINE_RAW_SPINLOCK(stop_lock);
532
533/*
534 * ipi_cpu_stop - handle IPI from smp_send_stop()
535 */
536static void ipi_cpu_stop(unsigned int cpu)
537{
538 if (system_state == SYSTEM_BOOTING ||
539 system_state == SYSTEM_RUNNING) {
540 raw_spin_lock(&stop_lock);
541 pr_crit("CPU%u: stopping\n", cpu);
542 dump_stack();
543 raw_spin_unlock(&stop_lock);
544 }
545
546 set_cpu_online(cpu, false);
547
08e875c1
CM
548 local_irq_disable();
549
550 while (1)
551 cpu_relax();
552}
553
554/*
555 * Main handler for inter-processor interrupts
556 */
557void handle_IPI(int ipinr, struct pt_regs *regs)
558{
559 unsigned int cpu = smp_processor_id();
560 struct pt_regs *old_regs = set_irq_regs(regs);
561
562 if (ipinr >= IPI_RESCHEDULE && ipinr < IPI_RESCHEDULE + NR_IPI)
563 __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_RESCHEDULE]);
564
565 switch (ipinr) {
566 case IPI_RESCHEDULE:
567 scheduler_ipi();
568 break;
569
570 case IPI_CALL_FUNC:
571 irq_enter();
572 generic_smp_call_function_interrupt();
573 irq_exit();
574 break;
575
576 case IPI_CALL_FUNC_SINGLE:
577 irq_enter();
578 generic_smp_call_function_single_interrupt();
579 irq_exit();
580 break;
581
582 case IPI_CPU_STOP:
583 irq_enter();
584 ipi_cpu_stop(cpu);
585 irq_exit();
586 break;
587
1f85008e
LP
588#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
589 case IPI_TIMER:
590 irq_enter();
591 tick_receive_broadcast();
592 irq_exit();
593 break;
594#endif
595
eb631bb5
LB
596#ifdef CONFIG_IRQ_WORK
597 case IPI_IRQ_WORK:
598 irq_enter();
599 irq_work_run();
600 irq_exit();
601 break;
602#endif
603
08e875c1
CM
604 default:
605 pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
606 break;
607 }
608 set_irq_regs(old_regs);
609}
610
611void smp_send_reschedule(int cpu)
612{
613 smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
614}
615
1f85008e
LP
616#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
617void tick_broadcast(const struct cpumask *mask)
618{
619 smp_cross_call(mask, IPI_TIMER);
620}
621#endif
622
08e875c1
CM
623void smp_send_stop(void)
624{
625 unsigned long timeout;
626
627 if (num_online_cpus() > 1) {
628 cpumask_t mask;
629
630 cpumask_copy(&mask, cpu_online_mask);
631 cpu_clear(smp_processor_id(), mask);
632
633 smp_cross_call(&mask, IPI_CPU_STOP);
634 }
635
636 /* Wait up to one second for other CPUs to stop */
637 timeout = USEC_PER_SEC;
638 while (num_online_cpus() > 1 && timeout--)
639 udelay(1);
640
641 if (num_online_cpus() > 1)
642 pr_warning("SMP: failed to stop secondary CPUs\n");
643}
644
645/*
646 * not supported here
647 */
648int setup_profiling_timer(unsigned int multiplier)
649{
650 return -EINVAL;
651}
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