Commit | Line | Data |
---|---|---|
08e875c1 CM |
1 | /* |
2 | * SMP initialisation and IPI support | |
3 | * Based on arch/arm/kernel/smp.c | |
4 | * | |
5 | * Copyright (C) 2012 ARM Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
0f078336 | 20 | #include <linux/acpi.h> |
08e875c1 CM |
21 | #include <linux/delay.h> |
22 | #include <linux/init.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/profile.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/err.h> | |
31 | #include <linux/cpu.h> | |
32 | #include <linux/smp.h> | |
33 | #include <linux/seq_file.h> | |
34 | #include <linux/irq.h> | |
35 | #include <linux/percpu.h> | |
36 | #include <linux/clockchips.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/of.h> | |
eb631bb5 | 39 | #include <linux/irq_work.h> |
08e875c1 | 40 | |
e039ee4e | 41 | #include <asm/alternative.h> |
08e875c1 CM |
42 | #include <asm/atomic.h> |
43 | #include <asm/cacheflush.h> | |
df857416 | 44 | #include <asm/cpu.h> |
08e875c1 | 45 | #include <asm/cputype.h> |
cd1aebf5 | 46 | #include <asm/cpu_ops.h> |
08e875c1 | 47 | #include <asm/mmu_context.h> |
1a2db300 | 48 | #include <asm/numa.h> |
08e875c1 CM |
49 | #include <asm/pgtable.h> |
50 | #include <asm/pgalloc.h> | |
51 | #include <asm/processor.h> | |
4c7aa002 | 52 | #include <asm/smp_plat.h> |
08e875c1 CM |
53 | #include <asm/sections.h> |
54 | #include <asm/tlbflush.h> | |
55 | #include <asm/ptrace.h> | |
377bcff9 | 56 | #include <asm/virt.h> |
08e875c1 | 57 | |
45ed695a NP |
58 | #define CREATE_TRACE_POINTS |
59 | #include <trace/events/ipi.h> | |
60 | ||
08e875c1 CM |
61 | /* |
62 | * as from 2.5, kernels no longer have an init_tasks structure | |
63 | * so we need some other way of telling a new secondary core | |
64 | * where to place its SVC stack | |
65 | */ | |
66 | struct secondary_data secondary_data; | |
bb905274 SP |
67 | /* Number of CPUs which aren't online, but looping in kernel text. */ |
68 | int cpus_stuck_in_kernel; | |
08e875c1 CM |
69 | |
70 | enum ipi_msg_type { | |
71 | IPI_RESCHEDULE, | |
72 | IPI_CALL_FUNC, | |
08e875c1 | 73 | IPI_CPU_STOP, |
1f85008e | 74 | IPI_TIMER, |
eb631bb5 | 75 | IPI_IRQ_WORK, |
5e89c55e | 76 | IPI_WAKEUP |
08e875c1 CM |
77 | }; |
78 | ||
ac1ad20f SP |
79 | #ifdef CONFIG_ARM64_VHE |
80 | ||
81 | /* Whether the boot CPU is running in HYP mode or not*/ | |
82 | static bool boot_cpu_hyp_mode; | |
83 | ||
84 | static inline void save_boot_cpu_run_el(void) | |
85 | { | |
86 | boot_cpu_hyp_mode = is_kernel_in_hyp_mode(); | |
87 | } | |
88 | ||
89 | static inline bool is_boot_cpu_in_hyp_mode(void) | |
90 | { | |
91 | return boot_cpu_hyp_mode; | |
92 | } | |
93 | ||
94 | /* | |
95 | * Verify that a secondary CPU is running the kernel at the same | |
96 | * EL as that of the boot CPU. | |
97 | */ | |
98 | void verify_cpu_run_el(void) | |
99 | { | |
100 | bool in_el2 = is_kernel_in_hyp_mode(); | |
101 | bool boot_cpu_el2 = is_boot_cpu_in_hyp_mode(); | |
102 | ||
103 | if (in_el2 ^ boot_cpu_el2) { | |
104 | pr_crit("CPU%d: mismatched Exception Level(EL%d) with boot CPU(EL%d)\n", | |
105 | smp_processor_id(), | |
106 | in_el2 ? 2 : 1, | |
107 | boot_cpu_el2 ? 2 : 1); | |
108 | cpu_panic_kernel(); | |
109 | } | |
110 | } | |
111 | ||
112 | #else | |
113 | static inline void save_boot_cpu_run_el(void) {} | |
114 | #endif | |
115 | ||
bb905274 SP |
116 | #ifdef CONFIG_HOTPLUG_CPU |
117 | static int op_cpu_kill(unsigned int cpu); | |
118 | #else | |
119 | static inline int op_cpu_kill(unsigned int cpu) | |
120 | { | |
121 | return -ENOSYS; | |
122 | } | |
123 | #endif | |
124 | ||
125 | ||
08e875c1 CM |
126 | /* |
127 | * Boot a secondary CPU, and assign it the specified idle task. | |
128 | * This also gives us the initial stack to use for this CPU. | |
129 | */ | |
b8c6453a | 130 | static int boot_secondary(unsigned int cpu, struct task_struct *idle) |
08e875c1 | 131 | { |
652af899 MR |
132 | if (cpu_ops[cpu]->cpu_boot) |
133 | return cpu_ops[cpu]->cpu_boot(cpu); | |
08e875c1 | 134 | |
652af899 | 135 | return -EOPNOTSUPP; |
08e875c1 CM |
136 | } |
137 | ||
138 | static DECLARE_COMPLETION(cpu_running); | |
139 | ||
b8c6453a | 140 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
08e875c1 CM |
141 | { |
142 | int ret; | |
bb905274 | 143 | long status; |
08e875c1 CM |
144 | |
145 | /* | |
146 | * We need to tell the secondary core where to find its stack and the | |
147 | * page tables. | |
148 | */ | |
149 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; | |
bb905274 | 150 | update_cpu_boot_status(CPU_MMU_OFF); |
08e875c1 CM |
151 | __flush_dcache_area(&secondary_data, sizeof(secondary_data)); |
152 | ||
153 | /* | |
154 | * Now bring the CPU into our world. | |
155 | */ | |
156 | ret = boot_secondary(cpu, idle); | |
157 | if (ret == 0) { | |
158 | /* | |
159 | * CPU was successfully started, wait for it to come online or | |
160 | * time out. | |
161 | */ | |
162 | wait_for_completion_timeout(&cpu_running, | |
163 | msecs_to_jiffies(1000)); | |
164 | ||
165 | if (!cpu_online(cpu)) { | |
166 | pr_crit("CPU%u: failed to come online\n", cpu); | |
167 | ret = -EIO; | |
168 | } | |
169 | } else { | |
170 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
171 | } | |
172 | ||
173 | secondary_data.stack = NULL; | |
bb905274 SP |
174 | status = READ_ONCE(secondary_data.status); |
175 | if (ret && status) { | |
176 | ||
177 | if (status == CPU_MMU_OFF) | |
178 | status = READ_ONCE(__early_cpu_boot_status); | |
179 | ||
180 | switch (status) { | |
181 | default: | |
182 | pr_err("CPU%u: failed in unknown state : 0x%lx\n", | |
183 | cpu, status); | |
184 | break; | |
185 | case CPU_KILL_ME: | |
186 | if (!op_cpu_kill(cpu)) { | |
187 | pr_crit("CPU%u: died during early boot\n", cpu); | |
188 | break; | |
189 | } | |
190 | /* Fall through */ | |
191 | pr_crit("CPU%u: may not have shut down cleanly\n", cpu); | |
192 | case CPU_STUCK_IN_KERNEL: | |
193 | pr_crit("CPU%u: is stuck in kernel\n", cpu); | |
194 | cpus_stuck_in_kernel++; | |
195 | break; | |
196 | case CPU_PANIC_KERNEL: | |
197 | panic("CPU%u detected unsupported configuration\n", cpu); | |
198 | } | |
199 | } | |
08e875c1 CM |
200 | |
201 | return ret; | |
202 | } | |
203 | ||
f6e763b9 MB |
204 | static void smp_store_cpu_info(unsigned int cpuid) |
205 | { | |
206 | store_cpu_topology(cpuid); | |
1a2db300 | 207 | numa_store_cpu_info(cpuid); |
f6e763b9 MB |
208 | } |
209 | ||
08e875c1 CM |
210 | /* |
211 | * This is the secondary CPU boot entry. We're using this CPUs | |
212 | * idle thread stack, but a set of temporary page tables. | |
213 | */ | |
b8c6453a | 214 | asmlinkage void secondary_start_kernel(void) |
08e875c1 CM |
215 | { |
216 | struct mm_struct *mm = &init_mm; | |
217 | unsigned int cpu = smp_processor_id(); | |
218 | ||
08e875c1 CM |
219 | /* |
220 | * All kernel threads share the same mm context; grab a | |
221 | * reference and switch to it. | |
222 | */ | |
223 | atomic_inc(&mm->mm_count); | |
224 | current->active_mm = mm; | |
08e875c1 | 225 | |
71586276 | 226 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
71586276 | 227 | |
08e875c1 CM |
228 | /* |
229 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
230 | * point to zero page to avoid speculatively fetching new entries. | |
231 | */ | |
9e8e865b | 232 | cpu_uninstall_idmap(); |
08e875c1 CM |
233 | |
234 | preempt_disable(); | |
235 | trace_hardirqs_off(); | |
236 | ||
dbb4e152 SP |
237 | /* |
238 | * If the system has established the capabilities, make sure | |
239 | * this CPU ticks all of those. If it doesn't, the CPU will | |
240 | * fail to come online. | |
241 | */ | |
c47a1900 | 242 | check_local_cpu_capabilities(); |
dbb4e152 | 243 | |
652af899 MR |
244 | if (cpu_ops[cpu]->cpu_postboot) |
245 | cpu_ops[cpu]->cpu_postboot(); | |
08e875c1 | 246 | |
df857416 MR |
247 | /* |
248 | * Log the CPU info before it is marked online and might get read. | |
249 | */ | |
250 | cpuinfo_store_cpu(); | |
251 | ||
7ade67b5 MZ |
252 | /* |
253 | * Enable GIC and timers. | |
254 | */ | |
255 | notify_cpu_starting(cpu); | |
256 | ||
f6e763b9 MB |
257 | smp_store_cpu_info(cpu); |
258 | ||
08e875c1 CM |
259 | /* |
260 | * OK, now it's safe to let the boot CPU continue. Wait for | |
261 | * the CPU migration code to notice that the CPU is online | |
262 | * before we continue. | |
263 | */ | |
64f17818 SP |
264 | pr_info("CPU%u: Booted secondary processor [%08x]\n", |
265 | cpu, read_cpuid_id()); | |
bb905274 | 266 | update_cpu_boot_status(CPU_BOOT_SUCCESS); |
08e875c1 | 267 | set_cpu_online(cpu, true); |
b3770b32 | 268 | complete(&cpu_running); |
08e875c1 | 269 | |
53ae3acd | 270 | local_irq_enable(); |
b3bf6aa7 | 271 | local_async_enable(); |
53ae3acd | 272 | |
08e875c1 CM |
273 | /* |
274 | * OK, it's off to the idle thread for us | |
275 | */ | |
fc6d73d6 | 276 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
08e875c1 CM |
277 | } |
278 | ||
9327e2c6 MR |
279 | #ifdef CONFIG_HOTPLUG_CPU |
280 | static int op_cpu_disable(unsigned int cpu) | |
281 | { | |
282 | /* | |
283 | * If we don't have a cpu_die method, abort before we reach the point | |
284 | * of no return. CPU0 may not have an cpu_ops, so test for it. | |
285 | */ | |
286 | if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die) | |
287 | return -EOPNOTSUPP; | |
288 | ||
289 | /* | |
290 | * We may need to abort a hot unplug for some other mechanism-specific | |
291 | * reason. | |
292 | */ | |
293 | if (cpu_ops[cpu]->cpu_disable) | |
294 | return cpu_ops[cpu]->cpu_disable(cpu); | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
299 | /* | |
300 | * __cpu_disable runs on the processor to be shutdown. | |
301 | */ | |
302 | int __cpu_disable(void) | |
303 | { | |
304 | unsigned int cpu = smp_processor_id(); | |
305 | int ret; | |
306 | ||
307 | ret = op_cpu_disable(cpu); | |
308 | if (ret) | |
309 | return ret; | |
310 | ||
311 | /* | |
312 | * Take this CPU offline. Once we clear this, we can't return, | |
313 | * and we must not schedule until we're ready to give up the cpu. | |
314 | */ | |
315 | set_cpu_online(cpu, false); | |
316 | ||
317 | /* | |
318 | * OK - migrate IRQs away from this CPU | |
319 | */ | |
217d453d YY |
320 | irq_migrate_all_off_this_cpu(); |
321 | ||
9327e2c6 MR |
322 | return 0; |
323 | } | |
324 | ||
c814ca02 AC |
325 | static int op_cpu_kill(unsigned int cpu) |
326 | { | |
327 | /* | |
328 | * If we have no means of synchronising with the dying CPU, then assume | |
329 | * that it is really dead. We can only wait for an arbitrary length of | |
330 | * time and hope that it's dead, so let's skip the wait and just hope. | |
331 | */ | |
332 | if (!cpu_ops[cpu]->cpu_kill) | |
6b99c68c | 333 | return 0; |
c814ca02 AC |
334 | |
335 | return cpu_ops[cpu]->cpu_kill(cpu); | |
336 | } | |
337 | ||
9327e2c6 MR |
338 | /* |
339 | * called on the thread which is asking for a CPU to be shutdown - | |
340 | * waits until shutdown has completed, or it is timed out. | |
341 | */ | |
342 | void __cpu_die(unsigned int cpu) | |
343 | { | |
6b99c68c MR |
344 | int err; |
345 | ||
05981277 | 346 | if (!cpu_wait_death(cpu, 5)) { |
9327e2c6 MR |
347 | pr_crit("CPU%u: cpu didn't die\n", cpu); |
348 | return; | |
349 | } | |
350 | pr_notice("CPU%u: shutdown\n", cpu); | |
c814ca02 AC |
351 | |
352 | /* | |
353 | * Now that the dying CPU is beyond the point of no return w.r.t. | |
354 | * in-kernel synchronisation, try to get the firwmare to help us to | |
355 | * verify that it has really left the kernel before we consider | |
356 | * clobbering anything it might still be using. | |
357 | */ | |
6b99c68c MR |
358 | err = op_cpu_kill(cpu); |
359 | if (err) | |
360 | pr_warn("CPU%d may not have shut down cleanly: %d\n", | |
361 | cpu, err); | |
9327e2c6 MR |
362 | } |
363 | ||
364 | /* | |
365 | * Called from the idle thread for the CPU which has been shutdown. | |
366 | * | |
367 | * Note that we disable IRQs here, but do not re-enable them | |
368 | * before returning to the caller. This is also the behaviour | |
369 | * of the other hotplug-cpu capable cores, so presumably coming | |
370 | * out of idle fixes this. | |
371 | */ | |
372 | void cpu_die(void) | |
373 | { | |
374 | unsigned int cpu = smp_processor_id(); | |
375 | ||
376 | idle_task_exit(); | |
377 | ||
378 | local_irq_disable(); | |
379 | ||
380 | /* Tell __cpu_die() that this CPU is now safe to dispose of */ | |
05981277 | 381 | (void)cpu_report_death(); |
9327e2c6 MR |
382 | |
383 | /* | |
384 | * Actually shutdown the CPU. This must never fail. The specific hotplug | |
385 | * mechanism must perform all required cache maintenance to ensure that | |
386 | * no dirty lines are lost in the process of shutting down the CPU. | |
387 | */ | |
388 | cpu_ops[cpu]->cpu_die(cpu); | |
389 | ||
390 | BUG(); | |
391 | } | |
392 | #endif | |
393 | ||
fce6361f SP |
394 | /* |
395 | * Kill the calling secondary CPU, early in bringup before it is turned | |
396 | * online. | |
397 | */ | |
398 | void cpu_die_early(void) | |
399 | { | |
400 | int cpu = smp_processor_id(); | |
401 | ||
402 | pr_crit("CPU%d: will not boot\n", cpu); | |
403 | ||
404 | /* Mark this CPU absent */ | |
405 | set_cpu_present(cpu, 0); | |
406 | ||
407 | #ifdef CONFIG_HOTPLUG_CPU | |
bb905274 | 408 | update_cpu_boot_status(CPU_KILL_ME); |
fce6361f SP |
409 | /* Check if we can park ourselves */ |
410 | if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die) | |
411 | cpu_ops[cpu]->cpu_die(cpu); | |
412 | #endif | |
bb905274 | 413 | update_cpu_boot_status(CPU_STUCK_IN_KERNEL); |
fce6361f SP |
414 | |
415 | cpu_park_loop(); | |
416 | } | |
417 | ||
377bcff9 JR |
418 | static void __init hyp_mode_check(void) |
419 | { | |
420 | if (is_hyp_mode_available()) | |
421 | pr_info("CPU: All CPU(s) started at EL2\n"); | |
422 | else if (is_hyp_mode_mismatched()) | |
423 | WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC, | |
424 | "CPU: CPUs started in inconsistent modes"); | |
425 | else | |
426 | pr_info("CPU: All CPU(s) started at EL1\n"); | |
427 | } | |
428 | ||
08e875c1 CM |
429 | void __init smp_cpus_done(unsigned int max_cpus) |
430 | { | |
326b16db | 431 | pr_info("SMP: Total of %d processors activated.\n", num_online_cpus()); |
3a75578e | 432 | setup_cpu_features(); |
377bcff9 JR |
433 | hyp_mode_check(); |
434 | apply_alternatives_all(); | |
08e875c1 CM |
435 | } |
436 | ||
437 | void __init smp_prepare_boot_cpu(void) | |
438 | { | |
9113c2aa | 439 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
efd9e03f CM |
440 | /* |
441 | * Initialise the static keys early as they may be enabled by the | |
442 | * cpufeature code. | |
443 | */ | |
444 | jump_label_init(); | |
4b998ff1 | 445 | cpuinfo_store_boot_cpu(); |
ac1ad20f | 446 | save_boot_cpu_run_el(); |
c47a1900 SP |
447 | /* |
448 | * Run the errata work around checks on the boot CPU, once we have | |
449 | * initialised the cpu feature infrastructure from | |
450 | * cpuinfo_store_boot_cpu() above. | |
451 | */ | |
452 | update_cpu_errata_workarounds(); | |
08e875c1 CM |
453 | } |
454 | ||
0f078336 LP |
455 | static u64 __init of_get_cpu_mpidr(struct device_node *dn) |
456 | { | |
457 | const __be32 *cell; | |
458 | u64 hwid; | |
459 | ||
460 | /* | |
461 | * A cpu node with missing "reg" property is | |
462 | * considered invalid to build a cpu_logical_map | |
463 | * entry. | |
464 | */ | |
465 | cell = of_get_property(dn, "reg", NULL); | |
466 | if (!cell) { | |
467 | pr_err("%s: missing reg property\n", dn->full_name); | |
468 | return INVALID_HWID; | |
469 | } | |
470 | ||
471 | hwid = of_read_number(cell, of_n_addr_cells(dn)); | |
472 | /* | |
473 | * Non affinity bits must be set to 0 in the DT | |
474 | */ | |
475 | if (hwid & ~MPIDR_HWID_BITMASK) { | |
476 | pr_err("%s: invalid reg property\n", dn->full_name); | |
477 | return INVALID_HWID; | |
478 | } | |
479 | return hwid; | |
480 | } | |
481 | ||
482 | /* | |
483 | * Duplicate MPIDRs are a recipe for disaster. Scan all initialized | |
484 | * entries and check for duplicates. If any is found just ignore the | |
485 | * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid | |
486 | * matching valid MPIDR values. | |
487 | */ | |
488 | static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid) | |
489 | { | |
490 | unsigned int i; | |
491 | ||
492 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) | |
493 | if (cpu_logical_map(i) == hwid) | |
494 | return true; | |
495 | return false; | |
496 | } | |
497 | ||
819a8826 LP |
498 | /* |
499 | * Initialize cpu operations for a logical cpu and | |
500 | * set it in the possible mask on success | |
501 | */ | |
502 | static int __init smp_cpu_setup(int cpu) | |
503 | { | |
504 | if (cpu_read_ops(cpu)) | |
505 | return -ENODEV; | |
506 | ||
507 | if (cpu_ops[cpu]->cpu_init(cpu)) | |
508 | return -ENODEV; | |
509 | ||
510 | set_cpu_possible(cpu, true); | |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
0f078336 LP |
515 | static bool bootcpu_valid __initdata; |
516 | static unsigned int cpu_count = 1; | |
517 | ||
518 | #ifdef CONFIG_ACPI | |
519 | /* | |
520 | * acpi_map_gic_cpu_interface - parse processor MADT entry | |
521 | * | |
522 | * Carry out sanity checks on MADT processor entry and initialize | |
523 | * cpu_logical_map on success | |
524 | */ | |
525 | static void __init | |
526 | acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) | |
527 | { | |
528 | u64 hwid = processor->arm_mpidr; | |
529 | ||
f9058929 HG |
530 | if (!(processor->flags & ACPI_MADT_ENABLED)) { |
531 | pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); | |
0f078336 LP |
532 | return; |
533 | } | |
534 | ||
f9058929 HG |
535 | if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { |
536 | pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); | |
0f078336 LP |
537 | return; |
538 | } | |
539 | ||
540 | if (is_mpidr_duplicate(cpu_count, hwid)) { | |
541 | pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); | |
542 | return; | |
543 | } | |
544 | ||
545 | /* Check if GICC structure of boot CPU is available in the MADT */ | |
546 | if (cpu_logical_map(0) == hwid) { | |
547 | if (bootcpu_valid) { | |
548 | pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n", | |
549 | hwid); | |
550 | return; | |
551 | } | |
552 | bootcpu_valid = true; | |
553 | return; | |
554 | } | |
555 | ||
556 | if (cpu_count >= NR_CPUS) | |
557 | return; | |
558 | ||
559 | /* map the logical cpu id to cpu MPIDR */ | |
560 | cpu_logical_map(cpu_count) = hwid; | |
561 | ||
5e89c55e LP |
562 | /* |
563 | * Set-up the ACPI parking protocol cpu entries | |
564 | * while initializing the cpu_logical_map to | |
565 | * avoid parsing MADT entries multiple times for | |
566 | * nothing (ie a valid cpu_logical_map entry should | |
567 | * contain a valid parking protocol data set to | |
568 | * initialize the cpu if the parking protocol is | |
569 | * the only available enable method). | |
570 | */ | |
571 | acpi_set_mailbox_entry(cpu_count, processor); | |
572 | ||
d8b47fca HG |
573 | early_map_cpu_to_node(cpu_count, acpi_numa_get_nid(cpu_count, hwid)); |
574 | ||
0f078336 LP |
575 | cpu_count++; |
576 | } | |
577 | ||
578 | static int __init | |
579 | acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header, | |
580 | const unsigned long end) | |
581 | { | |
582 | struct acpi_madt_generic_interrupt *processor; | |
583 | ||
584 | processor = (struct acpi_madt_generic_interrupt *)header; | |
99e3e3ae | 585 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
0f078336 LP |
586 | return -EINVAL; |
587 | ||
588 | acpi_table_print_madt_entry(header); | |
589 | ||
590 | acpi_map_gic_cpu_interface(processor); | |
591 | ||
592 | return 0; | |
593 | } | |
594 | #else | |
595 | #define acpi_table_parse_madt(...) do { } while (0) | |
596 | #endif | |
597 | ||
08e875c1 | 598 | /* |
4c7aa002 JM |
599 | * Enumerate the possible CPU set from the device tree and build the |
600 | * cpu logical map array containing MPIDR values related to logical | |
601 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 | 602 | */ |
29b8302b | 603 | static void __init of_parse_and_init_cpus(void) |
08e875c1 | 604 | { |
08e875c1 | 605 | struct device_node *dn = NULL; |
08e875c1 CM |
606 | |
607 | while ((dn = of_find_node_by_type(dn, "cpu"))) { | |
0f078336 | 608 | u64 hwid = of_get_cpu_mpidr(dn); |
4c7aa002 | 609 | |
0f078336 | 610 | if (hwid == INVALID_HWID) |
4c7aa002 | 611 | goto next; |
4c7aa002 | 612 | |
0f078336 LP |
613 | if (is_mpidr_duplicate(cpu_count, hwid)) { |
614 | pr_err("%s: duplicate cpu reg properties in the DT\n", | |
615 | dn->full_name); | |
4c7aa002 JM |
616 | goto next; |
617 | } | |
618 | ||
4c7aa002 JM |
619 | /* |
620 | * The numbering scheme requires that the boot CPU | |
621 | * must be assigned logical id 0. Record it so that | |
622 | * the logical map built from DT is validated and can | |
623 | * be used. | |
624 | */ | |
625 | if (hwid == cpu_logical_map(0)) { | |
626 | if (bootcpu_valid) { | |
627 | pr_err("%s: duplicate boot cpu reg property in DT\n", | |
628 | dn->full_name); | |
629 | goto next; | |
630 | } | |
631 | ||
632 | bootcpu_valid = true; | |
7ba5f605 | 633 | early_map_cpu_to_node(0, of_node_to_nid(dn)); |
4c7aa002 JM |
634 | |
635 | /* | |
636 | * cpu_logical_map has already been | |
637 | * initialized and the boot cpu doesn't need | |
638 | * the enable-method so continue without | |
639 | * incrementing cpu. | |
640 | */ | |
641 | continue; | |
642 | } | |
643 | ||
0f078336 | 644 | if (cpu_count >= NR_CPUS) |
08e875c1 CM |
645 | goto next; |
646 | ||
4c7aa002 | 647 | pr_debug("cpu logical map 0x%llx\n", hwid); |
0f078336 | 648 | cpu_logical_map(cpu_count) = hwid; |
1a2db300 GK |
649 | |
650 | early_map_cpu_to_node(cpu_count, of_node_to_nid(dn)); | |
08e875c1 | 651 | next: |
0f078336 | 652 | cpu_count++; |
08e875c1 | 653 | } |
0f078336 LP |
654 | } |
655 | ||
656 | /* | |
657 | * Enumerate the possible CPU set from the device tree or ACPI and build the | |
658 | * cpu logical map array containing MPIDR values related to logical | |
659 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
660 | */ | |
661 | void __init smp_init_cpus(void) | |
662 | { | |
663 | int i; | |
664 | ||
665 | if (acpi_disabled) | |
666 | of_parse_and_init_cpus(); | |
667 | else | |
668 | /* | |
669 | * do a walk of MADT to determine how many CPUs | |
670 | * we have including disabled CPUs, and get information | |
671 | * we need for SMP init | |
672 | */ | |
673 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
674 | acpi_parse_gic_cpu_interface, 0); | |
08e875c1 | 675 | |
50ee91bd KW |
676 | if (cpu_count > nr_cpu_ids) |
677 | pr_warn("Number of cores (%d) exceeds configured maximum of %d - clipping\n", | |
678 | cpu_count, nr_cpu_ids); | |
4c7aa002 JM |
679 | |
680 | if (!bootcpu_valid) { | |
0f078336 | 681 | pr_err("missing boot CPU MPIDR, not enabling secondaries\n"); |
4c7aa002 JM |
682 | return; |
683 | } | |
684 | ||
685 | /* | |
819a8826 LP |
686 | * We need to set the cpu_logical_map entries before enabling |
687 | * the cpus so that cpu processor description entries (DT cpu nodes | |
688 | * and ACPI MADT entries) can be retrieved by matching the cpu hwid | |
689 | * with entries in cpu_logical_map while initializing the cpus. | |
690 | * If the cpu set-up fails, invalidate the cpu_logical_map entry. | |
4c7aa002 | 691 | */ |
50ee91bd | 692 | for (i = 1; i < nr_cpu_ids; i++) { |
819a8826 LP |
693 | if (cpu_logical_map(i) != INVALID_HWID) { |
694 | if (smp_cpu_setup(i)) | |
695 | cpu_logical_map(i) = INVALID_HWID; | |
696 | } | |
697 | } | |
08e875c1 CM |
698 | } |
699 | ||
700 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
701 | { | |
cd1aebf5 | 702 | int err; |
44dbcc93 | 703 | unsigned int cpu; |
08e875c1 | 704 | |
f6e763b9 MB |
705 | init_cpu_topology(); |
706 | ||
707 | smp_store_cpu_info(smp_processor_id()); | |
708 | ||
e75118a7 SP |
709 | /* |
710 | * If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set | |
711 | * secondary CPUs present. | |
712 | */ | |
713 | if (max_cpus == 0) | |
714 | return; | |
715 | ||
08e875c1 CM |
716 | /* |
717 | * Initialise the present map (which describes the set of CPUs | |
718 | * actually populated at the present time) and release the | |
719 | * secondaries from the bootloader. | |
720 | */ | |
721 | for_each_possible_cpu(cpu) { | |
08e875c1 | 722 | |
d329de3f MZ |
723 | if (cpu == smp_processor_id()) |
724 | continue; | |
725 | ||
cd1aebf5 | 726 | if (!cpu_ops[cpu]) |
08e875c1 CM |
727 | continue; |
728 | ||
cd1aebf5 | 729 | err = cpu_ops[cpu]->cpu_prepare(cpu); |
d329de3f MZ |
730 | if (err) |
731 | continue; | |
08e875c1 CM |
732 | |
733 | set_cpu_present(cpu, true); | |
08e875c1 | 734 | } |
08e875c1 CM |
735 | } |
736 | ||
36310736 | 737 | void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
08e875c1 CM |
738 | |
739 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
740 | { | |
45ed695a | 741 | __smp_cross_call = fn; |
08e875c1 CM |
742 | } |
743 | ||
45ed695a NP |
744 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
745 | #define S(x,s) [x] = s | |
08e875c1 CM |
746 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), |
747 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
08e875c1 | 748 | S(IPI_CPU_STOP, "CPU stop interrupts"), |
1f85008e | 749 | S(IPI_TIMER, "Timer broadcast interrupts"), |
eb631bb5 | 750 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
5e89c55e | 751 | S(IPI_WAKEUP, "CPU wake-up interrupts"), |
08e875c1 CM |
752 | }; |
753 | ||
45ed695a NP |
754 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
755 | { | |
756 | trace_ipi_raise(target, ipi_types[ipinr]); | |
757 | __smp_cross_call(target, ipinr); | |
758 | } | |
759 | ||
08e875c1 CM |
760 | void show_ipi_list(struct seq_file *p, int prec) |
761 | { | |
762 | unsigned int cpu, i; | |
763 | ||
764 | for (i = 0; i < NR_IPI; i++) { | |
45ed695a | 765 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, |
08e875c1 | 766 | prec >= 4 ? " " : ""); |
67317c26 | 767 | for_each_online_cpu(cpu) |
08e875c1 CM |
768 | seq_printf(p, "%10u ", |
769 | __get_irq_stat(cpu, ipi_irqs[i])); | |
770 | seq_printf(p, " %s\n", ipi_types[i]); | |
771 | } | |
772 | } | |
773 | ||
774 | u64 smp_irq_stat_cpu(unsigned int cpu) | |
775 | { | |
776 | u64 sum = 0; | |
777 | int i; | |
778 | ||
779 | for (i = 0; i < NR_IPI; i++) | |
780 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
781 | ||
782 | return sum; | |
783 | } | |
784 | ||
45ed695a NP |
785 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
786 | { | |
787 | smp_cross_call(mask, IPI_CALL_FUNC); | |
788 | } | |
789 | ||
790 | void arch_send_call_function_single_ipi(int cpu) | |
791 | { | |
0aaf0dae | 792 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
45ed695a NP |
793 | } |
794 | ||
5e89c55e LP |
795 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
796 | void arch_send_wakeup_ipi_mask(const struct cpumask *mask) | |
797 | { | |
798 | smp_cross_call(mask, IPI_WAKEUP); | |
799 | } | |
800 | #endif | |
801 | ||
45ed695a NP |
802 | #ifdef CONFIG_IRQ_WORK |
803 | void arch_irq_work_raise(void) | |
804 | { | |
805 | if (__smp_cross_call) | |
806 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); | |
807 | } | |
808 | #endif | |
809 | ||
08e875c1 CM |
810 | /* |
811 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
812 | */ | |
813 | static void ipi_cpu_stop(unsigned int cpu) | |
814 | { | |
08e875c1 CM |
815 | set_cpu_online(cpu, false); |
816 | ||
08e875c1 CM |
817 | local_irq_disable(); |
818 | ||
819 | while (1) | |
820 | cpu_relax(); | |
821 | } | |
822 | ||
823 | /* | |
824 | * Main handler for inter-processor interrupts | |
825 | */ | |
826 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
827 | { | |
828 | unsigned int cpu = smp_processor_id(); | |
829 | struct pt_regs *old_regs = set_irq_regs(regs); | |
830 | ||
45ed695a | 831 | if ((unsigned)ipinr < NR_IPI) { |
be081d9b | 832 | trace_ipi_entry_rcuidle(ipi_types[ipinr]); |
45ed695a NP |
833 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); |
834 | } | |
08e875c1 CM |
835 | |
836 | switch (ipinr) { | |
837 | case IPI_RESCHEDULE: | |
838 | scheduler_ipi(); | |
839 | break; | |
840 | ||
841 | case IPI_CALL_FUNC: | |
842 | irq_enter(); | |
843 | generic_smp_call_function_interrupt(); | |
844 | irq_exit(); | |
845 | break; | |
846 | ||
08e875c1 CM |
847 | case IPI_CPU_STOP: |
848 | irq_enter(); | |
849 | ipi_cpu_stop(cpu); | |
850 | irq_exit(); | |
851 | break; | |
852 | ||
1f85008e LP |
853 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
854 | case IPI_TIMER: | |
855 | irq_enter(); | |
856 | tick_receive_broadcast(); | |
857 | irq_exit(); | |
858 | break; | |
859 | #endif | |
860 | ||
eb631bb5 LB |
861 | #ifdef CONFIG_IRQ_WORK |
862 | case IPI_IRQ_WORK: | |
863 | irq_enter(); | |
864 | irq_work_run(); | |
865 | irq_exit(); | |
866 | break; | |
867 | #endif | |
868 | ||
5e89c55e LP |
869 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
870 | case IPI_WAKEUP: | |
871 | WARN_ONCE(!acpi_parking_protocol_valid(cpu), | |
872 | "CPU%u: Wake-up IPI outside the ACPI parking protocol\n", | |
873 | cpu); | |
874 | break; | |
875 | #endif | |
876 | ||
08e875c1 CM |
877 | default: |
878 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
879 | break; | |
880 | } | |
45ed695a NP |
881 | |
882 | if ((unsigned)ipinr < NR_IPI) | |
be081d9b | 883 | trace_ipi_exit_rcuidle(ipi_types[ipinr]); |
08e875c1 CM |
884 | set_irq_regs(old_regs); |
885 | } | |
886 | ||
887 | void smp_send_reschedule(int cpu) | |
888 | { | |
889 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
890 | } | |
891 | ||
1f85008e LP |
892 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
893 | void tick_broadcast(const struct cpumask *mask) | |
894 | { | |
895 | smp_cross_call(mask, IPI_TIMER); | |
896 | } | |
897 | #endif | |
898 | ||
08e875c1 CM |
899 | void smp_send_stop(void) |
900 | { | |
901 | unsigned long timeout; | |
902 | ||
903 | if (num_online_cpus() > 1) { | |
904 | cpumask_t mask; | |
905 | ||
906 | cpumask_copy(&mask, cpu_online_mask); | |
434ed7f4 | 907 | cpumask_clear_cpu(smp_processor_id(), &mask); |
08e875c1 | 908 | |
82611c14 JG |
909 | if (system_state == SYSTEM_BOOTING || |
910 | system_state == SYSTEM_RUNNING) | |
911 | pr_crit("SMP: stopping secondary CPUs\n"); | |
08e875c1 CM |
912 | smp_cross_call(&mask, IPI_CPU_STOP); |
913 | } | |
914 | ||
915 | /* Wait up to one second for other CPUs to stop */ | |
916 | timeout = USEC_PER_SEC; | |
917 | while (num_online_cpus() > 1 && timeout--) | |
918 | udelay(1); | |
919 | ||
920 | if (num_online_cpus() > 1) | |
82611c14 JG |
921 | pr_warning("SMP: failed to stop secondary CPUs %*pbl\n", |
922 | cpumask_pr_args(cpu_online_mask)); | |
08e875c1 CM |
923 | } |
924 | ||
925 | /* | |
926 | * not supported here | |
927 | */ | |
928 | int setup_profiling_timer(unsigned int multiplier) | |
929 | { | |
930 | return -EINVAL; | |
931 | } | |
5c492c3f JM |
932 | |
933 | static bool have_cpu_die(void) | |
934 | { | |
935 | #ifdef CONFIG_HOTPLUG_CPU | |
936 | int any_cpu = raw_smp_processor_id(); | |
937 | ||
938 | if (cpu_ops[any_cpu]->cpu_die) | |
939 | return true; | |
940 | #endif | |
941 | return false; | |
942 | } | |
943 | ||
944 | bool cpus_are_stuck_in_kernel(void) | |
945 | { | |
946 | bool smp_spin_tables = (num_possible_cpus() > 1 && !have_cpu_die()); | |
947 | ||
948 | return !!cpus_stuck_in_kernel || smp_spin_tables; | |
949 | } |