[deliverable/linux.git] / arch / arm64 / mm / proc.S

/*
 * Based on arch/arm/mm/proc.S
 *
 * Copyright (C) 2001 Deep Blue Solutions Ltd.
 * Copyright (C) 2012 ARM Ltd.
 * Author: Catalin Marinas <catalin.marinas@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#ifndef CONFIG_SMP
/* PTWs cacheable, inner/outer WBWA not shareable */
#define TCR_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
#else
/* PTWs cacheable, inner/outer WBWA shareable */
#define TCR_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_SHARED
#endif

#define MAIR(attr, mt)	((attr) << ((mt) * 8))

/*
 *	cpu_cache_off()
 *
 *	Turn the CPU D-cache off.
 */
ENTRY(cpu_cache_off)
	mrs	x0, sctlr_el1
	bic	x0, x0, #1 << 2			// clear SCTLR.C
	msr	sctlr_el1, x0
	isb
	ret
ENDPROC(cpu_cache_off)

/*
 *	cpu_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the same state
 *	as it would be if it had been reset, and branch to what would be the
 *	reset vector. It must be executed with the flat identity mapping.
 *
 *	- loc   - location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_reset)
	mrs	x1, sctlr_el1
	bic	x1, x1, #1
	msr	sctlr_el1, x1			// disable the MMU
	isb
	ret	x0
ENDPROC(cpu_reset)

/*
 *	cpu_do_idle()
 *
 *	Idle the processor (wait for interrupt).
 */
ENTRY(cpu_do_idle)
	dsb	sy				// WFI may enter a low-power mode
	wfi
	ret
ENDPROC(cpu_do_idle)

#ifdef CONFIG_ARM64_CPU_SUSPEND
/**
 * cpu_do_suspend - save CPU registers context
 *
 * x0: virtual address of context pointer
 */
ENTRY(cpu_do_suspend)
	mrs	x2, tpidr_el0
	mrs	x3, tpidrro_el0
	mrs	x4, contextidr_el1
	mrs	x5, mair_el1
	mrs	x6, cpacr_el1
	mrs	x7, ttbr1_el1
	mrs	x8, tcr_el1
	mrs	x9, vbar_el1
	mrs	x10, mdscr_el1
	mrs	x11, oslsr_el1
	mrs	x12, sctlr_el1
	stp	x2, x3, [x0]
	stp	x4, x5, [x0, #16]
	stp	x6, x7, [x0, #32]
	stp	x8, x9, [x0, #48]
	stp	x10, x11, [x0, #64]
	str	x12, [x0, #80]
	ret
ENDPROC(cpu_do_suspend)

/**
 * cpu_do_resume - restore CPU register context
 *
 * x0: Physical address of context pointer
 * x1: ttbr0_el1 to be restored
 *
 * Returns:
 *	sctlr_el1 value in x0
 */
ENTRY(cpu_do_resume)
	/*
	 * Invalidate local tlb entries before turning on MMU
	 */
	tlbi	vmalle1
	ldp	x2, x3, [x0]
	ldp	x4, x5, [x0, #16]
	ldp	x6, x7, [x0, #32]
	ldp	x8, x9, [x0, #48]
	ldp	x10, x11, [x0, #64]
	ldr	x12, [x0, #80]
	msr	tpidr_el0, x2
	msr	tpidrro_el0, x3
	msr	contextidr_el1, x4
	msr	mair_el1, x5
	msr	cpacr_el1, x6
	msr	ttbr0_el1, x1
	msr	ttbr1_el1, x7
	msr	tcr_el1, x8
	msr	vbar_el1, x9
	msr	mdscr_el1, x10
	/*
	 * Restore oslsr_el1 by writing oslar_el1
	 */
	ubfx	x11, x11, #1, #1
	msr	oslar_el1, x11
	mov	x0, x12
	dsb	nsh		// Make sure local tlb invalidation completed
	isb
	ret
ENDPROC(cpu_do_resume)
#endif

/*
 *	cpu_do_switch_mm(pgd_phys, tsk)
 *
 *	Set the translation table base pointer to be pgd_phys.
 *
 *	- pgd_phys - physical address of new TTB
 */
ENTRY(cpu_do_switch_mm)
	mmid	w1, x1				// get mm->context.id
	bfi	x0, x1, #48, #16		// set the ASID
	msr	ttbr0_el1, x0			// set TTBR0
	isb
	ret
ENDPROC(cpu_do_switch_mm)

	.section ".text.init", #alloc, #execinstr

/*
 *	__cpu_setup
 *
 *	Initialise the processor for turning the MMU on.  Return in x0 the
 *	value of the SCTLR_EL1 register.
 */
ENTRY(__cpu_setup)
	ic	iallu				// I+BTB cache invalidate
	tlbi	vmalle1is			// invalidate I + D TLBs
	dsb	sy

	mov	x0, #3 << 20
	msr	cpacr_el1, x0			// Enable FP/ASIMD
	msr	mdscr_el1, xzr			// Reset mdscr_el1
	/*
	 * Memory region attributes for LPAE:
	 *
	 *   n = AttrIndx[2:0]
	 *			n	MAIR
	 *   DEVICE_nGnRnE	000	00000000
	 *   DEVICE_nGnRE	001	00000100
	 *   DEVICE_GRE		010	00001100
	 *   NORMAL_NC		011	01000100
	 *   NORMAL		100	11111111
	 */
	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
		     MAIR(0x04, MT_DEVICE_nGnRE) | \
		     MAIR(0x0c, MT_DEVICE_GRE) | \
		     MAIR(0x44, MT_NORMAL_NC) | \
		     MAIR(0xff, MT_NORMAL)
	msr	mair_el1, x5
	/*
	 * Prepare SCTLR
	 */
	adr	x5, crval
	ldp	w5, w6, [x5]
	mrs	x0, sctlr_el1
	bic	x0, x0, x5			// clear bits
	orr	x0, x0, x6			// set bits
	/*
	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
	 * both user and kernel.
	 */
	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | \
		      TCR_ASID16 | TCR_TBI0 | (1 << 31)
	/*
	 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
	 * TCR_EL1.
	 */
	mrs	x9, ID_AA64MMFR0_EL1
	bfi	x10, x9, #32, #3
#ifdef CONFIG_ARM64_64K_PAGES
	orr	x10, x10, TCR_TG0_64K
	orr	x10, x10, TCR_TG1_64K
#endif
	msr	tcr_el1, x10
	ret					// return to head.S
ENDPROC(__cpu_setup)

	/*
	 *                 n n            T
	 *       U E      WT T UD     US IHBS
	 *       CE0      XWHW CZ     ME TEEA S
	 * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
	 * 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
	 * .... .1.. .... 01.1 11.1 ..01 0001 1101 < software settings
	 */
	.type	crval, #object
crval:
	.word	0x000802e2			// clear
	.word	0x0405d11d			// set
Commit	Line	Data
9cce7a43 CM	1	/*
	2	* Based on arch/arm/mm/proc.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	* Copyright (C) 2012 ARM Ltd.
	6	* Author: Catalin Marinas <catalin.marinas@arm.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <linux/init.h>
	22	#include <linux/linkage.h>
	23	#include <asm/assembler.h>
	24	#include <asm/asm-offsets.h>
	25	#include <asm/hwcap.h>
	26	#include <asm/pgtable-hwdef.h>
	27	#include <asm/pgtable.h>
	28
	29	#include "proc-macros.S"
	30
	31	#ifndef CONFIG_SMP
	32	/* PTWs cacheable, inner/outer WBWA not shareable */
	33	#define TCR_FLAGS TCR_IRGN_WBWA \| TCR_ORGN_WBWA
	34	#else
	35	/* PTWs cacheable, inner/outer WBWA shareable */
	36	#define TCR_FLAGS TCR_IRGN_WBWA \| TCR_ORGN_WBWA \| TCR_SHARED
	37	#endif
	38
	39	#define MAIR(attr, mt) ((attr) << ((mt) * 8))
	40
	41	/*
	42	* cpu_cache_off()
	43	*
	44	* Turn the CPU D-cache off.
	45	*/
	46	ENTRY(cpu_cache_off)
	47	mrs x0, sctlr_el1
	48	bic x0, x0, #1 << 2 // clear SCTLR.C
	49	msr sctlr_el1, x0
	50	isb
	51	ret
	52	ENDPROC(cpu_cache_off)
	53
	54	/*
	55	* cpu_reset(loc)
	56	*
	57	* Perform a soft reset of the system. Put the CPU into the same state
	58	* as it would be if it had been reset, and branch to what would be the
	59	* reset vector. It must be executed with the flat identity mapping.
	60	*
	61	* - loc - location to jump to for soft reset
	62	*/
	63	.align 5
	64	ENTRY(cpu_reset)
65	mrs x1, sctlr_el1
66	bic x1, x1, #1
67	msr sctlr_el1, x1 // disable the MMU
68	isb
69	ret x0
70	ENDPROC(cpu_reset)
71
72	/*
73	* cpu_do_idle()
74	*
75	* Idle the processor (wait for interrupt).
76	*/
77	ENTRY(cpu_do_idle)
78	dsb sy // WFI may enter a low-power mode
79	wfi
80	ret
81	ENDPROC(cpu_do_idle)
82
6732bc65 LP	83	#ifdef CONFIG_ARM64_CPU_SUSPEND
	84	/**
	85	* cpu_do_suspend - save CPU registers context
	86	*
	87	* x0: virtual address of context pointer
	88	*/
	89	ENTRY(cpu_do_suspend)
	90	mrs x2, tpidr_el0
	91	mrs x3, tpidrro_el0
	92	mrs x4, contextidr_el1
	93	mrs x5, mair_el1
	94	mrs x6, cpacr_el1
	95	mrs x7, ttbr1_el1
	96	mrs x8, tcr_el1
	97	mrs x9, vbar_el1
	98	mrs x10, mdscr_el1
	99	mrs x11, oslsr_el1
	100	mrs x12, sctlr_el1
	101	stp x2, x3, [x0]
	102	stp x4, x5, [x0, #16]
	103	stp x6, x7, [x0, #32]
	104	stp x8, x9, [x0, #48]
	105	stp x10, x11, [x0, #64]
	106	str x12, [x0, #80]
	107	ret
	108	ENDPROC(cpu_do_suspend)
	109
	110	/**
	111	* cpu_do_resume - restore CPU register context
	112	*
	113	* x0: Physical address of context pointer
	114	* x1: ttbr0_el1 to be restored
	115	*
	116	* Returns:
	117	* sctlr_el1 value in x0
	118	*/
	119	ENTRY(cpu_do_resume)
	120	/*
	121	* Invalidate local tlb entries before turning on MMU
	122	*/
	123	tlbi vmalle1
	124	ldp x2, x3, [x0]
	125	ldp x4, x5, [x0, #16]
	126	ldp x6, x7, [x0, #32]
	127	ldp x8, x9, [x0, #48]
	128	ldp x10, x11, [x0, #64]
	129	ldr x12, [x0, #80]
	130	msr tpidr_el0, x2
	131	msr tpidrro_el0, x3
	132	msr contextidr_el1, x4
	133	msr mair_el1, x5
	134	msr cpacr_el1, x6
	135	msr ttbr0_el1, x1
	136	msr ttbr1_el1, x7
	137	msr tcr_el1, x8
	138	msr vbar_el1, x9
	139	msr mdscr_el1, x10
	140	/*
	141	* Restore oslsr_el1 by writing oslar_el1
	142	*/
	143	ubfx x11, x11, #1, #1
	144	msr oslar_el1, x11
	145	mov x0, x12
	146	dsb nsh // Make sure local tlb invalidation completed
147	isb
148	ret
149	ENDPROC(cpu_do_resume)
150	#endif
151
9cce7a43	152	/*
812944e9	153	* cpu_do_switch_mm(pgd_phys, tsk)
9cce7a43 CM	154	*
	155	* Set the translation table base pointer to be pgd_phys.
	156	*
	157	* - pgd_phys - physical address of new TTB
	158	*/
	159	ENTRY(cpu_do_switch_mm)
	160	mmid w1, x1 // get mm->context.id
	161	bfi x0, x1, #48, #16 // set the ASID
	162	msr ttbr0_el1, x0 // set TTBR0
	163	isb
	164	ret
	165	ENDPROC(cpu_do_switch_mm)
	166
9cce7a43 CM	167	.section ".text.init", #alloc, #execinstr
	168
	169	/*
	170	* __cpu_setup
	171	*
	172	* Initialise the processor for turning the MMU on. Return in x0 the
	173	* value of the SCTLR_EL1 register.
	174	*/
	175	ENTRY(__cpu_setup)
9cce7a43	176	ic iallu // I+BTB cache invalidate
3cea71bc	177	tlbi vmalle1is // invalidate I + D TLBs
9cce7a43 CM	178	dsb sy
	179
	180	mov x0, #3 << 20
	181	msr cpacr_el1, x0 // Enable FP/ASIMD
9c413e25	182	msr mdscr_el1, xzr // Reset mdscr_el1
9cce7a43 CM	183	/*
	184	* Memory region attributes for LPAE:
	185	*
	186	* n = AttrIndx[2:0]
	187	* n MAIR
	188	* DEVICE_nGnRnE 000 00000000
	189	* DEVICE_nGnRE 001 00000100
	190	* DEVICE_GRE 010 00001100
	191	* NORMAL_NC 011 01000100
	192	* NORMAL 100 11111111
	193	*/
	194	ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) \| \
	195	MAIR(0x04, MT_DEVICE_nGnRE) \| \
	196	MAIR(0x0c, MT_DEVICE_GRE) \| \
	197	MAIR(0x44, MT_NORMAL_NC) \| \
	198	MAIR(0xff, MT_NORMAL)
	199	msr mair_el1, x5
	200	/*
	201	* Prepare SCTLR
	202	*/
	203	adr x5, crval
	204	ldp w5, w6, [x5]
	205	mrs x0, sctlr_el1
	206	bic x0, x0, x5 // clear bits
	207	orr x0, x0, x6 // set bits
	208	/*
	209	* Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
	210	* both user and kernel.
	211	*/
87366d8c	212	ldr x10, =TCR_TxSZ(VA_BITS) \| TCR_FLAGS \| \
d50240a5	213	TCR_ASID16 \| TCR_TBI0 \| (1 << 31)
87366d8c RMC	214	/*
	215	* Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
	216	* TCR_EL1.
	217	*/
	218	mrs x9, ID_AA64MMFR0_EL1
	219	bfi x10, x9, #32, #3
9cce7a43 CM	220	#ifdef CONFIG_ARM64_64K_PAGES
	221	orr x10, x10, TCR_TG0_64K
	222	orr x10, x10, TCR_TG1_64K
	223	#endif
	224	msr tcr_el1, x10
	225	ret // return to head.S
	226	ENDPROC(__cpu_setup)
	227
	228	/*
	229	* n n T
	230	* U E WT T UD US IHBS
	231	* CE0 XWHW CZ ME TEEA S
	232	* .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
	233	* 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
9cf71728	234	* .... .1.. .... 01.1 11.1 ..01 0001 1101 < software settings
9cce7a43 CM	235	*/
	236	.type crval, #object
	237	crval:
9cf71728	238	.word 0x000802e2 // clear
9cce7a43	239	.word 0x0405d11d // set