[deliverable/linux.git] / arch / avr32 / kernel / cpu.c

/*
 * Copyright (C) 2005-2006 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/device.h>
#include <linux/seq_file.h>
#include <linux/cpu.h>
#include <linux/module.h>
#include <linux/percpu.h>
#include <linux/param.h>
#include <linux/errno.h>
#include <linux/clk.h>

#include <asm/setup.h>
#include <asm/sysreg.h>

static DEFINE_PER_CPU(struct cpu, cpu_devices);

#ifdef CONFIG_PERFORMANCE_COUNTERS

/*
 * XXX: If/when a SMP-capable implementation of AVR32 will ever be
 * made, we must make sure that the code executes on the correct CPU.
 */
static ssize_t show_pc0event(struct device *dev,
			struct device_attribute *attr, char *buf)
{
	unsigned long pccr;

	pccr = sysreg_read(PCCR);
	return sprintf(buf, "0x%lx\n", (pccr >> 12) & 0x3f);
}
static ssize_t store_pc0event(struct device *dev,
			struct device_attribute *attr, const char *buf,
			      size_t count)
{
	unsigned long val;
	char *endp;

	val = simple_strtoul(buf, &endp, 0);
	if (endp == buf || val > 0x3f)
		return -EINVAL;
	val = (val << 12) | (sysreg_read(PCCR) & 0xfffc0fff);
	sysreg_write(PCCR, val);
	return count;
}
static ssize_t show_pc0count(struct device *dev,
			struct device_attribute *attr, char *buf)
{
	unsigned long pcnt0;

	pcnt0 = sysreg_read(PCNT0);
	return sprintf(buf, "%lu\n", pcnt0);
}
static ssize_t store_pc0count(struct device *dev,
				struct device_attribute *attr,
				const char *buf, size_t count)
{
	unsigned long val;
	char *endp;

	val = simple_strtoul(buf, &endp, 0);
	if (endp == buf)
		return -EINVAL;
	sysreg_write(PCNT0, val);

	return count;
}

static ssize_t show_pc1event(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	unsigned long pccr;

	pccr = sysreg_read(PCCR);
	return sprintf(buf, "0x%lx\n", (pccr >> 18) & 0x3f);
}
static ssize_t store_pc1event(struct device *dev,
			      struct device_attribute *attr, const char *buf,
			      size_t count)
{
	unsigned long val;
	char *endp;

	val = simple_strtoul(buf, &endp, 0);
	if (endp == buf || val > 0x3f)
		return -EINVAL;
	val = (val << 18) | (sysreg_read(PCCR) & 0xff03ffff);
	sysreg_write(PCCR, val);
	return count;
}
static ssize_t show_pc1count(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	unsigned long pcnt1;

	pcnt1 = sysreg_read(PCNT1);
	return sprintf(buf, "%lu\n", pcnt1);
}
static ssize_t store_pc1count(struct device *dev,
				struct device_attribute *attr, const char *buf,
			      size_t count)
{
	unsigned long val;
	char *endp;

	val = simple_strtoul(buf, &endp, 0);
	if (endp == buf)
		return -EINVAL;
	sysreg_write(PCNT1, val);

	return count;
}

static ssize_t show_pccycles(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	unsigned long pccnt;

	pccnt = sysreg_read(PCCNT);
	return sprintf(buf, "%lu\n", pccnt);
}
static ssize_t store_pccycles(struct device *dev,
				struct device_attribute *attr, const char *buf,
			      size_t count)
{
	unsigned long val;
	char *endp;

	val = simple_strtoul(buf, &endp, 0);
	if (endp == buf)
		return -EINVAL;
	sysreg_write(PCCNT, val);

	return count;
}

static ssize_t show_pcenable(struct device *dev,
			struct device_attribute *attr, char *buf)
{
	unsigned long pccr;

	pccr = sysreg_read(PCCR);
	return sprintf(buf, "%c\n", (pccr & 1)?'1':'0');
}
static ssize_t store_pcenable(struct device *dev,
			      struct device_attribute *attr, const char *buf,
			      size_t count)
{
	unsigned long pccr, val;
	char *endp;

	val = simple_strtoul(buf, &endp, 0);
	if (endp == buf)
		return -EINVAL;
	if (val)
		val = 1;

	pccr = sysreg_read(PCCR);
	pccr = (pccr & ~1UL) | val;
	sysreg_write(PCCR, pccr);

	return count;
}

static DEVICE_ATTR(pc0event, 0600, show_pc0event, store_pc0event);
static DEVICE_ATTR(pc0count, 0600, show_pc0count, store_pc0count);
static DEVICE_ATTR(pc1event, 0600, show_pc1event, store_pc1event);
static DEVICE_ATTR(pc1count, 0600, show_pc1count, store_pc1count);
static DEVICE_ATTR(pccycles, 0600, show_pccycles, store_pccycles);
static DEVICE_ATTR(pcenable, 0600, show_pcenable, store_pcenable);

#endif /* CONFIG_PERFORMANCE_COUNTERS */

static int __init topology_init(void)
{
	int cpu;

	for_each_possible_cpu(cpu) {
		struct cpu *c = &per_cpu(cpu_devices, cpu);

		register_cpu(c, cpu);

#ifdef CONFIG_PERFORMANCE_COUNTERS
		device_create_file(&c->dev, &dev_attr_pc0event);
		device_create_file(&c->dev, &dev_attr_pc0count);
		device_create_file(&c->dev, &dev_attr_pc1event);
		device_create_file(&c->dev, &dev_attr_pc1count);
		device_create_file(&c->dev, &dev_attr_pccycles);
		device_create_file(&c->dev, &dev_attr_pcenable);
#endif
	}

	return 0;
}

subsys_initcall(topology_init);

struct chip_id_map {
	u16	mid;
	u16	pn;
	const char *name;
};

static const struct chip_id_map chip_names[] = {
	{ .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
};
#define NR_CHIP_NAMES ARRAY_SIZE(chip_names)

static const char *cpu_names[] = {
	"Morgan",
	"AP7",
};
#define NR_CPU_NAMES ARRAY_SIZE(cpu_names)

static const char *arch_names[] = {
	"AVR32A",
	"AVR32B",
};
#define NR_ARCH_NAMES ARRAY_SIZE(arch_names)

static const char *mmu_types[] = {
	"No MMU",
	"ITLB and DTLB",
	"Shared TLB",
	"MPU"
};

static const char *cpu_feature_flags[] = {
	"rmw", "dsp", "simd", "ocd", "perfctr", "java", "fpu",
};

static const char *get_chip_name(struct avr32_cpuinfo *cpu)
{
	unsigned int i;
	unsigned int mid = avr32_get_manufacturer_id(cpu);
	unsigned int pn = avr32_get_product_number(cpu);

	for (i = 0; i < NR_CHIP_NAMES; i++) {
		if (chip_names[i].mid == mid && chip_names[i].pn == pn)
			return chip_names[i].name;
	}

	return "(unknown)";
}

void __init setup_processor(void)
{
	unsigned long config0, config1;
	unsigned long features;
	unsigned cpu_id, cpu_rev, arch_id, arch_rev, mmu_type;
	unsigned device_id;
	unsigned tmp;
	unsigned i;

	config0 = sysreg_read(CONFIG0);
	config1 = sysreg_read(CONFIG1);
	cpu_id = SYSREG_BFEXT(PROCESSORID, config0);
	cpu_rev = SYSREG_BFEXT(PROCESSORREVISION, config0);
	arch_id = SYSREG_BFEXT(AT, config0);
	arch_rev = SYSREG_BFEXT(AR, config0);
	mmu_type = SYSREG_BFEXT(MMUT, config0);

	device_id = ocd_read(DID);

	boot_cpu_data.arch_type = arch_id;
	boot_cpu_data.cpu_type = cpu_id;
	boot_cpu_data.arch_revision = arch_rev;
	boot_cpu_data.cpu_revision = cpu_rev;
	boot_cpu_data.tlb_config = mmu_type;
	boot_cpu_data.device_id = device_id;

	tmp = SYSREG_BFEXT(ILSZ, config1);
	if (tmp) {
		boot_cpu_data.icache.ways = 1 << SYSREG_BFEXT(IASS, config1);
		boot_cpu_data.icache.sets = 1 << SYSREG_BFEXT(ISET, config1);
		boot_cpu_data.icache.linesz = 1 << (tmp + 1);
	}
	tmp = SYSREG_BFEXT(DLSZ, config1);
	if (tmp) {
		boot_cpu_data.dcache.ways = 1 << SYSREG_BFEXT(DASS, config1);
		boot_cpu_data.dcache.sets = 1 << SYSREG_BFEXT(DSET, config1);
		boot_cpu_data.dcache.linesz = 1 << (tmp + 1);
	}

	if ((cpu_id >= NR_CPU_NAMES) || (arch_id >= NR_ARCH_NAMES)) {
		printk ("Unknown CPU configuration (ID %02x, arch %02x), "
			"continuing anyway...\n",
			cpu_id, arch_id);
		return;
	}

	printk ("CPU: %s chip revision %c\n", get_chip_name(&boot_cpu_data),
			avr32_get_chip_revision(&boot_cpu_data) + 'A');
	printk ("CPU: %s [%02x] core revision %d (%s arch revision %d)\n",
		cpu_names[cpu_id], cpu_id, cpu_rev,
		arch_names[arch_id], arch_rev);
	printk ("CPU: MMU configuration: %s\n", mmu_types[mmu_type]);

	printk ("CPU: features:");
	features = 0;
	if (config0 & SYSREG_BIT(CONFIG0_R))
		features |= AVR32_FEATURE_RMW;
	if (config0 & SYSREG_BIT(CONFIG0_D))
		features |= AVR32_FEATURE_DSP;
	if (config0 & SYSREG_BIT(CONFIG0_S))
		features |= AVR32_FEATURE_SIMD;
	if (config0 & SYSREG_BIT(CONFIG0_O))
		features |= AVR32_FEATURE_OCD;
	if (config0 & SYSREG_BIT(CONFIG0_P))
		features |= AVR32_FEATURE_PCTR;
	if (config0 & SYSREG_BIT(CONFIG0_J))
		features |= AVR32_FEATURE_JAVA;
	if (config0 & SYSREG_BIT(CONFIG0_F))
		features |= AVR32_FEATURE_FPU;

	for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
		if (features & (1 << i))
			printk(" %s", cpu_feature_flags[i]);

	printk("\n");
	boot_cpu_data.features = features;
}

#ifdef CONFIG_PROC_FS
static int c_show(struct seq_file *m, void *v)
{
	unsigned int icache_size, dcache_size;
	unsigned int cpu = smp_processor_id();
	unsigned int freq;
	unsigned int i;

	icache_size = boot_cpu_data.icache.ways *
		boot_cpu_data.icache.sets *
		boot_cpu_data.icache.linesz;
	dcache_size = boot_cpu_data.dcache.ways *
		boot_cpu_data.dcache.sets *
		boot_cpu_data.dcache.linesz;

	seq_printf(m, "processor\t: %d\n", cpu);

	seq_printf(m, "chip type\t: %s revision %c\n",
			get_chip_name(&boot_cpu_data),
			avr32_get_chip_revision(&boot_cpu_data) + 'A');
	if (boot_cpu_data.arch_type < NR_ARCH_NAMES)
		seq_printf(m, "cpu arch\t: %s revision %d\n",
			   arch_names[boot_cpu_data.arch_type],
			   boot_cpu_data.arch_revision);
	if (boot_cpu_data.cpu_type < NR_CPU_NAMES)
		seq_printf(m, "cpu core\t: %s revision %d\n",
			   cpu_names[boot_cpu_data.cpu_type],
			   boot_cpu_data.cpu_revision);

	freq = (clk_get_rate(boot_cpu_data.clk) + 500) / 1000;
	seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, freq % 1000);

	seq_printf(m, "i-cache\t\t: %dK (%u ways x %u sets x %u)\n",
		   icache_size >> 10,
		   boot_cpu_data.icache.ways,
		   boot_cpu_data.icache.sets,
		   boot_cpu_data.icache.linesz);
	seq_printf(m, "d-cache\t\t: %dK (%u ways x %u sets x %u)\n",
		   dcache_size >> 10,
		   boot_cpu_data.dcache.ways,
		   boot_cpu_data.dcache.sets,
		   boot_cpu_data.dcache.linesz);

	seq_printf(m, "features\t:");
	for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
		if (boot_cpu_data.features & (1 << i))
			seq_printf(m, " %s", cpu_feature_flags[i]);

	seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
		   boot_cpu_data.loops_per_jiffy / (500000/HZ),
		   (boot_cpu_data.loops_per_jiffy / (5000/HZ)) % 100);

	return 0;
}

static void *c_start(struct seq_file *m, loff_t *pos)
{
	return *pos < 1 ? (void *)1 : NULL;
}

static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
	++*pos;
	return NULL;
}

static void c_stop(struct seq_file *m, void *v)
{

}

const struct seq_operations cpuinfo_op = {
	.start	= c_start,
	.next	= c_next,
	.stop	= c_stop,
	.show	= c_show
};
#endif /* CONFIG_PROC_FS */
Commit	Line	Data
5f97f7f9 HS	1	/*
	2	* Copyright (C) 2005-2006 Atmel Corporation
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8	#include <linux/init.h>
8a25a2fd	9	#include <linux/device.h>
5f97f7f9 HS	10	#include <linux/seq_file.h>
5f97f7f9 HS	11	#include <linux/cpu.h>
4ffabefb	12	#include <linux/module.h>
5f97f7f9 HS	13	#include <linux/percpu.h>
	14	#include <linux/param.h>
	15	#include <linux/errno.h>
281ef58c	16	#include <linux/clk.h>
5f97f7f9 HS	17
	18	#include <asm/setup.h>
	19	#include <asm/sysreg.h>
	20
	21	static DEFINE_PER_CPU(struct cpu, cpu_devices);
	22
	23	#ifdef CONFIG_PERFORMANCE_COUNTERS
	24
	25	/*
	26	* XXX: If/when a SMP-capable implementation of AVR32 will ever be
	27	* made, we must make sure that the code executes on the correct CPU.
	28	*/
8a25a2fd KS	29	static ssize_t show_pc0event(struct device *dev,
8a25a2fd KS	30	struct device_attribute attr, char buf)
5f97f7f9 HS	31	{
	32	unsigned long pccr;
	33
	34	pccr = sysreg_read(PCCR);
	35	return sprintf(buf, "0x%lx\n", (pccr >> 12) & 0x3f);
	36	}
8a25a2fd KS	37	static ssize_t store_pc0event(struct device *dev,
8a25a2fd KS	38	struct device_attribute attr, const char buf,
5f97f7f9 HS	39	size_t count)
	40	{
	41	unsigned long val;
	42	char *endp;
	43
	44	val = simple_strtoul(buf, &endp, 0);
	45	if (endp == buf \|\| val > 0x3f)
	46	return -EINVAL;
	47	val = (val << 12) \| (sysreg_read(PCCR) & 0xfffc0fff);
	48	sysreg_write(PCCR, val);
	49	return count;
	50	}
8a25a2fd KS	51	static ssize_t show_pc0count(struct device *dev,
8a25a2fd KS	52	struct device_attribute attr, char buf)
5f97f7f9 HS	53	{
	54	unsigned long pcnt0;
	55
	56	pcnt0 = sysreg_read(PCNT0);
	57	return sprintf(buf, "%lu\n", pcnt0);
	58	}
8a25a2fd KS	59	static ssize_t store_pc0count(struct device *dev,
8a25a2fd KS	60	struct device_attribute *attr,
4a0b2b4d	61	const char *buf, size_t count)
5f97f7f9 HS	62	{
	63	unsigned long val;
	64	char *endp;
	65
	66	val = simple_strtoul(buf, &endp, 0);
	67	if (endp == buf)
	68	return -EINVAL;
	69	sysreg_write(PCNT0, val);
	70
	71	return count;
	72	}
	73
8a25a2fd KS	74	static ssize_t show_pc1event(struct device *dev,
8a25a2fd KS	75	struct device_attribute attr, char buf)
5f97f7f9 HS	76	{
	77	unsigned long pccr;
	78
	79	pccr = sysreg_read(PCCR);
	80	return sprintf(buf, "0x%lx\n", (pccr >> 18) & 0x3f);
	81	}
8a25a2fd KS	82	static ssize_t store_pc1event(struct device *dev,
8a25a2fd KS	83	struct device_attribute attr, const char buf,
5f97f7f9 HS	84	size_t count)
	85	{
	86	unsigned long val;
	87	char *endp;
	88
	89	val = simple_strtoul(buf, &endp, 0);
	90	if (endp == buf \|\| val > 0x3f)
	91	return -EINVAL;
	92	val = (val << 18) \| (sysreg_read(PCCR) & 0xff03ffff);
	93	sysreg_write(PCCR, val);
	94	return count;
	95	}
8a25a2fd KS	96	static ssize_t show_pc1count(struct device *dev,
8a25a2fd KS	97	struct device_attribute attr, char buf)
5f97f7f9 HS	98	{
	99	unsigned long pcnt1;
	100
	101	pcnt1 = sysreg_read(PCNT1);
	102	return sprintf(buf, "%lu\n", pcnt1);
	103	}
8a25a2fd KS	104	static ssize_t store_pc1count(struct device *dev,
8a25a2fd KS	105	struct device_attribute attr, const char buf,
5f97f7f9 HS	106	size_t count)
	107	{
	108	unsigned long val;
	109	char *endp;
	110
	111	val = simple_strtoul(buf, &endp, 0);
	112	if (endp == buf)
	113	return -EINVAL;
	114	sysreg_write(PCNT1, val);
	115
	116	return count;
	117	}
	118
8a25a2fd KS	119	static ssize_t show_pccycles(struct device *dev,
8a25a2fd KS	120	struct device_attribute attr, char buf)
5f97f7f9 HS	121	{
	122	unsigned long pccnt;
	123
	124	pccnt = sysreg_read(PCCNT);
	125	return sprintf(buf, "%lu\n", pccnt);
	126	}
8a25a2fd KS	127	static ssize_t store_pccycles(struct device *dev,
8a25a2fd KS	128	struct device_attribute attr, const char buf,
5f97f7f9 HS	129	size_t count)
	130	{
	131	unsigned long val;
	132	char *endp;
	133
	134	val = simple_strtoul(buf, &endp, 0);
	135	if (endp == buf)
	136	return -EINVAL;
	137	sysreg_write(PCCNT, val);
	138
	139	return count;
	140	}
	141
8a25a2fd KS	142	static ssize_t show_pcenable(struct device *dev,
8a25a2fd KS	143	struct device_attribute attr, char buf)
5f97f7f9 HS	144	{
	145	unsigned long pccr;
	146
	147	pccr = sysreg_read(PCCR);
	148	return sprintf(buf, "%c\n", (pccr & 1)?'1':'0');
	149	}
8a25a2fd KS	150	static ssize_t store_pcenable(struct device *dev,
8a25a2fd KS	151	struct device_attribute attr, const char buf,
5f97f7f9 HS	152	size_t count)
	153	{
	154	unsigned long pccr, val;
	155	char *endp;
	156
	157	val = simple_strtoul(buf, &endp, 0);
	158	if (endp == buf)
	159	return -EINVAL;
	160	if (val)
	161	val = 1;
	162
	163	pccr = sysreg_read(PCCR);
	164	pccr = (pccr & ~1UL) \| val;
	165	sysreg_write(PCCR, pccr);
	166
	167	return count;
	168	}
	169
8a25a2fd KS	170	static DEVICE_ATTR(pc0event, 0600, show_pc0event, store_pc0event);
	171	static DEVICE_ATTR(pc0count, 0600, show_pc0count, store_pc0count);
	172	static DEVICE_ATTR(pc1event, 0600, show_pc1event, store_pc1event);
	173	static DEVICE_ATTR(pc1count, 0600, show_pc1count, store_pc1count);
	174	static DEVICE_ATTR(pccycles, 0600, show_pccycles, store_pccycles);
	175	static DEVICE_ATTR(pcenable, 0600, show_pcenable, store_pcenable);
5f97f7f9 HS	176
	177	#endif /* CONFIG_PERFORMANCE_COUNTERS */
	178
	179	static int __init topology_init(void)
	180	{
	181	int cpu;
	182
	183	for_each_possible_cpu(cpu) {
	184	struct cpu *c = &per_cpu(cpu_devices, cpu);
	185
	186	register_cpu(c, cpu);
	187
	188	#ifdef CONFIG_PERFORMANCE_COUNTERS
8a25a2fd KS	189	device_create_file(&c->dev, &dev_attr_pc0event);
	190	device_create_file(&c->dev, &dev_attr_pc0count);
	191	device_create_file(&c->dev, &dev_attr_pc1event);
	192	device_create_file(&c->dev, &dev_attr_pc1count);
	193	device_create_file(&c->dev, &dev_attr_pccycles);
	194	device_create_file(&c->dev, &dev_attr_pcenable);
5f97f7f9 HS	195	#endif
	196	}
	197
	198	return 0;
	199	}
	200
	201	subsys_initcall(topology_init);
	202
281ef58c HS	203	struct chip_id_map {
	204	u16 mid;
	205	u16 pn;
	206	const char *name;
	207	};
	208
	209	static const struct chip_id_map chip_names[] = {
	210	{ .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
	211	};
	212	#define NR_CHIP_NAMES ARRAY_SIZE(chip_names)
	213
5f97f7f9 HS	214	static const char *cpu_names[] = {
5f97f7f9 HS	215	"Morgan",
281ef58c	216	"AP7",
5f97f7f9 HS	217	};
	218	#define NR_CPU_NAMES ARRAY_SIZE(cpu_names)
	219
	220	static const char *arch_names[] = {
	221	"AVR32A",
	222	"AVR32B",
	223	};
	224	#define NR_ARCH_NAMES ARRAY_SIZE(arch_names)
	225
	226	static const char *mmu_types[] = {
	227	"No MMU",
	228	"ITLB and DTLB",
	229	"Shared TLB",
	230	"MPU"
	231	};
	232
281ef58c HS	233	static const char *cpu_feature_flags[] = {
	234	"rmw", "dsp", "simd", "ocd", "perfctr", "java", "fpu",
	235	};
	236
	237	static const char get_chip_name(struct avr32_cpuinfo cpu)
	238	{
	239	unsigned int i;
	240	unsigned int mid = avr32_get_manufacturer_id(cpu);
	241	unsigned int pn = avr32_get_product_number(cpu);
	242
	243	for (i = 0; i < NR_CHIP_NAMES; i++) {
	244	if (chip_names[i].mid == mid && chip_names[i].pn == pn)
	245	return chip_names[i].name;
	246	}
	247
	248	return "(unknown)";
	249	}
	250
5f97f7f9 HS	251	void __init setup_processor(void)
	252	{
	253	unsigned long config0, config1;
3b328c98	254	unsigned long features;
5f97f7f9	255	unsigned cpu_id, cpu_rev, arch_id, arch_rev, mmu_type;
281ef58c	256	unsigned device_id;
5f97f7f9	257	unsigned tmp;
281ef58c	258	unsigned i;
5f97f7f9	259
3b328c98 HS	260	config0 = sysreg_read(CONFIG0);
	261	config1 = sysreg_read(CONFIG1);
	262	cpu_id = SYSREG_BFEXT(PROCESSORID, config0);
	263	cpu_rev = SYSREG_BFEXT(PROCESSORREVISION, config0);
	264	arch_id = SYSREG_BFEXT(AT, config0);
	265	arch_rev = SYSREG_BFEXT(AR, config0);
	266	mmu_type = SYSREG_BFEXT(MMUT, config0);
5f97f7f9	267
281ef58c HS	268	device_id = ocd_read(DID);
281ef58c HS	269
5f97f7f9 HS	270	boot_cpu_data.arch_type = arch_id;
	271	boot_cpu_data.cpu_type = cpu_id;
	272	boot_cpu_data.arch_revision = arch_rev;
	273	boot_cpu_data.cpu_revision = cpu_rev;
	274	boot_cpu_data.tlb_config = mmu_type;
281ef58c	275	boot_cpu_data.device_id = device_id;
5f97f7f9	276
3b328c98	277	tmp = SYSREG_BFEXT(ILSZ, config1);
5f97f7f9	278	if (tmp) {
3b328c98 HS	279	boot_cpu_data.icache.ways = 1 << SYSREG_BFEXT(IASS, config1);
3b328c98 HS	280	boot_cpu_data.icache.sets = 1 << SYSREG_BFEXT(ISET, config1);
5f97f7f9 HS	281	boot_cpu_data.icache.linesz = 1 << (tmp + 1);
5f97f7f9 HS	282	}
3b328c98	283	tmp = SYSREG_BFEXT(DLSZ, config1);
5f97f7f9	284	if (tmp) {
3b328c98 HS	285	boot_cpu_data.dcache.ways = 1 << SYSREG_BFEXT(DASS, config1);
3b328c98 HS	286	boot_cpu_data.dcache.sets = 1 << SYSREG_BFEXT(DSET, config1);
5f97f7f9 HS	287	boot_cpu_data.dcache.linesz = 1 << (tmp + 1);
	288	}
	289
	290	if ((cpu_id >= NR_CPU_NAMES) \|\| (arch_id >= NR_ARCH_NAMES)) {
	291	printk ("Unknown CPU configuration (ID %02x, arch %02x), "
	292	"continuing anyway...\n",
	293	cpu_id, arch_id);
	294	return;
	295	}
	296
281ef58c HS	297	printk ("CPU: %s chip revision %c\n", get_chip_name(&boot_cpu_data),
	298	avr32_get_chip_revision(&boot_cpu_data) + 'A');
	299	printk ("CPU: %s [%02x] core revision %d (%s arch revision %d)\n",
5f97f7f9 HS	300	cpu_names[cpu_id], cpu_id, cpu_rev,
	301	arch_names[arch_id], arch_rev);
	302	printk ("CPU: MMU configuration: %s\n", mmu_types[mmu_type]);
3b328c98	303
5f97f7f9	304	printk ("CPU: features:");
3b328c98	305	features = 0;
281ef58c	306	if (config0 & SYSREG_BIT(CONFIG0_R))
3b328c98	307	features \|= AVR32_FEATURE_RMW;
281ef58c	308	if (config0 & SYSREG_BIT(CONFIG0_D))
3b328c98	309	features \|= AVR32_FEATURE_DSP;
281ef58c	310	if (config0 & SYSREG_BIT(CONFIG0_S))
3b328c98	311	features \|= AVR32_FEATURE_SIMD;
281ef58c	312	if (config0 & SYSREG_BIT(CONFIG0_O))
3b328c98	313	features \|= AVR32_FEATURE_OCD;
281ef58c	314	if (config0 & SYSREG_BIT(CONFIG0_P))
3b328c98	315	features \|= AVR32_FEATURE_PCTR;
281ef58c	316	if (config0 & SYSREG_BIT(CONFIG0_J))
3b328c98	317	features \|= AVR32_FEATURE_JAVA;
281ef58c	318	if (config0 & SYSREG_BIT(CONFIG0_F))
3b328c98	319	features \|= AVR32_FEATURE_FPU;
281ef58c HS	320
	321	for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
	322	if (features & (1 << i))
	323	printk(" %s", cpu_feature_flags[i]);
	324
5f97f7f9	325	printk("\n");
3b328c98	326	boot_cpu_data.features = features;
5f97f7f9 HS	327	}
	328
	329	#ifdef CONFIG_PROC_FS
	330	static int c_show(struct seq_file m, void v)
	331	{
	332	unsigned int icache_size, dcache_size;
	333	unsigned int cpu = smp_processor_id();
281ef58c HS	334	unsigned int freq;
281ef58c HS	335	unsigned int i;
5f97f7f9 HS	336
	337	icache_size = boot_cpu_data.icache.ways *
	338	boot_cpu_data.icache.sets *
	339	boot_cpu_data.icache.linesz;
	340	dcache_size = boot_cpu_data.dcache.ways *
	341	boot_cpu_data.dcache.sets *
	342	boot_cpu_data.dcache.linesz;
	343
	344	seq_printf(m, "processor\t: %d\n", cpu);
	345
281ef58c HS	346	seq_printf(m, "chip type\t: %s revision %c\n",
	347	get_chip_name(&boot_cpu_data),
	348	avr32_get_chip_revision(&boot_cpu_data) + 'A');
5f97f7f9	349	if (boot_cpu_data.arch_type < NR_ARCH_NAMES)
281ef58c	350	seq_printf(m, "cpu arch\t: %s revision %d\n",
5f97f7f9 HS	351	arch_names[boot_cpu_data.arch_type],
	352	boot_cpu_data.arch_revision);
	353	if (boot_cpu_data.cpu_type < NR_CPU_NAMES)
281ef58c	354	seq_printf(m, "cpu core\t: %s revision %d\n",
5f97f7f9 HS	355	cpu_names[boot_cpu_data.cpu_type],
	356	boot_cpu_data.cpu_revision);
	357
281ef58c HS	358	freq = (clk_get_rate(boot_cpu_data.clk) + 500) / 1000;
	359	seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, freq % 1000);
	360
5f97f7f9 HS	361	seq_printf(m, "i-cache\t\t: %dK (%u ways x %u sets x %u)\n",
	362	icache_size >> 10,
	363	boot_cpu_data.icache.ways,
	364	boot_cpu_data.icache.sets,
	365	boot_cpu_data.icache.linesz);
	366	seq_printf(m, "d-cache\t\t: %dK (%u ways x %u sets x %u)\n",
	367	dcache_size >> 10,
	368	boot_cpu_data.dcache.ways,
	369	boot_cpu_data.dcache.sets,
	370	boot_cpu_data.dcache.linesz);
281ef58c HS	371
	372	seq_printf(m, "features\t:");
	373	for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
	374	if (boot_cpu_data.features & (1 << i))
	375	seq_printf(m, " %s", cpu_feature_flags[i]);
	376
	377	seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
5f97f7f9 HS	378	boot_cpu_data.loops_per_jiffy / (500000/HZ),
	379	(boot_cpu_data.loops_per_jiffy / (5000/HZ)) % 100);
	380
	381	return 0;
	382	}
	383
	384	static void c_start(struct seq_file m, loff_t *pos)
	385	{
	386	return pos < 1 ? (void )1 : NULL;
	387	}
	388
	389	static void c_next(struct seq_file m, void v, loff_t pos)
	390	{
	391	++*pos;
	392	return NULL;
	393	}
	394
	395	static void c_stop(struct seq_file m, void v)
	396	{
	397
	398	}
	399
f6135d12	400	const struct seq_operations cpuinfo_op = {
5f97f7f9 HS	401	.start = c_start,
	402	.next = c_next,
	403	.stop = c_stop,
	404	.show = c_show
	405	};
	406	#endif /* CONFIG_PROC_FS */