Commit | Line | Data |
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5f97f7f9 HS |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | #include <linux/clk.h> | |
d0a2b7af | 9 | #include <linux/fb.h> |
5f97f7f9 HS |
10 | #include <linux/init.h> |
11 | #include <linux/platform_device.h> | |
6b84bbfc | 12 | #include <linux/dma-mapping.h> |
41d8ca45 | 13 | #include <linux/spi/spi.h> |
5f97f7f9 HS |
14 | |
15 | #include <asm/io.h> | |
16 | ||
c3e2a79c | 17 | #include <asm/arch/at32ap7000.h> |
5f97f7f9 HS |
18 | #include <asm/arch/board.h> |
19 | #include <asm/arch/portmux.h> | |
5f97f7f9 | 20 | |
d0a2b7af HS |
21 | #include <video/atmel_lcdc.h> |
22 | ||
5f97f7f9 | 23 | #include "clock.h" |
9c8f8e75 | 24 | #include "hmatrix.h" |
5f97f7f9 | 25 | #include "pio.h" |
7a5b8059 HS |
26 | #include "pm.h" |
27 | ||
5f97f7f9 HS |
28 | |
29 | #define PBMEM(base) \ | |
30 | { \ | |
31 | .start = base, \ | |
32 | .end = base + 0x3ff, \ | |
33 | .flags = IORESOURCE_MEM, \ | |
34 | } | |
35 | #define IRQ(num) \ | |
36 | { \ | |
37 | .start = num, \ | |
38 | .end = num, \ | |
39 | .flags = IORESOURCE_IRQ, \ | |
40 | } | |
41 | #define NAMED_IRQ(num, _name) \ | |
42 | { \ | |
43 | .start = num, \ | |
44 | .end = num, \ | |
45 | .name = _name, \ | |
46 | .flags = IORESOURCE_IRQ, \ | |
47 | } | |
48 | ||
6b84bbfc DB |
49 | /* REVISIT these assume *every* device supports DMA, but several |
50 | * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more. | |
51 | */ | |
5f97f7f9 | 52 | #define DEFINE_DEV(_name, _id) \ |
6b84bbfc | 53 | static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \ |
5f97f7f9 HS |
54 | static struct platform_device _name##_id##_device = { \ |
55 | .name = #_name, \ | |
56 | .id = _id, \ | |
6b84bbfc DB |
57 | .dev = { \ |
58 | .dma_mask = &_name##_id##_dma_mask, \ | |
59 | .coherent_dma_mask = DMA_32BIT_MASK, \ | |
60 | }, \ | |
5f97f7f9 HS |
61 | .resource = _name##_id##_resource, \ |
62 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
63 | } | |
64 | #define DEFINE_DEV_DATA(_name, _id) \ | |
6b84bbfc | 65 | static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \ |
5f97f7f9 HS |
66 | static struct platform_device _name##_id##_device = { \ |
67 | .name = #_name, \ | |
68 | .id = _id, \ | |
69 | .dev = { \ | |
6b84bbfc | 70 | .dma_mask = &_name##_id##_dma_mask, \ |
5f97f7f9 | 71 | .platform_data = &_name##_id##_data, \ |
6b84bbfc | 72 | .coherent_dma_mask = DMA_32BIT_MASK, \ |
5f97f7f9 HS |
73 | }, \ |
74 | .resource = _name##_id##_resource, \ | |
75 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
76 | } | |
77 | ||
c3e2a79c HS |
78 | #define select_peripheral(pin, periph, flags) \ |
79 | at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags) | |
80 | ||
5f97f7f9 HS |
81 | #define DEV_CLK(_name, devname, bus, _index) \ |
82 | static struct clk devname##_##_name = { \ | |
83 | .name = #_name, \ | |
84 | .dev = &devname##_device.dev, \ | |
85 | .parent = &bus##_clk, \ | |
86 | .mode = bus##_clk_mode, \ | |
87 | .get_rate = bus##_clk_get_rate, \ | |
88 | .index = _index, \ | |
89 | } | |
90 | ||
7a5b8059 HS |
91 | static DEFINE_SPINLOCK(pm_lock); |
92 | ||
5f97f7f9 HS |
93 | unsigned long at32ap7000_osc_rates[3] = { |
94 | [0] = 32768, | |
95 | /* FIXME: these are ATSTK1002-specific */ | |
96 | [1] = 20000000, | |
97 | [2] = 12000000, | |
98 | }; | |
99 | ||
100 | static unsigned long osc_get_rate(struct clk *clk) | |
101 | { | |
102 | return at32ap7000_osc_rates[clk->index]; | |
103 | } | |
104 | ||
105 | static unsigned long pll_get_rate(struct clk *clk, unsigned long control) | |
106 | { | |
107 | unsigned long div, mul, rate; | |
108 | ||
7a5b8059 | 109 | if (!(control & PM_BIT(PLLEN))) |
5f97f7f9 HS |
110 | return 0; |
111 | ||
7a5b8059 HS |
112 | div = PM_BFEXT(PLLDIV, control) + 1; |
113 | mul = PM_BFEXT(PLLMUL, control) + 1; | |
5f97f7f9 HS |
114 | |
115 | rate = clk->parent->get_rate(clk->parent); | |
116 | rate = (rate + div / 2) / div; | |
117 | rate *= mul; | |
118 | ||
119 | return rate; | |
120 | } | |
121 | ||
122 | static unsigned long pll0_get_rate(struct clk *clk) | |
123 | { | |
124 | u32 control; | |
125 | ||
7a5b8059 | 126 | control = pm_readl(PLL0); |
5f97f7f9 HS |
127 | |
128 | return pll_get_rate(clk, control); | |
129 | } | |
130 | ||
131 | static unsigned long pll1_get_rate(struct clk *clk) | |
132 | { | |
133 | u32 control; | |
134 | ||
7a5b8059 | 135 | control = pm_readl(PLL1); |
5f97f7f9 HS |
136 | |
137 | return pll_get_rate(clk, control); | |
138 | } | |
139 | ||
140 | /* | |
141 | * The AT32AP7000 has five primary clock sources: One 32kHz | |
142 | * oscillator, two crystal oscillators and two PLLs. | |
143 | */ | |
144 | static struct clk osc32k = { | |
145 | .name = "osc32k", | |
146 | .get_rate = osc_get_rate, | |
147 | .users = 1, | |
148 | .index = 0, | |
149 | }; | |
150 | static struct clk osc0 = { | |
151 | .name = "osc0", | |
152 | .get_rate = osc_get_rate, | |
153 | .users = 1, | |
154 | .index = 1, | |
155 | }; | |
156 | static struct clk osc1 = { | |
157 | .name = "osc1", | |
158 | .get_rate = osc_get_rate, | |
159 | .index = 2, | |
160 | }; | |
161 | static struct clk pll0 = { | |
162 | .name = "pll0", | |
163 | .get_rate = pll0_get_rate, | |
164 | .parent = &osc0, | |
165 | }; | |
166 | static struct clk pll1 = { | |
167 | .name = "pll1", | |
168 | .get_rate = pll1_get_rate, | |
169 | .parent = &osc0, | |
170 | }; | |
171 | ||
172 | /* | |
173 | * The main clock can be either osc0 or pll0. The boot loader may | |
174 | * have chosen one for us, so we don't really know which one until we | |
175 | * have a look at the SM. | |
176 | */ | |
177 | static struct clk *main_clock; | |
178 | ||
179 | /* | |
180 | * Synchronous clocks are generated from the main clock. The clocks | |
181 | * must satisfy the constraint | |
182 | * fCPU >= fHSB >= fPB | |
183 | * i.e. each clock must not be faster than its parent. | |
184 | */ | |
185 | static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift) | |
186 | { | |
187 | return main_clock->get_rate(main_clock) >> shift; | |
188 | }; | |
189 | ||
190 | static void cpu_clk_mode(struct clk *clk, int enabled) | |
191 | { | |
5f97f7f9 HS |
192 | unsigned long flags; |
193 | u32 mask; | |
194 | ||
7a5b8059 HS |
195 | spin_lock_irqsave(&pm_lock, flags); |
196 | mask = pm_readl(CPU_MASK); | |
5f97f7f9 HS |
197 | if (enabled) |
198 | mask |= 1 << clk->index; | |
199 | else | |
200 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
201 | pm_writel(CPU_MASK, mask); |
202 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
203 | } |
204 | ||
205 | static unsigned long cpu_clk_get_rate(struct clk *clk) | |
206 | { | |
207 | unsigned long cksel, shift = 0; | |
208 | ||
7a5b8059 HS |
209 | cksel = pm_readl(CKSEL); |
210 | if (cksel & PM_BIT(CPUDIV)) | |
211 | shift = PM_BFEXT(CPUSEL, cksel) + 1; | |
5f97f7f9 HS |
212 | |
213 | return bus_clk_get_rate(clk, shift); | |
214 | } | |
215 | ||
9e58e185 HCE |
216 | static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply) |
217 | { | |
218 | u32 control; | |
219 | unsigned long parent_rate, child_div, actual_rate, div; | |
220 | ||
221 | parent_rate = clk->parent->get_rate(clk->parent); | |
222 | control = pm_readl(CKSEL); | |
223 | ||
224 | if (control & PM_BIT(HSBDIV)) | |
225 | child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1); | |
226 | else | |
227 | child_div = 1; | |
228 | ||
229 | if (rate > 3 * (parent_rate / 4) || child_div == 1) { | |
230 | actual_rate = parent_rate; | |
231 | control &= ~PM_BIT(CPUDIV); | |
232 | } else { | |
233 | unsigned int cpusel; | |
234 | div = (parent_rate + rate / 2) / rate; | |
235 | if (div > child_div) | |
236 | div = child_div; | |
237 | cpusel = (div > 1) ? (fls(div) - 2) : 0; | |
238 | control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control); | |
239 | actual_rate = parent_rate / (1 << (cpusel + 1)); | |
240 | } | |
241 | ||
242 | pr_debug("clk %s: new rate %lu (actual rate %lu)\n", | |
243 | clk->name, rate, actual_rate); | |
244 | ||
245 | if (apply) | |
246 | pm_writel(CKSEL, control); | |
247 | ||
248 | return actual_rate; | |
249 | } | |
250 | ||
5f97f7f9 HS |
251 | static void hsb_clk_mode(struct clk *clk, int enabled) |
252 | { | |
5f97f7f9 HS |
253 | unsigned long flags; |
254 | u32 mask; | |
255 | ||
7a5b8059 HS |
256 | spin_lock_irqsave(&pm_lock, flags); |
257 | mask = pm_readl(HSB_MASK); | |
5f97f7f9 HS |
258 | if (enabled) |
259 | mask |= 1 << clk->index; | |
260 | else | |
261 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
262 | pm_writel(HSB_MASK, mask); |
263 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
264 | } |
265 | ||
266 | static unsigned long hsb_clk_get_rate(struct clk *clk) | |
267 | { | |
268 | unsigned long cksel, shift = 0; | |
269 | ||
7a5b8059 HS |
270 | cksel = pm_readl(CKSEL); |
271 | if (cksel & PM_BIT(HSBDIV)) | |
272 | shift = PM_BFEXT(HSBSEL, cksel) + 1; | |
5f97f7f9 HS |
273 | |
274 | return bus_clk_get_rate(clk, shift); | |
275 | } | |
276 | ||
277 | static void pba_clk_mode(struct clk *clk, int enabled) | |
278 | { | |
5f97f7f9 HS |
279 | unsigned long flags; |
280 | u32 mask; | |
281 | ||
7a5b8059 HS |
282 | spin_lock_irqsave(&pm_lock, flags); |
283 | mask = pm_readl(PBA_MASK); | |
5f97f7f9 HS |
284 | if (enabled) |
285 | mask |= 1 << clk->index; | |
286 | else | |
287 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
288 | pm_writel(PBA_MASK, mask); |
289 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
290 | } |
291 | ||
292 | static unsigned long pba_clk_get_rate(struct clk *clk) | |
293 | { | |
294 | unsigned long cksel, shift = 0; | |
295 | ||
7a5b8059 HS |
296 | cksel = pm_readl(CKSEL); |
297 | if (cksel & PM_BIT(PBADIV)) | |
298 | shift = PM_BFEXT(PBASEL, cksel) + 1; | |
5f97f7f9 HS |
299 | |
300 | return bus_clk_get_rate(clk, shift); | |
301 | } | |
302 | ||
303 | static void pbb_clk_mode(struct clk *clk, int enabled) | |
304 | { | |
5f97f7f9 HS |
305 | unsigned long flags; |
306 | u32 mask; | |
307 | ||
7a5b8059 HS |
308 | spin_lock_irqsave(&pm_lock, flags); |
309 | mask = pm_readl(PBB_MASK); | |
5f97f7f9 HS |
310 | if (enabled) |
311 | mask |= 1 << clk->index; | |
312 | else | |
313 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
314 | pm_writel(PBB_MASK, mask); |
315 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
316 | } |
317 | ||
318 | static unsigned long pbb_clk_get_rate(struct clk *clk) | |
319 | { | |
320 | unsigned long cksel, shift = 0; | |
321 | ||
7a5b8059 HS |
322 | cksel = pm_readl(CKSEL); |
323 | if (cksel & PM_BIT(PBBDIV)) | |
324 | shift = PM_BFEXT(PBBSEL, cksel) + 1; | |
5f97f7f9 HS |
325 | |
326 | return bus_clk_get_rate(clk, shift); | |
327 | } | |
328 | ||
329 | static struct clk cpu_clk = { | |
330 | .name = "cpu", | |
331 | .get_rate = cpu_clk_get_rate, | |
9e58e185 | 332 | .set_rate = cpu_clk_set_rate, |
5f97f7f9 HS |
333 | .users = 1, |
334 | }; | |
335 | static struct clk hsb_clk = { | |
336 | .name = "hsb", | |
337 | .parent = &cpu_clk, | |
338 | .get_rate = hsb_clk_get_rate, | |
339 | }; | |
340 | static struct clk pba_clk = { | |
341 | .name = "pba", | |
342 | .parent = &hsb_clk, | |
343 | .mode = hsb_clk_mode, | |
344 | .get_rate = pba_clk_get_rate, | |
345 | .index = 1, | |
346 | }; | |
347 | static struct clk pbb_clk = { | |
348 | .name = "pbb", | |
349 | .parent = &hsb_clk, | |
350 | .mode = hsb_clk_mode, | |
351 | .get_rate = pbb_clk_get_rate, | |
352 | .users = 1, | |
353 | .index = 2, | |
354 | }; | |
355 | ||
356 | /* -------------------------------------------------------------------- | |
357 | * Generic Clock operations | |
358 | * -------------------------------------------------------------------- */ | |
359 | ||
360 | static void genclk_mode(struct clk *clk, int enabled) | |
361 | { | |
362 | u32 control; | |
363 | ||
7a5b8059 | 364 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 | 365 | if (enabled) |
7a5b8059 | 366 | control |= PM_BIT(CEN); |
5f97f7f9 | 367 | else |
7a5b8059 HS |
368 | control &= ~PM_BIT(CEN); |
369 | pm_writel(GCCTRL(clk->index), control); | |
5f97f7f9 HS |
370 | } |
371 | ||
372 | static unsigned long genclk_get_rate(struct clk *clk) | |
373 | { | |
374 | u32 control; | |
375 | unsigned long div = 1; | |
376 | ||
7a5b8059 HS |
377 | control = pm_readl(GCCTRL(clk->index)); |
378 | if (control & PM_BIT(DIVEN)) | |
379 | div = 2 * (PM_BFEXT(DIV, control) + 1); | |
5f97f7f9 HS |
380 | |
381 | return clk->parent->get_rate(clk->parent) / div; | |
382 | } | |
383 | ||
384 | static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply) | |
385 | { | |
386 | u32 control; | |
387 | unsigned long parent_rate, actual_rate, div; | |
388 | ||
5f97f7f9 | 389 | parent_rate = clk->parent->get_rate(clk->parent); |
7a5b8059 | 390 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
391 | |
392 | if (rate > 3 * parent_rate / 4) { | |
393 | actual_rate = parent_rate; | |
7a5b8059 | 394 | control &= ~PM_BIT(DIVEN); |
5f97f7f9 HS |
395 | } else { |
396 | div = (parent_rate + rate) / (2 * rate) - 1; | |
7a5b8059 | 397 | control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN); |
5f97f7f9 HS |
398 | actual_rate = parent_rate / (2 * (div + 1)); |
399 | } | |
400 | ||
7a5b8059 HS |
401 | dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n", |
402 | clk->name, rate, actual_rate); | |
5f97f7f9 HS |
403 | |
404 | if (apply) | |
7a5b8059 | 405 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
406 | |
407 | return actual_rate; | |
408 | } | |
409 | ||
410 | int genclk_set_parent(struct clk *clk, struct clk *parent) | |
411 | { | |
412 | u32 control; | |
413 | ||
7a5b8059 HS |
414 | dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n", |
415 | clk->name, parent->name, clk->parent->name); | |
5f97f7f9 | 416 | |
7a5b8059 | 417 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
418 | |
419 | if (parent == &osc1 || parent == &pll1) | |
7a5b8059 | 420 | control |= PM_BIT(OSCSEL); |
5f97f7f9 | 421 | else if (parent == &osc0 || parent == &pll0) |
7a5b8059 | 422 | control &= ~PM_BIT(OSCSEL); |
5f97f7f9 HS |
423 | else |
424 | return -EINVAL; | |
425 | ||
426 | if (parent == &pll0 || parent == &pll1) | |
7a5b8059 | 427 | control |= PM_BIT(PLLSEL); |
5f97f7f9 | 428 | else |
7a5b8059 | 429 | control &= ~PM_BIT(PLLSEL); |
5f97f7f9 | 430 | |
7a5b8059 | 431 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
432 | clk->parent = parent; |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
7a5fe238 HS |
437 | static void __init genclk_init_parent(struct clk *clk) |
438 | { | |
439 | u32 control; | |
440 | struct clk *parent; | |
441 | ||
442 | BUG_ON(clk->index > 7); | |
443 | ||
7a5b8059 HS |
444 | control = pm_readl(GCCTRL(clk->index)); |
445 | if (control & PM_BIT(OSCSEL)) | |
446 | parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1; | |
7a5fe238 | 447 | else |
7a5b8059 | 448 | parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0; |
7a5fe238 HS |
449 | |
450 | clk->parent = parent; | |
451 | } | |
452 | ||
5f97f7f9 HS |
453 | /* -------------------------------------------------------------------- |
454 | * System peripherals | |
455 | * -------------------------------------------------------------------- */ | |
7a5b8059 HS |
456 | static struct resource at32_pm0_resource[] = { |
457 | { | |
458 | .start = 0xfff00000, | |
459 | .end = 0xfff0007f, | |
460 | .flags = IORESOURCE_MEM, | |
461 | }, | |
462 | IRQ(20), | |
5f97f7f9 | 463 | }; |
7a5b8059 HS |
464 | |
465 | static struct resource at32ap700x_rtc0_resource[] = { | |
466 | { | |
467 | .start = 0xfff00080, | |
468 | .end = 0xfff000af, | |
469 | .flags = IORESOURCE_MEM, | |
470 | }, | |
471 | IRQ(21), | |
5f97f7f9 | 472 | }; |
7a5b8059 HS |
473 | |
474 | static struct resource at32_wdt0_resource[] = { | |
475 | { | |
476 | .start = 0xfff000b0, | |
477 | .end = 0xfff000bf, | |
478 | .flags = IORESOURCE_MEM, | |
479 | }, | |
480 | }; | |
481 | ||
482 | static struct resource at32_eic0_resource[] = { | |
483 | { | |
484 | .start = 0xfff00100, | |
485 | .end = 0xfff0013f, | |
486 | .flags = IORESOURCE_MEM, | |
487 | }, | |
488 | IRQ(19), | |
489 | }; | |
490 | ||
491 | DEFINE_DEV(at32_pm, 0); | |
492 | DEFINE_DEV(at32ap700x_rtc, 0); | |
493 | DEFINE_DEV(at32_wdt, 0); | |
494 | DEFINE_DEV(at32_eic, 0); | |
495 | ||
496 | /* | |
497 | * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this | |
498 | * is always running. | |
499 | */ | |
500 | static struct clk at32_pm_pclk = { | |
188ff65d | 501 | .name = "pclk", |
7a5b8059 | 502 | .dev = &at32_pm0_device.dev, |
188ff65d HS |
503 | .parent = &pbb_clk, |
504 | .mode = pbb_clk_mode, | |
505 | .get_rate = pbb_clk_get_rate, | |
506 | .users = 1, | |
507 | .index = 0, | |
508 | }; | |
5f97f7f9 HS |
509 | |
510 | static struct resource intc0_resource[] = { | |
511 | PBMEM(0xfff00400), | |
512 | }; | |
513 | struct platform_device at32_intc0_device = { | |
514 | .name = "intc", | |
515 | .id = 0, | |
516 | .resource = intc0_resource, | |
517 | .num_resources = ARRAY_SIZE(intc0_resource), | |
518 | }; | |
519 | DEV_CLK(pclk, at32_intc0, pbb, 1); | |
520 | ||
521 | static struct clk ebi_clk = { | |
522 | .name = "ebi", | |
523 | .parent = &hsb_clk, | |
524 | .mode = hsb_clk_mode, | |
525 | .get_rate = hsb_clk_get_rate, | |
526 | .users = 1, | |
527 | }; | |
528 | static struct clk hramc_clk = { | |
529 | .name = "hramc", | |
530 | .parent = &hsb_clk, | |
531 | .mode = hsb_clk_mode, | |
532 | .get_rate = hsb_clk_get_rate, | |
533 | .users = 1, | |
188ff65d | 534 | .index = 3, |
5f97f7f9 HS |
535 | }; |
536 | ||
bc157b75 HS |
537 | static struct resource smc0_resource[] = { |
538 | PBMEM(0xfff03400), | |
539 | }; | |
540 | DEFINE_DEV(smc, 0); | |
541 | DEV_CLK(pclk, smc0, pbb, 13); | |
542 | DEV_CLK(mck, smc0, hsb, 0); | |
543 | ||
5f97f7f9 HS |
544 | static struct platform_device pdc_device = { |
545 | .name = "pdc", | |
546 | .id = 0, | |
547 | }; | |
548 | DEV_CLK(hclk, pdc, hsb, 4); | |
549 | DEV_CLK(pclk, pdc, pba, 16); | |
550 | ||
551 | static struct clk pico_clk = { | |
552 | .name = "pico", | |
553 | .parent = &cpu_clk, | |
554 | .mode = cpu_clk_mode, | |
555 | .get_rate = cpu_clk_get_rate, | |
556 | .users = 1, | |
557 | }; | |
558 | ||
9c8f8e75 HS |
559 | /* -------------------------------------------------------------------- |
560 | * HMATRIX | |
561 | * -------------------------------------------------------------------- */ | |
562 | ||
563 | static struct clk hmatrix_clk = { | |
564 | .name = "hmatrix_clk", | |
565 | .parent = &pbb_clk, | |
566 | .mode = pbb_clk_mode, | |
567 | .get_rate = pbb_clk_get_rate, | |
568 | .index = 2, | |
569 | .users = 1, | |
570 | }; | |
571 | #define HMATRIX_BASE ((void __iomem *)0xfff00800) | |
572 | ||
573 | #define hmatrix_readl(reg) \ | |
574 | __raw_readl((HMATRIX_BASE) + HMATRIX_##reg) | |
575 | #define hmatrix_writel(reg,value) \ | |
576 | __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg) | |
577 | ||
578 | /* | |
579 | * Set bits in the HMATRIX Special Function Register (SFR) used by the | |
580 | * External Bus Interface (EBI). This can be used to enable special | |
581 | * features like CompactFlash support, NAND Flash support, etc. on | |
582 | * certain chipselects. | |
583 | */ | |
584 | static inline void set_ebi_sfr_bits(u32 mask) | |
585 | { | |
586 | u32 sfr; | |
587 | ||
588 | clk_enable(&hmatrix_clk); | |
589 | sfr = hmatrix_readl(SFR4); | |
590 | sfr |= mask; | |
591 | hmatrix_writel(SFR4, sfr); | |
592 | clk_disable(&hmatrix_clk); | |
593 | } | |
594 | ||
7760989e HCE |
595 | /* -------------------------------------------------------------------- |
596 | * System Timer/Counter (TC) | |
597 | * -------------------------------------------------------------------- */ | |
598 | static struct resource at32_systc0_resource[] = { | |
599 | PBMEM(0xfff00c00), | |
600 | IRQ(22), | |
601 | }; | |
602 | struct platform_device at32_systc0_device = { | |
603 | .name = "systc", | |
604 | .id = 0, | |
605 | .resource = at32_systc0_resource, | |
606 | .num_resources = ARRAY_SIZE(at32_systc0_resource), | |
607 | }; | |
608 | DEV_CLK(pclk, at32_systc0, pbb, 3); | |
609 | ||
5f97f7f9 HS |
610 | /* -------------------------------------------------------------------- |
611 | * PIO | |
612 | * -------------------------------------------------------------------- */ | |
613 | ||
614 | static struct resource pio0_resource[] = { | |
615 | PBMEM(0xffe02800), | |
616 | IRQ(13), | |
617 | }; | |
618 | DEFINE_DEV(pio, 0); | |
619 | DEV_CLK(mck, pio0, pba, 10); | |
620 | ||
621 | static struct resource pio1_resource[] = { | |
622 | PBMEM(0xffe02c00), | |
623 | IRQ(14), | |
624 | }; | |
625 | DEFINE_DEV(pio, 1); | |
626 | DEV_CLK(mck, pio1, pba, 11); | |
627 | ||
628 | static struct resource pio2_resource[] = { | |
629 | PBMEM(0xffe03000), | |
630 | IRQ(15), | |
631 | }; | |
632 | DEFINE_DEV(pio, 2); | |
633 | DEV_CLK(mck, pio2, pba, 12); | |
634 | ||
635 | static struct resource pio3_resource[] = { | |
636 | PBMEM(0xffe03400), | |
637 | IRQ(16), | |
638 | }; | |
639 | DEFINE_DEV(pio, 3); | |
640 | DEV_CLK(mck, pio3, pba, 13); | |
641 | ||
7f9f4678 HS |
642 | static struct resource pio4_resource[] = { |
643 | PBMEM(0xffe03800), | |
644 | IRQ(17), | |
645 | }; | |
646 | DEFINE_DEV(pio, 4); | |
647 | DEV_CLK(mck, pio4, pba, 14); | |
648 | ||
5f97f7f9 HS |
649 | void __init at32_add_system_devices(void) |
650 | { | |
7a5b8059 | 651 | platform_device_register(&at32_pm0_device); |
5f97f7f9 | 652 | platform_device_register(&at32_intc0_device); |
7a5b8059 HS |
653 | platform_device_register(&at32ap700x_rtc0_device); |
654 | platform_device_register(&at32_wdt0_device); | |
655 | platform_device_register(&at32_eic0_device); | |
bc157b75 | 656 | platform_device_register(&smc0_device); |
5f97f7f9 HS |
657 | platform_device_register(&pdc_device); |
658 | ||
7760989e HCE |
659 | platform_device_register(&at32_systc0_device); |
660 | ||
5f97f7f9 HS |
661 | platform_device_register(&pio0_device); |
662 | platform_device_register(&pio1_device); | |
663 | platform_device_register(&pio2_device); | |
664 | platform_device_register(&pio3_device); | |
7f9f4678 | 665 | platform_device_register(&pio4_device); |
5f97f7f9 HS |
666 | } |
667 | ||
668 | /* -------------------------------------------------------------------- | |
669 | * USART | |
670 | * -------------------------------------------------------------------- */ | |
671 | ||
75d35213 HS |
672 | static struct atmel_uart_data atmel_usart0_data = { |
673 | .use_dma_tx = 1, | |
674 | .use_dma_rx = 1, | |
675 | }; | |
1e8ea802 | 676 | static struct resource atmel_usart0_resource[] = { |
5f97f7f9 | 677 | PBMEM(0xffe00c00), |
a3d912c8 | 678 | IRQ(6), |
5f97f7f9 | 679 | }; |
75d35213 | 680 | DEFINE_DEV_DATA(atmel_usart, 0); |
1e8ea802 | 681 | DEV_CLK(usart, atmel_usart0, pba, 4); |
5f97f7f9 | 682 | |
75d35213 HS |
683 | static struct atmel_uart_data atmel_usart1_data = { |
684 | .use_dma_tx = 1, | |
685 | .use_dma_rx = 1, | |
686 | }; | |
1e8ea802 | 687 | static struct resource atmel_usart1_resource[] = { |
5f97f7f9 HS |
688 | PBMEM(0xffe01000), |
689 | IRQ(7), | |
690 | }; | |
75d35213 | 691 | DEFINE_DEV_DATA(atmel_usart, 1); |
1e8ea802 | 692 | DEV_CLK(usart, atmel_usart1, pba, 4); |
5f97f7f9 | 693 | |
75d35213 HS |
694 | static struct atmel_uart_data atmel_usart2_data = { |
695 | .use_dma_tx = 1, | |
696 | .use_dma_rx = 1, | |
697 | }; | |
1e8ea802 | 698 | static struct resource atmel_usart2_resource[] = { |
5f97f7f9 HS |
699 | PBMEM(0xffe01400), |
700 | IRQ(8), | |
701 | }; | |
75d35213 | 702 | DEFINE_DEV_DATA(atmel_usart, 2); |
1e8ea802 | 703 | DEV_CLK(usart, atmel_usart2, pba, 5); |
5f97f7f9 | 704 | |
75d35213 HS |
705 | static struct atmel_uart_data atmel_usart3_data = { |
706 | .use_dma_tx = 1, | |
707 | .use_dma_rx = 1, | |
708 | }; | |
1e8ea802 | 709 | static struct resource atmel_usart3_resource[] = { |
5f97f7f9 HS |
710 | PBMEM(0xffe01800), |
711 | IRQ(9), | |
712 | }; | |
75d35213 | 713 | DEFINE_DEV_DATA(atmel_usart, 3); |
1e8ea802 | 714 | DEV_CLK(usart, atmel_usart3, pba, 6); |
5f97f7f9 HS |
715 | |
716 | static inline void configure_usart0_pins(void) | |
717 | { | |
c3e2a79c HS |
718 | select_peripheral(PA(8), PERIPH_B, 0); /* RXD */ |
719 | select_peripheral(PA(9), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
720 | } |
721 | ||
722 | static inline void configure_usart1_pins(void) | |
723 | { | |
c3e2a79c HS |
724 | select_peripheral(PA(17), PERIPH_A, 0); /* RXD */ |
725 | select_peripheral(PA(18), PERIPH_A, 0); /* TXD */ | |
5f97f7f9 HS |
726 | } |
727 | ||
728 | static inline void configure_usart2_pins(void) | |
729 | { | |
c3e2a79c HS |
730 | select_peripheral(PB(26), PERIPH_B, 0); /* RXD */ |
731 | select_peripheral(PB(27), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
732 | } |
733 | ||
734 | static inline void configure_usart3_pins(void) | |
735 | { | |
c3e2a79c HS |
736 | select_peripheral(PB(18), PERIPH_B, 0); /* RXD */ |
737 | select_peripheral(PB(17), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
738 | } |
739 | ||
a3d912c8 | 740 | static struct platform_device *__initdata at32_usarts[4]; |
c194588d HS |
741 | |
742 | void __init at32_map_usart(unsigned int hw_id, unsigned int line) | |
5f97f7f9 HS |
743 | { |
744 | struct platform_device *pdev; | |
745 | ||
c194588d | 746 | switch (hw_id) { |
5f97f7f9 | 747 | case 0: |
1e8ea802 | 748 | pdev = &atmel_usart0_device; |
5f97f7f9 HS |
749 | configure_usart0_pins(); |
750 | break; | |
751 | case 1: | |
1e8ea802 | 752 | pdev = &atmel_usart1_device; |
5f97f7f9 HS |
753 | configure_usart1_pins(); |
754 | break; | |
755 | case 2: | |
1e8ea802 | 756 | pdev = &atmel_usart2_device; |
5f97f7f9 HS |
757 | configure_usart2_pins(); |
758 | break; | |
759 | case 3: | |
1e8ea802 | 760 | pdev = &atmel_usart3_device; |
5f97f7f9 HS |
761 | configure_usart3_pins(); |
762 | break; | |
763 | default: | |
c194588d | 764 | return; |
75d35213 HS |
765 | } |
766 | ||
767 | if (PXSEG(pdev->resource[0].start) == P4SEG) { | |
768 | /* Addresses in the P4 segment are permanently mapped 1:1 */ | |
769 | struct atmel_uart_data *data = pdev->dev.platform_data; | |
770 | data->regs = (void __iomem *)pdev->resource[0].start; | |
5f97f7f9 HS |
771 | } |
772 | ||
c194588d HS |
773 | pdev->id = line; |
774 | at32_usarts[line] = pdev; | |
5f97f7f9 HS |
775 | } |
776 | ||
777 | struct platform_device *__init at32_add_device_usart(unsigned int id) | |
778 | { | |
c194588d HS |
779 | platform_device_register(at32_usarts[id]); |
780 | return at32_usarts[id]; | |
5f97f7f9 HS |
781 | } |
782 | ||
73e2798b | 783 | struct platform_device *atmel_default_console_device; |
5f97f7f9 HS |
784 | |
785 | void __init at32_setup_serial_console(unsigned int usart_id) | |
786 | { | |
c194588d | 787 | atmel_default_console_device = at32_usarts[usart_id]; |
5f97f7f9 HS |
788 | } |
789 | ||
790 | /* -------------------------------------------------------------------- | |
791 | * Ethernet | |
792 | * -------------------------------------------------------------------- */ | |
793 | ||
794 | static struct eth_platform_data macb0_data; | |
795 | static struct resource macb0_resource[] = { | |
796 | PBMEM(0xfff01800), | |
797 | IRQ(25), | |
798 | }; | |
799 | DEFINE_DEV_DATA(macb, 0); | |
800 | DEV_CLK(hclk, macb0, hsb, 8); | |
801 | DEV_CLK(pclk, macb0, pbb, 6); | |
802 | ||
cfcb3a89 HS |
803 | static struct eth_platform_data macb1_data; |
804 | static struct resource macb1_resource[] = { | |
805 | PBMEM(0xfff01c00), | |
806 | IRQ(26), | |
807 | }; | |
808 | DEFINE_DEV_DATA(macb, 1); | |
809 | DEV_CLK(hclk, macb1, hsb, 9); | |
810 | DEV_CLK(pclk, macb1, pbb, 7); | |
811 | ||
5f97f7f9 HS |
812 | struct platform_device *__init |
813 | at32_add_device_eth(unsigned int id, struct eth_platform_data *data) | |
814 | { | |
815 | struct platform_device *pdev; | |
816 | ||
817 | switch (id) { | |
818 | case 0: | |
819 | pdev = &macb0_device; | |
820 | ||
c3e2a79c HS |
821 | select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */ |
822 | select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */ | |
823 | select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */ | |
824 | select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */ | |
825 | select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */ | |
826 | select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */ | |
827 | select_peripheral(PC(13), PERIPH_A, 0); /* RXER */ | |
828 | select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */ | |
829 | select_peripheral(PC(16), PERIPH_A, 0); /* MDC */ | |
830 | select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */ | |
5f97f7f9 HS |
831 | |
832 | if (!data->is_rmii) { | |
c3e2a79c HS |
833 | select_peripheral(PC(0), PERIPH_A, 0); /* COL */ |
834 | select_peripheral(PC(1), PERIPH_A, 0); /* CRS */ | |
835 | select_peripheral(PC(2), PERIPH_A, 0); /* TXER */ | |
836 | select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */ | |
837 | select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */ | |
838 | select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */ | |
839 | select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */ | |
840 | select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */ | |
841 | select_peripheral(PC(18), PERIPH_A, 0); /* SPD */ | |
5f97f7f9 HS |
842 | } |
843 | break; | |
844 | ||
cfcb3a89 HS |
845 | case 1: |
846 | pdev = &macb1_device; | |
847 | ||
848 | select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */ | |
849 | select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */ | |
850 | select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */ | |
851 | select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */ | |
852 | select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */ | |
853 | select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */ | |
854 | select_peripheral(PD(5), PERIPH_B, 0); /* RXER */ | |
855 | select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */ | |
856 | select_peripheral(PD(3), PERIPH_B, 0); /* MDC */ | |
857 | select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */ | |
858 | ||
859 | if (!data->is_rmii) { | |
860 | select_peripheral(PC(19), PERIPH_B, 0); /* COL */ | |
861 | select_peripheral(PC(23), PERIPH_B, 0); /* CRS */ | |
862 | select_peripheral(PC(26), PERIPH_B, 0); /* TXER */ | |
863 | select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */ | |
864 | select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */ | |
865 | select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */ | |
866 | select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */ | |
867 | select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */ | |
868 | select_peripheral(PD(15), PERIPH_B, 0); /* SPD */ | |
869 | } | |
870 | break; | |
871 | ||
5f97f7f9 HS |
872 | default: |
873 | return NULL; | |
874 | } | |
875 | ||
876 | memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data)); | |
877 | platform_device_register(pdev); | |
878 | ||
879 | return pdev; | |
880 | } | |
881 | ||
882 | /* -------------------------------------------------------------------- | |
883 | * SPI | |
884 | * -------------------------------------------------------------------- */ | |
3d60ee1b | 885 | static struct resource atmel_spi0_resource[] = { |
5f97f7f9 HS |
886 | PBMEM(0xffe00000), |
887 | IRQ(3), | |
888 | }; | |
3d60ee1b HS |
889 | DEFINE_DEV(atmel_spi, 0); |
890 | DEV_CLK(spi_clk, atmel_spi0, pba, 0); | |
891 | ||
892 | static struct resource atmel_spi1_resource[] = { | |
893 | PBMEM(0xffe00400), | |
894 | IRQ(4), | |
895 | }; | |
896 | DEFINE_DEV(atmel_spi, 1); | |
897 | DEV_CLK(spi_clk, atmel_spi1, pba, 1); | |
5f97f7f9 | 898 | |
9a596a62 | 899 | static void __init |
41d8ca45 HS |
900 | at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, |
901 | unsigned int n, const u8 *pins) | |
5f97f7f9 | 902 | { |
41d8ca45 HS |
903 | unsigned int pin, mode; |
904 | ||
905 | for (; n; n--, b++) { | |
906 | b->bus_num = bus_num; | |
907 | if (b->chip_select >= 4) | |
908 | continue; | |
909 | pin = (unsigned)b->controller_data; | |
910 | if (!pin) { | |
911 | pin = pins[b->chip_select]; | |
912 | b->controller_data = (void *)pin; | |
913 | } | |
914 | mode = AT32_GPIOF_OUTPUT; | |
915 | if (!(b->mode & SPI_CS_HIGH)) | |
916 | mode |= AT32_GPIOF_HIGH; | |
917 | at32_select_gpio(pin, mode); | |
918 | } | |
919 | } | |
920 | ||
921 | struct platform_device *__init | |
922 | at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n) | |
923 | { | |
924 | /* | |
925 | * Manage the chipselects as GPIOs, normally using the same pins | |
926 | * the SPI controller expects; but boards can use other pins. | |
927 | */ | |
928 | static u8 __initdata spi0_pins[] = | |
929 | { GPIO_PIN_PA(3), GPIO_PIN_PA(4), | |
930 | GPIO_PIN_PA(5), GPIO_PIN_PA(20), }; | |
931 | static u8 __initdata spi1_pins[] = | |
932 | { GPIO_PIN_PB(2), GPIO_PIN_PB(3), | |
933 | GPIO_PIN_PB(4), GPIO_PIN_PA(27), }; | |
5f97f7f9 HS |
934 | struct platform_device *pdev; |
935 | ||
936 | switch (id) { | |
937 | case 0: | |
3d60ee1b | 938 | pdev = &atmel_spi0_device; |
c3e2a79c HS |
939 | select_peripheral(PA(0), PERIPH_A, 0); /* MISO */ |
940 | select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */ | |
941 | select_peripheral(PA(2), PERIPH_A, 0); /* SCK */ | |
41d8ca45 | 942 | at32_spi_setup_slaves(0, b, n, spi0_pins); |
3d60ee1b HS |
943 | break; |
944 | ||
945 | case 1: | |
946 | pdev = &atmel_spi1_device; | |
947 | select_peripheral(PB(0), PERIPH_B, 0); /* MISO */ | |
948 | select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */ | |
949 | select_peripheral(PB(5), PERIPH_B, 0); /* SCK */ | |
41d8ca45 | 950 | at32_spi_setup_slaves(1, b, n, spi1_pins); |
5f97f7f9 HS |
951 | break; |
952 | ||
953 | default: | |
954 | return NULL; | |
955 | } | |
956 | ||
41d8ca45 | 957 | spi_register_board_info(b, n); |
5f97f7f9 HS |
958 | platform_device_register(pdev); |
959 | return pdev; | |
960 | } | |
961 | ||
962 | /* -------------------------------------------------------------------- | |
963 | * LCDC | |
964 | * -------------------------------------------------------------------- */ | |
d0a2b7af HS |
965 | static struct atmel_lcdfb_info atmel_lcdfb0_data; |
966 | static struct resource atmel_lcdfb0_resource[] = { | |
5f97f7f9 HS |
967 | { |
968 | .start = 0xff000000, | |
969 | .end = 0xff000fff, | |
970 | .flags = IORESOURCE_MEM, | |
971 | }, | |
972 | IRQ(1), | |
d0a2b7af HS |
973 | { |
974 | /* Placeholder for pre-allocated fb memory */ | |
975 | .start = 0x00000000, | |
976 | .end = 0x00000000, | |
977 | .flags = 0, | |
978 | }, | |
5f97f7f9 | 979 | }; |
d0a2b7af HS |
980 | DEFINE_DEV_DATA(atmel_lcdfb, 0); |
981 | DEV_CLK(hck1, atmel_lcdfb0, hsb, 7); | |
982 | static struct clk atmel_lcdfb0_pixclk = { | |
983 | .name = "lcdc_clk", | |
984 | .dev = &atmel_lcdfb0_device.dev, | |
5f97f7f9 HS |
985 | .mode = genclk_mode, |
986 | .get_rate = genclk_get_rate, | |
987 | .set_rate = genclk_set_rate, | |
988 | .set_parent = genclk_set_parent, | |
989 | .index = 7, | |
990 | }; | |
991 | ||
992 | struct platform_device *__init | |
d0a2b7af HS |
993 | at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, |
994 | unsigned long fbmem_start, unsigned long fbmem_len) | |
5f97f7f9 HS |
995 | { |
996 | struct platform_device *pdev; | |
d0a2b7af HS |
997 | struct atmel_lcdfb_info *info; |
998 | struct fb_monspecs *monspecs; | |
999 | struct fb_videomode *modedb; | |
1000 | unsigned int modedb_size; | |
1001 | ||
1002 | /* | |
1003 | * Do a deep copy of the fb data, monspecs and modedb. Make | |
1004 | * sure all allocations are done before setting up the | |
1005 | * portmux. | |
1006 | */ | |
1007 | monspecs = kmemdup(data->default_monspecs, | |
1008 | sizeof(struct fb_monspecs), GFP_KERNEL); | |
1009 | if (!monspecs) | |
1010 | return NULL; | |
1011 | ||
1012 | modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len; | |
1013 | modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL); | |
1014 | if (!modedb) | |
1015 | goto err_dup_modedb; | |
1016 | monspecs->modedb = modedb; | |
5f97f7f9 HS |
1017 | |
1018 | switch (id) { | |
1019 | case 0: | |
d0a2b7af | 1020 | pdev = &atmel_lcdfb0_device; |
c3e2a79c HS |
1021 | select_peripheral(PC(19), PERIPH_A, 0); /* CC */ |
1022 | select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */ | |
1023 | select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */ | |
1024 | select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */ | |
1025 | select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */ | |
1026 | select_peripheral(PC(24), PERIPH_A, 0); /* MODE */ | |
1027 | select_peripheral(PC(25), PERIPH_A, 0); /* PWR */ | |
1028 | select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */ | |
1029 | select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */ | |
1030 | select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */ | |
1031 | select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */ | |
1032 | select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */ | |
1033 | select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */ | |
1034 | select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */ | |
1035 | select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */ | |
1036 | select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */ | |
1037 | select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */ | |
1038 | select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */ | |
1039 | select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */ | |
1040 | select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */ | |
1041 | select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */ | |
1042 | select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */ | |
1043 | select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */ | |
1044 | select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */ | |
1045 | select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */ | |
1046 | select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */ | |
1047 | select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */ | |
1048 | select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */ | |
1049 | select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */ | |
1050 | select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */ | |
1051 | select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */ | |
5f97f7f9 | 1052 | |
d0a2b7af HS |
1053 | clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); |
1054 | clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); | |
5f97f7f9 HS |
1055 | break; |
1056 | ||
1057 | default: | |
d0a2b7af | 1058 | goto err_invalid_id; |
5f97f7f9 HS |
1059 | } |
1060 | ||
d0a2b7af HS |
1061 | if (fbmem_len) { |
1062 | pdev->resource[2].start = fbmem_start; | |
1063 | pdev->resource[2].end = fbmem_start + fbmem_len - 1; | |
1064 | pdev->resource[2].flags = IORESOURCE_MEM; | |
1065 | } | |
1066 | ||
1067 | info = pdev->dev.platform_data; | |
1068 | memcpy(info, data, sizeof(struct atmel_lcdfb_info)); | |
1069 | info->default_monspecs = monspecs; | |
5f97f7f9 HS |
1070 | |
1071 | platform_device_register(pdev); | |
1072 | return pdev; | |
d0a2b7af HS |
1073 | |
1074 | err_invalid_id: | |
1075 | kfree(modedb); | |
1076 | err_dup_modedb: | |
1077 | kfree(monspecs); | |
1078 | return NULL; | |
5f97f7f9 HS |
1079 | } |
1080 | ||
9cf6cf58 HCE |
1081 | /* -------------------------------------------------------------------- |
1082 | * SSC | |
1083 | * -------------------------------------------------------------------- */ | |
1084 | static struct resource ssc0_resource[] = { | |
1085 | PBMEM(0xffe01c00), | |
1086 | IRQ(10), | |
1087 | }; | |
1088 | DEFINE_DEV(ssc, 0); | |
1089 | DEV_CLK(pclk, ssc0, pba, 7); | |
1090 | ||
1091 | static struct resource ssc1_resource[] = { | |
1092 | PBMEM(0xffe02000), | |
1093 | IRQ(11), | |
1094 | }; | |
1095 | DEFINE_DEV(ssc, 1); | |
1096 | DEV_CLK(pclk, ssc1, pba, 8); | |
1097 | ||
1098 | static struct resource ssc2_resource[] = { | |
1099 | PBMEM(0xffe02400), | |
1100 | IRQ(12), | |
1101 | }; | |
1102 | DEFINE_DEV(ssc, 2); | |
1103 | DEV_CLK(pclk, ssc2, pba, 9); | |
1104 | ||
1105 | struct platform_device *__init | |
1106 | at32_add_device_ssc(unsigned int id, unsigned int flags) | |
1107 | { | |
1108 | struct platform_device *pdev; | |
1109 | ||
1110 | switch (id) { | |
1111 | case 0: | |
1112 | pdev = &ssc0_device; | |
1113 | if (flags & ATMEL_SSC_RF) | |
1114 | select_peripheral(PA(21), PERIPH_A, 0); /* RF */ | |
1115 | if (flags & ATMEL_SSC_RK) | |
1116 | select_peripheral(PA(22), PERIPH_A, 0); /* RK */ | |
1117 | if (flags & ATMEL_SSC_TK) | |
1118 | select_peripheral(PA(23), PERIPH_A, 0); /* TK */ | |
1119 | if (flags & ATMEL_SSC_TF) | |
1120 | select_peripheral(PA(24), PERIPH_A, 0); /* TF */ | |
1121 | if (flags & ATMEL_SSC_TD) | |
1122 | select_peripheral(PA(25), PERIPH_A, 0); /* TD */ | |
1123 | if (flags & ATMEL_SSC_RD) | |
1124 | select_peripheral(PA(26), PERIPH_A, 0); /* RD */ | |
1125 | break; | |
1126 | case 1: | |
1127 | pdev = &ssc1_device; | |
1128 | if (flags & ATMEL_SSC_RF) | |
1129 | select_peripheral(PA(0), PERIPH_B, 0); /* RF */ | |
1130 | if (flags & ATMEL_SSC_RK) | |
1131 | select_peripheral(PA(1), PERIPH_B, 0); /* RK */ | |
1132 | if (flags & ATMEL_SSC_TK) | |
1133 | select_peripheral(PA(2), PERIPH_B, 0); /* TK */ | |
1134 | if (flags & ATMEL_SSC_TF) | |
1135 | select_peripheral(PA(3), PERIPH_B, 0); /* TF */ | |
1136 | if (flags & ATMEL_SSC_TD) | |
1137 | select_peripheral(PA(4), PERIPH_B, 0); /* TD */ | |
1138 | if (flags & ATMEL_SSC_RD) | |
1139 | select_peripheral(PA(5), PERIPH_B, 0); /* RD */ | |
1140 | break; | |
1141 | case 2: | |
1142 | pdev = &ssc2_device; | |
1143 | if (flags & ATMEL_SSC_TD) | |
1144 | select_peripheral(PB(13), PERIPH_A, 0); /* TD */ | |
1145 | if (flags & ATMEL_SSC_RD) | |
1146 | select_peripheral(PB(14), PERIPH_A, 0); /* RD */ | |
1147 | if (flags & ATMEL_SSC_TK) | |
1148 | select_peripheral(PB(15), PERIPH_A, 0); /* TK */ | |
1149 | if (flags & ATMEL_SSC_TF) | |
1150 | select_peripheral(PB(16), PERIPH_A, 0); /* TF */ | |
1151 | if (flags & ATMEL_SSC_RF) | |
1152 | select_peripheral(PB(17), PERIPH_A, 0); /* RF */ | |
1153 | if (flags & ATMEL_SSC_RK) | |
1154 | select_peripheral(PB(18), PERIPH_A, 0); /* RK */ | |
1155 | break; | |
1156 | default: | |
1157 | return NULL; | |
1158 | } | |
1159 | ||
1160 | platform_device_register(pdev); | |
1161 | return pdev; | |
1162 | } | |
1163 | ||
7a5fe238 HS |
1164 | /* -------------------------------------------------------------------- |
1165 | * GCLK | |
1166 | * -------------------------------------------------------------------- */ | |
1167 | static struct clk gclk0 = { | |
1168 | .name = "gclk0", | |
1169 | .mode = genclk_mode, | |
1170 | .get_rate = genclk_get_rate, | |
1171 | .set_rate = genclk_set_rate, | |
1172 | .set_parent = genclk_set_parent, | |
1173 | .index = 0, | |
1174 | }; | |
1175 | static struct clk gclk1 = { | |
1176 | .name = "gclk1", | |
1177 | .mode = genclk_mode, | |
1178 | .get_rate = genclk_get_rate, | |
1179 | .set_rate = genclk_set_rate, | |
1180 | .set_parent = genclk_set_parent, | |
1181 | .index = 1, | |
1182 | }; | |
1183 | static struct clk gclk2 = { | |
1184 | .name = "gclk2", | |
1185 | .mode = genclk_mode, | |
1186 | .get_rate = genclk_get_rate, | |
1187 | .set_rate = genclk_set_rate, | |
1188 | .set_parent = genclk_set_parent, | |
1189 | .index = 2, | |
1190 | }; | |
1191 | static struct clk gclk3 = { | |
1192 | .name = "gclk3", | |
1193 | .mode = genclk_mode, | |
1194 | .get_rate = genclk_get_rate, | |
1195 | .set_rate = genclk_set_rate, | |
1196 | .set_parent = genclk_set_parent, | |
1197 | .index = 3, | |
1198 | }; | |
1199 | static struct clk gclk4 = { | |
1200 | .name = "gclk4", | |
1201 | .mode = genclk_mode, | |
1202 | .get_rate = genclk_get_rate, | |
1203 | .set_rate = genclk_set_rate, | |
1204 | .set_parent = genclk_set_parent, | |
1205 | .index = 4, | |
1206 | }; | |
1207 | ||
5f97f7f9 HS |
1208 | struct clk *at32_clock_list[] = { |
1209 | &osc32k, | |
1210 | &osc0, | |
1211 | &osc1, | |
1212 | &pll0, | |
1213 | &pll1, | |
1214 | &cpu_clk, | |
1215 | &hsb_clk, | |
1216 | &pba_clk, | |
1217 | &pbb_clk, | |
7a5b8059 | 1218 | &at32_pm_pclk, |
5f97f7f9 | 1219 | &at32_intc0_pclk, |
9c8f8e75 | 1220 | &hmatrix_clk, |
5f97f7f9 HS |
1221 | &ebi_clk, |
1222 | &hramc_clk, | |
bc157b75 HS |
1223 | &smc0_pclk, |
1224 | &smc0_mck, | |
5f97f7f9 HS |
1225 | &pdc_hclk, |
1226 | &pdc_pclk, | |
1227 | &pico_clk, | |
1228 | &pio0_mck, | |
1229 | &pio1_mck, | |
1230 | &pio2_mck, | |
1231 | &pio3_mck, | |
7f9f4678 | 1232 | &pio4_mck, |
7760989e | 1233 | &at32_systc0_pclk, |
1e8ea802 HS |
1234 | &atmel_usart0_usart, |
1235 | &atmel_usart1_usart, | |
1236 | &atmel_usart2_usart, | |
1237 | &atmel_usart3_usart, | |
5f97f7f9 HS |
1238 | &macb0_hclk, |
1239 | &macb0_pclk, | |
cfcb3a89 HS |
1240 | &macb1_hclk, |
1241 | &macb1_pclk, | |
3d60ee1b HS |
1242 | &atmel_spi0_spi_clk, |
1243 | &atmel_spi1_spi_clk, | |
d0a2b7af HS |
1244 | &atmel_lcdfb0_hck1, |
1245 | &atmel_lcdfb0_pixclk, | |
9cf6cf58 HCE |
1246 | &ssc0_pclk, |
1247 | &ssc1_pclk, | |
1248 | &ssc2_pclk, | |
7a5fe238 HS |
1249 | &gclk0, |
1250 | &gclk1, | |
1251 | &gclk2, | |
1252 | &gclk3, | |
1253 | &gclk4, | |
5f97f7f9 HS |
1254 | }; |
1255 | unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list); | |
1256 | ||
1257 | void __init at32_portmux_init(void) | |
1258 | { | |
1259 | at32_init_pio(&pio0_device); | |
1260 | at32_init_pio(&pio1_device); | |
1261 | at32_init_pio(&pio2_device); | |
1262 | at32_init_pio(&pio3_device); | |
7f9f4678 | 1263 | at32_init_pio(&pio4_device); |
5f97f7f9 HS |
1264 | } |
1265 | ||
1266 | void __init at32_clock_init(void) | |
1267 | { | |
5f97f7f9 HS |
1268 | u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0; |
1269 | int i; | |
1270 | ||
9e58e185 | 1271 | if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) { |
5f97f7f9 | 1272 | main_clock = &pll0; |
9e58e185 HCE |
1273 | cpu_clk.parent = &pll0; |
1274 | } else { | |
5f97f7f9 | 1275 | main_clock = &osc0; |
9e58e185 HCE |
1276 | cpu_clk.parent = &osc0; |
1277 | } | |
5f97f7f9 | 1278 | |
7a5b8059 | 1279 | if (pm_readl(PLL0) & PM_BIT(PLLOSC)) |
5f97f7f9 | 1280 | pll0.parent = &osc1; |
7a5b8059 | 1281 | if (pm_readl(PLL1) & PM_BIT(PLLOSC)) |
5f97f7f9 HS |
1282 | pll1.parent = &osc1; |
1283 | ||
7a5fe238 HS |
1284 | genclk_init_parent(&gclk0); |
1285 | genclk_init_parent(&gclk1); | |
1286 | genclk_init_parent(&gclk2); | |
1287 | genclk_init_parent(&gclk3); | |
1288 | genclk_init_parent(&gclk4); | |
d0a2b7af | 1289 | genclk_init_parent(&atmel_lcdfb0_pixclk); |
7a5fe238 | 1290 | |
5f97f7f9 HS |
1291 | /* |
1292 | * Turn on all clocks that have at least one user already, and | |
1293 | * turn off everything else. We only do this for module | |
1294 | * clocks, and even though it isn't particularly pretty to | |
1295 | * check the address of the mode function, it should do the | |
1296 | * trick... | |
1297 | */ | |
1298 | for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) { | |
1299 | struct clk *clk = at32_clock_list[i]; | |
1300 | ||
188ff65d HS |
1301 | if (clk->users == 0) |
1302 | continue; | |
1303 | ||
5f97f7f9 HS |
1304 | if (clk->mode == &cpu_clk_mode) |
1305 | cpu_mask |= 1 << clk->index; | |
1306 | else if (clk->mode == &hsb_clk_mode) | |
1307 | hsb_mask |= 1 << clk->index; | |
1308 | else if (clk->mode == &pba_clk_mode) | |
1309 | pba_mask |= 1 << clk->index; | |
1310 | else if (clk->mode == &pbb_clk_mode) | |
1311 | pbb_mask |= 1 << clk->index; | |
1312 | } | |
1313 | ||
7a5b8059 HS |
1314 | pm_writel(CPU_MASK, cpu_mask); |
1315 | pm_writel(HSB_MASK, hsb_mask); | |
1316 | pm_writel(PBA_MASK, pba_mask); | |
1317 | pm_writel(PBB_MASK, pbb_mask); | |
5f97f7f9 | 1318 | } |