Commit | Line | Data |
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5f97f7f9 HS |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | #include <linux/clk.h> | |
d0a2b7af | 9 | #include <linux/fb.h> |
5f97f7f9 HS |
10 | #include <linux/init.h> |
11 | #include <linux/platform_device.h> | |
6b84bbfc | 12 | #include <linux/dma-mapping.h> |
41d8ca45 | 13 | #include <linux/spi/spi.h> |
8d855317 | 14 | #include <linux/usb/atmel_usba_udc.h> |
5f97f7f9 HS |
15 | |
16 | #include <asm/io.h> | |
e7ba176b | 17 | #include <asm/irq.h> |
5f97f7f9 | 18 | |
438ff3f3 | 19 | #include <asm/arch/at32ap700x.h> |
5f97f7f9 HS |
20 | #include <asm/arch/board.h> |
21 | #include <asm/arch/portmux.h> | |
5f97f7f9 | 22 | |
d0a2b7af HS |
23 | #include <video/atmel_lcdc.h> |
24 | ||
5f97f7f9 | 25 | #include "clock.h" |
9c8f8e75 | 26 | #include "hmatrix.h" |
5f97f7f9 | 27 | #include "pio.h" |
7a5b8059 HS |
28 | #include "pm.h" |
29 | ||
5f97f7f9 HS |
30 | |
31 | #define PBMEM(base) \ | |
32 | { \ | |
33 | .start = base, \ | |
34 | .end = base + 0x3ff, \ | |
35 | .flags = IORESOURCE_MEM, \ | |
36 | } | |
37 | #define IRQ(num) \ | |
38 | { \ | |
39 | .start = num, \ | |
40 | .end = num, \ | |
41 | .flags = IORESOURCE_IRQ, \ | |
42 | } | |
43 | #define NAMED_IRQ(num, _name) \ | |
44 | { \ | |
45 | .start = num, \ | |
46 | .end = num, \ | |
47 | .name = _name, \ | |
48 | .flags = IORESOURCE_IRQ, \ | |
49 | } | |
50 | ||
6b84bbfc DB |
51 | /* REVISIT these assume *every* device supports DMA, but several |
52 | * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more. | |
53 | */ | |
5f97f7f9 | 54 | #define DEFINE_DEV(_name, _id) \ |
6b84bbfc | 55 | static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \ |
5f97f7f9 HS |
56 | static struct platform_device _name##_id##_device = { \ |
57 | .name = #_name, \ | |
58 | .id = _id, \ | |
6b84bbfc DB |
59 | .dev = { \ |
60 | .dma_mask = &_name##_id##_dma_mask, \ | |
61 | .coherent_dma_mask = DMA_32BIT_MASK, \ | |
62 | }, \ | |
5f97f7f9 HS |
63 | .resource = _name##_id##_resource, \ |
64 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
65 | } | |
66 | #define DEFINE_DEV_DATA(_name, _id) \ | |
6b84bbfc | 67 | static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \ |
5f97f7f9 HS |
68 | static struct platform_device _name##_id##_device = { \ |
69 | .name = #_name, \ | |
70 | .id = _id, \ | |
71 | .dev = { \ | |
6b84bbfc | 72 | .dma_mask = &_name##_id##_dma_mask, \ |
5f97f7f9 | 73 | .platform_data = &_name##_id##_data, \ |
6b84bbfc | 74 | .coherent_dma_mask = DMA_32BIT_MASK, \ |
5f97f7f9 HS |
75 | }, \ |
76 | .resource = _name##_id##_resource, \ | |
77 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
78 | } | |
79 | ||
c3e2a79c HS |
80 | #define select_peripheral(pin, periph, flags) \ |
81 | at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags) | |
82 | ||
5f97f7f9 HS |
83 | #define DEV_CLK(_name, devname, bus, _index) \ |
84 | static struct clk devname##_##_name = { \ | |
85 | .name = #_name, \ | |
86 | .dev = &devname##_device.dev, \ | |
87 | .parent = &bus##_clk, \ | |
88 | .mode = bus##_clk_mode, \ | |
89 | .get_rate = bus##_clk_get_rate, \ | |
90 | .index = _index, \ | |
91 | } | |
92 | ||
7a5b8059 HS |
93 | static DEFINE_SPINLOCK(pm_lock); |
94 | ||
5f97f7f9 HS |
95 | unsigned long at32ap7000_osc_rates[3] = { |
96 | [0] = 32768, | |
97 | /* FIXME: these are ATSTK1002-specific */ | |
98 | [1] = 20000000, | |
99 | [2] = 12000000, | |
100 | }; | |
101 | ||
102 | static unsigned long osc_get_rate(struct clk *clk) | |
103 | { | |
104 | return at32ap7000_osc_rates[clk->index]; | |
105 | } | |
106 | ||
107 | static unsigned long pll_get_rate(struct clk *clk, unsigned long control) | |
108 | { | |
109 | unsigned long div, mul, rate; | |
110 | ||
7a5b8059 | 111 | if (!(control & PM_BIT(PLLEN))) |
5f97f7f9 HS |
112 | return 0; |
113 | ||
7a5b8059 HS |
114 | div = PM_BFEXT(PLLDIV, control) + 1; |
115 | mul = PM_BFEXT(PLLMUL, control) + 1; | |
5f97f7f9 HS |
116 | |
117 | rate = clk->parent->get_rate(clk->parent); | |
118 | rate = (rate + div / 2) / div; | |
119 | rate *= mul; | |
120 | ||
121 | return rate; | |
122 | } | |
123 | ||
124 | static unsigned long pll0_get_rate(struct clk *clk) | |
125 | { | |
126 | u32 control; | |
127 | ||
7a5b8059 | 128 | control = pm_readl(PLL0); |
5f97f7f9 HS |
129 | |
130 | return pll_get_rate(clk, control); | |
131 | } | |
132 | ||
133 | static unsigned long pll1_get_rate(struct clk *clk) | |
134 | { | |
135 | u32 control; | |
136 | ||
7a5b8059 | 137 | control = pm_readl(PLL1); |
5f97f7f9 HS |
138 | |
139 | return pll_get_rate(clk, control); | |
140 | } | |
141 | ||
142 | /* | |
143 | * The AT32AP7000 has five primary clock sources: One 32kHz | |
144 | * oscillator, two crystal oscillators and two PLLs. | |
145 | */ | |
146 | static struct clk osc32k = { | |
147 | .name = "osc32k", | |
148 | .get_rate = osc_get_rate, | |
149 | .users = 1, | |
150 | .index = 0, | |
151 | }; | |
152 | static struct clk osc0 = { | |
153 | .name = "osc0", | |
154 | .get_rate = osc_get_rate, | |
155 | .users = 1, | |
156 | .index = 1, | |
157 | }; | |
158 | static struct clk osc1 = { | |
159 | .name = "osc1", | |
160 | .get_rate = osc_get_rate, | |
161 | .index = 2, | |
162 | }; | |
163 | static struct clk pll0 = { | |
164 | .name = "pll0", | |
165 | .get_rate = pll0_get_rate, | |
166 | .parent = &osc0, | |
167 | }; | |
168 | static struct clk pll1 = { | |
169 | .name = "pll1", | |
170 | .get_rate = pll1_get_rate, | |
171 | .parent = &osc0, | |
172 | }; | |
173 | ||
174 | /* | |
175 | * The main clock can be either osc0 or pll0. The boot loader may | |
176 | * have chosen one for us, so we don't really know which one until we | |
177 | * have a look at the SM. | |
178 | */ | |
179 | static struct clk *main_clock; | |
180 | ||
181 | /* | |
182 | * Synchronous clocks are generated from the main clock. The clocks | |
183 | * must satisfy the constraint | |
184 | * fCPU >= fHSB >= fPB | |
185 | * i.e. each clock must not be faster than its parent. | |
186 | */ | |
187 | static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift) | |
188 | { | |
189 | return main_clock->get_rate(main_clock) >> shift; | |
190 | }; | |
191 | ||
192 | static void cpu_clk_mode(struct clk *clk, int enabled) | |
193 | { | |
5f97f7f9 HS |
194 | unsigned long flags; |
195 | u32 mask; | |
196 | ||
7a5b8059 HS |
197 | spin_lock_irqsave(&pm_lock, flags); |
198 | mask = pm_readl(CPU_MASK); | |
5f97f7f9 HS |
199 | if (enabled) |
200 | mask |= 1 << clk->index; | |
201 | else | |
202 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
203 | pm_writel(CPU_MASK, mask); |
204 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
205 | } |
206 | ||
207 | static unsigned long cpu_clk_get_rate(struct clk *clk) | |
208 | { | |
209 | unsigned long cksel, shift = 0; | |
210 | ||
7a5b8059 HS |
211 | cksel = pm_readl(CKSEL); |
212 | if (cksel & PM_BIT(CPUDIV)) | |
213 | shift = PM_BFEXT(CPUSEL, cksel) + 1; | |
5f97f7f9 HS |
214 | |
215 | return bus_clk_get_rate(clk, shift); | |
216 | } | |
217 | ||
9e58e185 HCE |
218 | static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply) |
219 | { | |
220 | u32 control; | |
221 | unsigned long parent_rate, child_div, actual_rate, div; | |
222 | ||
223 | parent_rate = clk->parent->get_rate(clk->parent); | |
224 | control = pm_readl(CKSEL); | |
225 | ||
226 | if (control & PM_BIT(HSBDIV)) | |
227 | child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1); | |
228 | else | |
229 | child_div = 1; | |
230 | ||
231 | if (rate > 3 * (parent_rate / 4) || child_div == 1) { | |
232 | actual_rate = parent_rate; | |
233 | control &= ~PM_BIT(CPUDIV); | |
234 | } else { | |
235 | unsigned int cpusel; | |
236 | div = (parent_rate + rate / 2) / rate; | |
237 | if (div > child_div) | |
238 | div = child_div; | |
239 | cpusel = (div > 1) ? (fls(div) - 2) : 0; | |
240 | control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control); | |
241 | actual_rate = parent_rate / (1 << (cpusel + 1)); | |
242 | } | |
243 | ||
244 | pr_debug("clk %s: new rate %lu (actual rate %lu)\n", | |
245 | clk->name, rate, actual_rate); | |
246 | ||
247 | if (apply) | |
248 | pm_writel(CKSEL, control); | |
249 | ||
250 | return actual_rate; | |
251 | } | |
252 | ||
5f97f7f9 HS |
253 | static void hsb_clk_mode(struct clk *clk, int enabled) |
254 | { | |
5f97f7f9 HS |
255 | unsigned long flags; |
256 | u32 mask; | |
257 | ||
7a5b8059 HS |
258 | spin_lock_irqsave(&pm_lock, flags); |
259 | mask = pm_readl(HSB_MASK); | |
5f97f7f9 HS |
260 | if (enabled) |
261 | mask |= 1 << clk->index; | |
262 | else | |
263 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
264 | pm_writel(HSB_MASK, mask); |
265 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
266 | } |
267 | ||
268 | static unsigned long hsb_clk_get_rate(struct clk *clk) | |
269 | { | |
270 | unsigned long cksel, shift = 0; | |
271 | ||
7a5b8059 HS |
272 | cksel = pm_readl(CKSEL); |
273 | if (cksel & PM_BIT(HSBDIV)) | |
274 | shift = PM_BFEXT(HSBSEL, cksel) + 1; | |
5f97f7f9 HS |
275 | |
276 | return bus_clk_get_rate(clk, shift); | |
277 | } | |
278 | ||
279 | static void pba_clk_mode(struct clk *clk, int enabled) | |
280 | { | |
5f97f7f9 HS |
281 | unsigned long flags; |
282 | u32 mask; | |
283 | ||
7a5b8059 HS |
284 | spin_lock_irqsave(&pm_lock, flags); |
285 | mask = pm_readl(PBA_MASK); | |
5f97f7f9 HS |
286 | if (enabled) |
287 | mask |= 1 << clk->index; | |
288 | else | |
289 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
290 | pm_writel(PBA_MASK, mask); |
291 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
292 | } |
293 | ||
294 | static unsigned long pba_clk_get_rate(struct clk *clk) | |
295 | { | |
296 | unsigned long cksel, shift = 0; | |
297 | ||
7a5b8059 HS |
298 | cksel = pm_readl(CKSEL); |
299 | if (cksel & PM_BIT(PBADIV)) | |
300 | shift = PM_BFEXT(PBASEL, cksel) + 1; | |
5f97f7f9 HS |
301 | |
302 | return bus_clk_get_rate(clk, shift); | |
303 | } | |
304 | ||
305 | static void pbb_clk_mode(struct clk *clk, int enabled) | |
306 | { | |
5f97f7f9 HS |
307 | unsigned long flags; |
308 | u32 mask; | |
309 | ||
7a5b8059 HS |
310 | spin_lock_irqsave(&pm_lock, flags); |
311 | mask = pm_readl(PBB_MASK); | |
5f97f7f9 HS |
312 | if (enabled) |
313 | mask |= 1 << clk->index; | |
314 | else | |
315 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
316 | pm_writel(PBB_MASK, mask); |
317 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
318 | } |
319 | ||
320 | static unsigned long pbb_clk_get_rate(struct clk *clk) | |
321 | { | |
322 | unsigned long cksel, shift = 0; | |
323 | ||
7a5b8059 HS |
324 | cksel = pm_readl(CKSEL); |
325 | if (cksel & PM_BIT(PBBDIV)) | |
326 | shift = PM_BFEXT(PBBSEL, cksel) + 1; | |
5f97f7f9 HS |
327 | |
328 | return bus_clk_get_rate(clk, shift); | |
329 | } | |
330 | ||
331 | static struct clk cpu_clk = { | |
332 | .name = "cpu", | |
333 | .get_rate = cpu_clk_get_rate, | |
9e58e185 | 334 | .set_rate = cpu_clk_set_rate, |
5f97f7f9 HS |
335 | .users = 1, |
336 | }; | |
337 | static struct clk hsb_clk = { | |
338 | .name = "hsb", | |
339 | .parent = &cpu_clk, | |
340 | .get_rate = hsb_clk_get_rate, | |
341 | }; | |
342 | static struct clk pba_clk = { | |
343 | .name = "pba", | |
344 | .parent = &hsb_clk, | |
345 | .mode = hsb_clk_mode, | |
346 | .get_rate = pba_clk_get_rate, | |
347 | .index = 1, | |
348 | }; | |
349 | static struct clk pbb_clk = { | |
350 | .name = "pbb", | |
351 | .parent = &hsb_clk, | |
352 | .mode = hsb_clk_mode, | |
353 | .get_rate = pbb_clk_get_rate, | |
354 | .users = 1, | |
355 | .index = 2, | |
356 | }; | |
357 | ||
358 | /* -------------------------------------------------------------------- | |
359 | * Generic Clock operations | |
360 | * -------------------------------------------------------------------- */ | |
361 | ||
362 | static void genclk_mode(struct clk *clk, int enabled) | |
363 | { | |
364 | u32 control; | |
365 | ||
7a5b8059 | 366 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 | 367 | if (enabled) |
7a5b8059 | 368 | control |= PM_BIT(CEN); |
5f97f7f9 | 369 | else |
7a5b8059 HS |
370 | control &= ~PM_BIT(CEN); |
371 | pm_writel(GCCTRL(clk->index), control); | |
5f97f7f9 HS |
372 | } |
373 | ||
374 | static unsigned long genclk_get_rate(struct clk *clk) | |
375 | { | |
376 | u32 control; | |
377 | unsigned long div = 1; | |
378 | ||
7a5b8059 HS |
379 | control = pm_readl(GCCTRL(clk->index)); |
380 | if (control & PM_BIT(DIVEN)) | |
381 | div = 2 * (PM_BFEXT(DIV, control) + 1); | |
5f97f7f9 HS |
382 | |
383 | return clk->parent->get_rate(clk->parent) / div; | |
384 | } | |
385 | ||
386 | static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply) | |
387 | { | |
388 | u32 control; | |
389 | unsigned long parent_rate, actual_rate, div; | |
390 | ||
5f97f7f9 | 391 | parent_rate = clk->parent->get_rate(clk->parent); |
7a5b8059 | 392 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
393 | |
394 | if (rate > 3 * parent_rate / 4) { | |
395 | actual_rate = parent_rate; | |
7a5b8059 | 396 | control &= ~PM_BIT(DIVEN); |
5f97f7f9 HS |
397 | } else { |
398 | div = (parent_rate + rate) / (2 * rate) - 1; | |
7a5b8059 | 399 | control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN); |
5f97f7f9 HS |
400 | actual_rate = parent_rate / (2 * (div + 1)); |
401 | } | |
402 | ||
7a5b8059 HS |
403 | dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n", |
404 | clk->name, rate, actual_rate); | |
5f97f7f9 HS |
405 | |
406 | if (apply) | |
7a5b8059 | 407 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
408 | |
409 | return actual_rate; | |
410 | } | |
411 | ||
412 | int genclk_set_parent(struct clk *clk, struct clk *parent) | |
413 | { | |
414 | u32 control; | |
415 | ||
7a5b8059 HS |
416 | dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n", |
417 | clk->name, parent->name, clk->parent->name); | |
5f97f7f9 | 418 | |
7a5b8059 | 419 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
420 | |
421 | if (parent == &osc1 || parent == &pll1) | |
7a5b8059 | 422 | control |= PM_BIT(OSCSEL); |
5f97f7f9 | 423 | else if (parent == &osc0 || parent == &pll0) |
7a5b8059 | 424 | control &= ~PM_BIT(OSCSEL); |
5f97f7f9 HS |
425 | else |
426 | return -EINVAL; | |
427 | ||
428 | if (parent == &pll0 || parent == &pll1) | |
7a5b8059 | 429 | control |= PM_BIT(PLLSEL); |
5f97f7f9 | 430 | else |
7a5b8059 | 431 | control &= ~PM_BIT(PLLSEL); |
5f97f7f9 | 432 | |
7a5b8059 | 433 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
434 | clk->parent = parent; |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
7a5fe238 HS |
439 | static void __init genclk_init_parent(struct clk *clk) |
440 | { | |
441 | u32 control; | |
442 | struct clk *parent; | |
443 | ||
444 | BUG_ON(clk->index > 7); | |
445 | ||
7a5b8059 HS |
446 | control = pm_readl(GCCTRL(clk->index)); |
447 | if (control & PM_BIT(OSCSEL)) | |
448 | parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1; | |
7a5fe238 | 449 | else |
7a5b8059 | 450 | parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0; |
7a5fe238 HS |
451 | |
452 | clk->parent = parent; | |
453 | } | |
454 | ||
5f97f7f9 HS |
455 | /* -------------------------------------------------------------------- |
456 | * System peripherals | |
457 | * -------------------------------------------------------------------- */ | |
7a5b8059 HS |
458 | static struct resource at32_pm0_resource[] = { |
459 | { | |
460 | .start = 0xfff00000, | |
461 | .end = 0xfff0007f, | |
462 | .flags = IORESOURCE_MEM, | |
463 | }, | |
464 | IRQ(20), | |
5f97f7f9 | 465 | }; |
7a5b8059 HS |
466 | |
467 | static struct resource at32ap700x_rtc0_resource[] = { | |
468 | { | |
469 | .start = 0xfff00080, | |
470 | .end = 0xfff000af, | |
471 | .flags = IORESOURCE_MEM, | |
472 | }, | |
473 | IRQ(21), | |
5f97f7f9 | 474 | }; |
7a5b8059 HS |
475 | |
476 | static struct resource at32_wdt0_resource[] = { | |
477 | { | |
478 | .start = 0xfff000b0, | |
9797bed2 | 479 | .end = 0xfff000cf, |
7a5b8059 HS |
480 | .flags = IORESOURCE_MEM, |
481 | }, | |
482 | }; | |
483 | ||
484 | static struct resource at32_eic0_resource[] = { | |
485 | { | |
486 | .start = 0xfff00100, | |
487 | .end = 0xfff0013f, | |
488 | .flags = IORESOURCE_MEM, | |
489 | }, | |
490 | IRQ(19), | |
491 | }; | |
492 | ||
493 | DEFINE_DEV(at32_pm, 0); | |
494 | DEFINE_DEV(at32ap700x_rtc, 0); | |
495 | DEFINE_DEV(at32_wdt, 0); | |
496 | DEFINE_DEV(at32_eic, 0); | |
497 | ||
498 | /* | |
499 | * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this | |
500 | * is always running. | |
501 | */ | |
502 | static struct clk at32_pm_pclk = { | |
188ff65d | 503 | .name = "pclk", |
7a5b8059 | 504 | .dev = &at32_pm0_device.dev, |
188ff65d HS |
505 | .parent = &pbb_clk, |
506 | .mode = pbb_clk_mode, | |
507 | .get_rate = pbb_clk_get_rate, | |
508 | .users = 1, | |
509 | .index = 0, | |
510 | }; | |
5f97f7f9 HS |
511 | |
512 | static struct resource intc0_resource[] = { | |
513 | PBMEM(0xfff00400), | |
514 | }; | |
515 | struct platform_device at32_intc0_device = { | |
516 | .name = "intc", | |
517 | .id = 0, | |
518 | .resource = intc0_resource, | |
519 | .num_resources = ARRAY_SIZE(intc0_resource), | |
520 | }; | |
521 | DEV_CLK(pclk, at32_intc0, pbb, 1); | |
522 | ||
523 | static struct clk ebi_clk = { | |
524 | .name = "ebi", | |
525 | .parent = &hsb_clk, | |
526 | .mode = hsb_clk_mode, | |
527 | .get_rate = hsb_clk_get_rate, | |
528 | .users = 1, | |
529 | }; | |
530 | static struct clk hramc_clk = { | |
531 | .name = "hramc", | |
532 | .parent = &hsb_clk, | |
533 | .mode = hsb_clk_mode, | |
534 | .get_rate = hsb_clk_get_rate, | |
535 | .users = 1, | |
188ff65d | 536 | .index = 3, |
5f97f7f9 HS |
537 | }; |
538 | ||
bc157b75 HS |
539 | static struct resource smc0_resource[] = { |
540 | PBMEM(0xfff03400), | |
541 | }; | |
542 | DEFINE_DEV(smc, 0); | |
543 | DEV_CLK(pclk, smc0, pbb, 13); | |
544 | DEV_CLK(mck, smc0, hsb, 0); | |
545 | ||
5f97f7f9 HS |
546 | static struct platform_device pdc_device = { |
547 | .name = "pdc", | |
548 | .id = 0, | |
549 | }; | |
550 | DEV_CLK(hclk, pdc, hsb, 4); | |
551 | DEV_CLK(pclk, pdc, pba, 16); | |
552 | ||
553 | static struct clk pico_clk = { | |
554 | .name = "pico", | |
555 | .parent = &cpu_clk, | |
556 | .mode = cpu_clk_mode, | |
557 | .get_rate = cpu_clk_get_rate, | |
558 | .users = 1, | |
559 | }; | |
560 | ||
2042c1c4 HS |
561 | static struct resource dmaca0_resource[] = { |
562 | { | |
563 | .start = 0xff200000, | |
564 | .end = 0xff20ffff, | |
565 | .flags = IORESOURCE_MEM, | |
566 | }, | |
567 | IRQ(2), | |
568 | }; | |
569 | DEFINE_DEV(dmaca, 0); | |
570 | DEV_CLK(hclk, dmaca0, hsb, 10); | |
571 | ||
9c8f8e75 HS |
572 | /* -------------------------------------------------------------------- |
573 | * HMATRIX | |
574 | * -------------------------------------------------------------------- */ | |
575 | ||
576 | static struct clk hmatrix_clk = { | |
577 | .name = "hmatrix_clk", | |
578 | .parent = &pbb_clk, | |
579 | .mode = pbb_clk_mode, | |
580 | .get_rate = pbb_clk_get_rate, | |
581 | .index = 2, | |
582 | .users = 1, | |
583 | }; | |
584 | #define HMATRIX_BASE ((void __iomem *)0xfff00800) | |
585 | ||
586 | #define hmatrix_readl(reg) \ | |
587 | __raw_readl((HMATRIX_BASE) + HMATRIX_##reg) | |
588 | #define hmatrix_writel(reg,value) \ | |
589 | __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg) | |
590 | ||
591 | /* | |
592 | * Set bits in the HMATRIX Special Function Register (SFR) used by the | |
593 | * External Bus Interface (EBI). This can be used to enable special | |
594 | * features like CompactFlash support, NAND Flash support, etc. on | |
595 | * certain chipselects. | |
596 | */ | |
597 | static inline void set_ebi_sfr_bits(u32 mask) | |
598 | { | |
599 | u32 sfr; | |
600 | ||
601 | clk_enable(&hmatrix_clk); | |
602 | sfr = hmatrix_readl(SFR4); | |
603 | sfr |= mask; | |
604 | hmatrix_writel(SFR4, sfr); | |
605 | clk_disable(&hmatrix_clk); | |
606 | } | |
607 | ||
7760989e HCE |
608 | /* -------------------------------------------------------------------- |
609 | * System Timer/Counter (TC) | |
610 | * -------------------------------------------------------------------- */ | |
611 | static struct resource at32_systc0_resource[] = { | |
612 | PBMEM(0xfff00c00), | |
613 | IRQ(22), | |
614 | }; | |
615 | struct platform_device at32_systc0_device = { | |
616 | .name = "systc", | |
617 | .id = 0, | |
618 | .resource = at32_systc0_resource, | |
619 | .num_resources = ARRAY_SIZE(at32_systc0_resource), | |
620 | }; | |
621 | DEV_CLK(pclk, at32_systc0, pbb, 3); | |
622 | ||
5f97f7f9 HS |
623 | /* -------------------------------------------------------------------- |
624 | * PIO | |
625 | * -------------------------------------------------------------------- */ | |
626 | ||
627 | static struct resource pio0_resource[] = { | |
628 | PBMEM(0xffe02800), | |
629 | IRQ(13), | |
630 | }; | |
631 | DEFINE_DEV(pio, 0); | |
632 | DEV_CLK(mck, pio0, pba, 10); | |
633 | ||
634 | static struct resource pio1_resource[] = { | |
635 | PBMEM(0xffe02c00), | |
636 | IRQ(14), | |
637 | }; | |
638 | DEFINE_DEV(pio, 1); | |
639 | DEV_CLK(mck, pio1, pba, 11); | |
640 | ||
641 | static struct resource pio2_resource[] = { | |
642 | PBMEM(0xffe03000), | |
643 | IRQ(15), | |
644 | }; | |
645 | DEFINE_DEV(pio, 2); | |
646 | DEV_CLK(mck, pio2, pba, 12); | |
647 | ||
648 | static struct resource pio3_resource[] = { | |
649 | PBMEM(0xffe03400), | |
650 | IRQ(16), | |
651 | }; | |
652 | DEFINE_DEV(pio, 3); | |
653 | DEV_CLK(mck, pio3, pba, 13); | |
654 | ||
7f9f4678 HS |
655 | static struct resource pio4_resource[] = { |
656 | PBMEM(0xffe03800), | |
657 | IRQ(17), | |
658 | }; | |
659 | DEFINE_DEV(pio, 4); | |
660 | DEV_CLK(mck, pio4, pba, 14); | |
661 | ||
5f97f7f9 HS |
662 | void __init at32_add_system_devices(void) |
663 | { | |
7a5b8059 | 664 | platform_device_register(&at32_pm0_device); |
5f97f7f9 | 665 | platform_device_register(&at32_intc0_device); |
7a5b8059 HS |
666 | platform_device_register(&at32ap700x_rtc0_device); |
667 | platform_device_register(&at32_wdt0_device); | |
668 | platform_device_register(&at32_eic0_device); | |
bc157b75 | 669 | platform_device_register(&smc0_device); |
5f97f7f9 | 670 | platform_device_register(&pdc_device); |
2042c1c4 | 671 | platform_device_register(&dmaca0_device); |
5f97f7f9 | 672 | |
7760989e HCE |
673 | platform_device_register(&at32_systc0_device); |
674 | ||
5f97f7f9 HS |
675 | platform_device_register(&pio0_device); |
676 | platform_device_register(&pio1_device); | |
677 | platform_device_register(&pio2_device); | |
678 | platform_device_register(&pio3_device); | |
7f9f4678 | 679 | platform_device_register(&pio4_device); |
5f97f7f9 HS |
680 | } |
681 | ||
682 | /* -------------------------------------------------------------------- | |
683 | * USART | |
684 | * -------------------------------------------------------------------- */ | |
685 | ||
75d35213 HS |
686 | static struct atmel_uart_data atmel_usart0_data = { |
687 | .use_dma_tx = 1, | |
688 | .use_dma_rx = 1, | |
689 | }; | |
1e8ea802 | 690 | static struct resource atmel_usart0_resource[] = { |
5f97f7f9 | 691 | PBMEM(0xffe00c00), |
a3d912c8 | 692 | IRQ(6), |
5f97f7f9 | 693 | }; |
75d35213 | 694 | DEFINE_DEV_DATA(atmel_usart, 0); |
80f76c54 | 695 | DEV_CLK(usart, atmel_usart0, pba, 3); |
5f97f7f9 | 696 | |
75d35213 HS |
697 | static struct atmel_uart_data atmel_usart1_data = { |
698 | .use_dma_tx = 1, | |
699 | .use_dma_rx = 1, | |
700 | }; | |
1e8ea802 | 701 | static struct resource atmel_usart1_resource[] = { |
5f97f7f9 HS |
702 | PBMEM(0xffe01000), |
703 | IRQ(7), | |
704 | }; | |
75d35213 | 705 | DEFINE_DEV_DATA(atmel_usart, 1); |
1e8ea802 | 706 | DEV_CLK(usart, atmel_usart1, pba, 4); |
5f97f7f9 | 707 | |
75d35213 HS |
708 | static struct atmel_uart_data atmel_usart2_data = { |
709 | .use_dma_tx = 1, | |
710 | .use_dma_rx = 1, | |
711 | }; | |
1e8ea802 | 712 | static struct resource atmel_usart2_resource[] = { |
5f97f7f9 HS |
713 | PBMEM(0xffe01400), |
714 | IRQ(8), | |
715 | }; | |
75d35213 | 716 | DEFINE_DEV_DATA(atmel_usart, 2); |
1e8ea802 | 717 | DEV_CLK(usart, atmel_usart2, pba, 5); |
5f97f7f9 | 718 | |
75d35213 HS |
719 | static struct atmel_uart_data atmel_usart3_data = { |
720 | .use_dma_tx = 1, | |
721 | .use_dma_rx = 1, | |
722 | }; | |
1e8ea802 | 723 | static struct resource atmel_usart3_resource[] = { |
5f97f7f9 HS |
724 | PBMEM(0xffe01800), |
725 | IRQ(9), | |
726 | }; | |
75d35213 | 727 | DEFINE_DEV_DATA(atmel_usart, 3); |
1e8ea802 | 728 | DEV_CLK(usart, atmel_usart3, pba, 6); |
5f97f7f9 HS |
729 | |
730 | static inline void configure_usart0_pins(void) | |
731 | { | |
c3e2a79c HS |
732 | select_peripheral(PA(8), PERIPH_B, 0); /* RXD */ |
733 | select_peripheral(PA(9), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
734 | } |
735 | ||
736 | static inline void configure_usart1_pins(void) | |
737 | { | |
c3e2a79c HS |
738 | select_peripheral(PA(17), PERIPH_A, 0); /* RXD */ |
739 | select_peripheral(PA(18), PERIPH_A, 0); /* TXD */ | |
5f97f7f9 HS |
740 | } |
741 | ||
742 | static inline void configure_usart2_pins(void) | |
743 | { | |
c3e2a79c HS |
744 | select_peripheral(PB(26), PERIPH_B, 0); /* RXD */ |
745 | select_peripheral(PB(27), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
746 | } |
747 | ||
748 | static inline void configure_usart3_pins(void) | |
749 | { | |
c3e2a79c HS |
750 | select_peripheral(PB(18), PERIPH_B, 0); /* RXD */ |
751 | select_peripheral(PB(17), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
752 | } |
753 | ||
a3d912c8 | 754 | static struct platform_device *__initdata at32_usarts[4]; |
c194588d HS |
755 | |
756 | void __init at32_map_usart(unsigned int hw_id, unsigned int line) | |
5f97f7f9 HS |
757 | { |
758 | struct platform_device *pdev; | |
759 | ||
c194588d | 760 | switch (hw_id) { |
5f97f7f9 | 761 | case 0: |
1e8ea802 | 762 | pdev = &atmel_usart0_device; |
5f97f7f9 HS |
763 | configure_usart0_pins(); |
764 | break; | |
765 | case 1: | |
1e8ea802 | 766 | pdev = &atmel_usart1_device; |
5f97f7f9 HS |
767 | configure_usart1_pins(); |
768 | break; | |
769 | case 2: | |
1e8ea802 | 770 | pdev = &atmel_usart2_device; |
5f97f7f9 HS |
771 | configure_usart2_pins(); |
772 | break; | |
773 | case 3: | |
1e8ea802 | 774 | pdev = &atmel_usart3_device; |
5f97f7f9 HS |
775 | configure_usart3_pins(); |
776 | break; | |
777 | default: | |
c194588d | 778 | return; |
75d35213 HS |
779 | } |
780 | ||
781 | if (PXSEG(pdev->resource[0].start) == P4SEG) { | |
782 | /* Addresses in the P4 segment are permanently mapped 1:1 */ | |
783 | struct atmel_uart_data *data = pdev->dev.platform_data; | |
784 | data->regs = (void __iomem *)pdev->resource[0].start; | |
5f97f7f9 HS |
785 | } |
786 | ||
c194588d HS |
787 | pdev->id = line; |
788 | at32_usarts[line] = pdev; | |
5f97f7f9 HS |
789 | } |
790 | ||
791 | struct platform_device *__init at32_add_device_usart(unsigned int id) | |
792 | { | |
c194588d HS |
793 | platform_device_register(at32_usarts[id]); |
794 | return at32_usarts[id]; | |
5f97f7f9 HS |
795 | } |
796 | ||
73e2798b | 797 | struct platform_device *atmel_default_console_device; |
5f97f7f9 HS |
798 | |
799 | void __init at32_setup_serial_console(unsigned int usart_id) | |
800 | { | |
c194588d | 801 | atmel_default_console_device = at32_usarts[usart_id]; |
5f97f7f9 HS |
802 | } |
803 | ||
804 | /* -------------------------------------------------------------------- | |
805 | * Ethernet | |
806 | * -------------------------------------------------------------------- */ | |
807 | ||
438ff3f3 | 808 | #ifdef CONFIG_CPU_AT32AP7000 |
5f97f7f9 HS |
809 | static struct eth_platform_data macb0_data; |
810 | static struct resource macb0_resource[] = { | |
811 | PBMEM(0xfff01800), | |
812 | IRQ(25), | |
813 | }; | |
814 | DEFINE_DEV_DATA(macb, 0); | |
815 | DEV_CLK(hclk, macb0, hsb, 8); | |
816 | DEV_CLK(pclk, macb0, pbb, 6); | |
817 | ||
cfcb3a89 HS |
818 | static struct eth_platform_data macb1_data; |
819 | static struct resource macb1_resource[] = { | |
820 | PBMEM(0xfff01c00), | |
821 | IRQ(26), | |
822 | }; | |
823 | DEFINE_DEV_DATA(macb, 1); | |
824 | DEV_CLK(hclk, macb1, hsb, 9); | |
825 | DEV_CLK(pclk, macb1, pbb, 7); | |
826 | ||
5f97f7f9 HS |
827 | struct platform_device *__init |
828 | at32_add_device_eth(unsigned int id, struct eth_platform_data *data) | |
829 | { | |
830 | struct platform_device *pdev; | |
831 | ||
832 | switch (id) { | |
833 | case 0: | |
834 | pdev = &macb0_device; | |
835 | ||
c3e2a79c HS |
836 | select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */ |
837 | select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */ | |
838 | select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */ | |
839 | select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */ | |
840 | select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */ | |
841 | select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */ | |
842 | select_peripheral(PC(13), PERIPH_A, 0); /* RXER */ | |
843 | select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */ | |
844 | select_peripheral(PC(16), PERIPH_A, 0); /* MDC */ | |
845 | select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */ | |
5f97f7f9 HS |
846 | |
847 | if (!data->is_rmii) { | |
c3e2a79c HS |
848 | select_peripheral(PC(0), PERIPH_A, 0); /* COL */ |
849 | select_peripheral(PC(1), PERIPH_A, 0); /* CRS */ | |
850 | select_peripheral(PC(2), PERIPH_A, 0); /* TXER */ | |
851 | select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */ | |
852 | select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */ | |
853 | select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */ | |
854 | select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */ | |
855 | select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */ | |
856 | select_peripheral(PC(18), PERIPH_A, 0); /* SPD */ | |
5f97f7f9 HS |
857 | } |
858 | break; | |
859 | ||
cfcb3a89 HS |
860 | case 1: |
861 | pdev = &macb1_device; | |
862 | ||
863 | select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */ | |
864 | select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */ | |
865 | select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */ | |
866 | select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */ | |
867 | select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */ | |
868 | select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */ | |
869 | select_peripheral(PD(5), PERIPH_B, 0); /* RXER */ | |
870 | select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */ | |
871 | select_peripheral(PD(3), PERIPH_B, 0); /* MDC */ | |
872 | select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */ | |
873 | ||
874 | if (!data->is_rmii) { | |
875 | select_peripheral(PC(19), PERIPH_B, 0); /* COL */ | |
876 | select_peripheral(PC(23), PERIPH_B, 0); /* CRS */ | |
877 | select_peripheral(PC(26), PERIPH_B, 0); /* TXER */ | |
878 | select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */ | |
879 | select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */ | |
880 | select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */ | |
881 | select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */ | |
882 | select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */ | |
883 | select_peripheral(PD(15), PERIPH_B, 0); /* SPD */ | |
884 | } | |
885 | break; | |
886 | ||
5f97f7f9 HS |
887 | default: |
888 | return NULL; | |
889 | } | |
890 | ||
891 | memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data)); | |
892 | platform_device_register(pdev); | |
893 | ||
894 | return pdev; | |
895 | } | |
438ff3f3 | 896 | #endif |
5f97f7f9 HS |
897 | |
898 | /* -------------------------------------------------------------------- | |
899 | * SPI | |
900 | * -------------------------------------------------------------------- */ | |
3d60ee1b | 901 | static struct resource atmel_spi0_resource[] = { |
5f97f7f9 HS |
902 | PBMEM(0xffe00000), |
903 | IRQ(3), | |
904 | }; | |
3d60ee1b HS |
905 | DEFINE_DEV(atmel_spi, 0); |
906 | DEV_CLK(spi_clk, atmel_spi0, pba, 0); | |
907 | ||
908 | static struct resource atmel_spi1_resource[] = { | |
909 | PBMEM(0xffe00400), | |
910 | IRQ(4), | |
911 | }; | |
912 | DEFINE_DEV(atmel_spi, 1); | |
913 | DEV_CLK(spi_clk, atmel_spi1, pba, 1); | |
5f97f7f9 | 914 | |
9a596a62 | 915 | static void __init |
41d8ca45 HS |
916 | at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, |
917 | unsigned int n, const u8 *pins) | |
5f97f7f9 | 918 | { |
41d8ca45 HS |
919 | unsigned int pin, mode; |
920 | ||
921 | for (; n; n--, b++) { | |
922 | b->bus_num = bus_num; | |
923 | if (b->chip_select >= 4) | |
924 | continue; | |
925 | pin = (unsigned)b->controller_data; | |
926 | if (!pin) { | |
927 | pin = pins[b->chip_select]; | |
928 | b->controller_data = (void *)pin; | |
929 | } | |
930 | mode = AT32_GPIOF_OUTPUT; | |
931 | if (!(b->mode & SPI_CS_HIGH)) | |
932 | mode |= AT32_GPIOF_HIGH; | |
933 | at32_select_gpio(pin, mode); | |
934 | } | |
935 | } | |
936 | ||
937 | struct platform_device *__init | |
938 | at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n) | |
939 | { | |
940 | /* | |
941 | * Manage the chipselects as GPIOs, normally using the same pins | |
942 | * the SPI controller expects; but boards can use other pins. | |
943 | */ | |
944 | static u8 __initdata spi0_pins[] = | |
945 | { GPIO_PIN_PA(3), GPIO_PIN_PA(4), | |
946 | GPIO_PIN_PA(5), GPIO_PIN_PA(20), }; | |
947 | static u8 __initdata spi1_pins[] = | |
948 | { GPIO_PIN_PB(2), GPIO_PIN_PB(3), | |
949 | GPIO_PIN_PB(4), GPIO_PIN_PA(27), }; | |
5f97f7f9 HS |
950 | struct platform_device *pdev; |
951 | ||
952 | switch (id) { | |
953 | case 0: | |
3d60ee1b | 954 | pdev = &atmel_spi0_device; |
c3e2a79c HS |
955 | select_peripheral(PA(0), PERIPH_A, 0); /* MISO */ |
956 | select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */ | |
957 | select_peripheral(PA(2), PERIPH_A, 0); /* SCK */ | |
41d8ca45 | 958 | at32_spi_setup_slaves(0, b, n, spi0_pins); |
3d60ee1b HS |
959 | break; |
960 | ||
961 | case 1: | |
962 | pdev = &atmel_spi1_device; | |
963 | select_peripheral(PB(0), PERIPH_B, 0); /* MISO */ | |
964 | select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */ | |
965 | select_peripheral(PB(5), PERIPH_B, 0); /* SCK */ | |
41d8ca45 | 966 | at32_spi_setup_slaves(1, b, n, spi1_pins); |
5f97f7f9 HS |
967 | break; |
968 | ||
969 | default: | |
970 | return NULL; | |
971 | } | |
972 | ||
41d8ca45 | 973 | spi_register_board_info(b, n); |
5f97f7f9 HS |
974 | platform_device_register(pdev); |
975 | return pdev; | |
976 | } | |
977 | ||
2042c1c4 HS |
978 | /* -------------------------------------------------------------------- |
979 | * TWI | |
980 | * -------------------------------------------------------------------- */ | |
981 | static struct resource atmel_twi0_resource[] __initdata = { | |
982 | PBMEM(0xffe00800), | |
983 | IRQ(5), | |
984 | }; | |
985 | static struct clk atmel_twi0_pclk = { | |
986 | .name = "twi_pclk", | |
987 | .parent = &pba_clk, | |
988 | .mode = pba_clk_mode, | |
989 | .get_rate = pba_clk_get_rate, | |
990 | .index = 2, | |
991 | }; | |
992 | ||
040b28fc BN |
993 | struct platform_device *__init at32_add_device_twi(unsigned int id, |
994 | struct i2c_board_info *b, | |
995 | unsigned int n) | |
2042c1c4 HS |
996 | { |
997 | struct platform_device *pdev; | |
998 | ||
999 | if (id != 0) | |
1000 | return NULL; | |
1001 | ||
1002 | pdev = platform_device_alloc("atmel_twi", id); | |
1003 | if (!pdev) | |
1004 | return NULL; | |
1005 | ||
1006 | if (platform_device_add_resources(pdev, atmel_twi0_resource, | |
1007 | ARRAY_SIZE(atmel_twi0_resource))) | |
1008 | goto err_add_resources; | |
1009 | ||
1010 | select_peripheral(PA(6), PERIPH_A, 0); /* SDA */ | |
1011 | select_peripheral(PA(7), PERIPH_A, 0); /* SDL */ | |
1012 | ||
1013 | atmel_twi0_pclk.dev = &pdev->dev; | |
1014 | ||
040b28fc BN |
1015 | if (b) |
1016 | i2c_register_board_info(id, b, n); | |
1017 | ||
2042c1c4 HS |
1018 | platform_device_add(pdev); |
1019 | return pdev; | |
1020 | ||
1021 | err_add_resources: | |
1022 | platform_device_put(pdev); | |
1023 | return NULL; | |
1024 | } | |
1025 | ||
1026 | /* -------------------------------------------------------------------- | |
1027 | * MMC | |
1028 | * -------------------------------------------------------------------- */ | |
1029 | static struct resource atmel_mci0_resource[] __initdata = { | |
1030 | PBMEM(0xfff02400), | |
1031 | IRQ(28), | |
1032 | }; | |
1033 | static struct clk atmel_mci0_pclk = { | |
1034 | .name = "mci_clk", | |
1035 | .parent = &pbb_clk, | |
1036 | .mode = pbb_clk_mode, | |
1037 | .get_rate = pbb_clk_get_rate, | |
1038 | .index = 9, | |
1039 | }; | |
1040 | ||
1041 | struct platform_device *__init at32_add_device_mci(unsigned int id) | |
1042 | { | |
1043 | struct platform_device *pdev; | |
1044 | ||
1045 | if (id != 0) | |
1046 | return NULL; | |
1047 | ||
1048 | pdev = platform_device_alloc("atmel_mci", id); | |
1049 | if (!pdev) | |
1050 | return NULL; | |
1051 | ||
1052 | if (platform_device_add_resources(pdev, atmel_mci0_resource, | |
1053 | ARRAY_SIZE(atmel_mci0_resource))) | |
1054 | goto err_add_resources; | |
1055 | ||
1056 | select_peripheral(PA(10), PERIPH_A, 0); /* CLK */ | |
1057 | select_peripheral(PA(11), PERIPH_A, 0); /* CMD */ | |
1058 | select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */ | |
1059 | select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */ | |
1060 | select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */ | |
1061 | select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */ | |
1062 | ||
1063 | atmel_mci0_pclk.dev = &pdev->dev; | |
1064 | ||
1065 | platform_device_add(pdev); | |
1066 | return pdev; | |
1067 | ||
1068 | err_add_resources: | |
1069 | platform_device_put(pdev); | |
1070 | return NULL; | |
1071 | } | |
1072 | ||
5f97f7f9 HS |
1073 | /* -------------------------------------------------------------------- |
1074 | * LCDC | |
1075 | * -------------------------------------------------------------------- */ | |
438ff3f3 | 1076 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af HS |
1077 | static struct atmel_lcdfb_info atmel_lcdfb0_data; |
1078 | static struct resource atmel_lcdfb0_resource[] = { | |
5f97f7f9 HS |
1079 | { |
1080 | .start = 0xff000000, | |
1081 | .end = 0xff000fff, | |
1082 | .flags = IORESOURCE_MEM, | |
1083 | }, | |
1084 | IRQ(1), | |
d0a2b7af HS |
1085 | { |
1086 | /* Placeholder for pre-allocated fb memory */ | |
1087 | .start = 0x00000000, | |
1088 | .end = 0x00000000, | |
1089 | .flags = 0, | |
1090 | }, | |
5f97f7f9 | 1091 | }; |
d0a2b7af HS |
1092 | DEFINE_DEV_DATA(atmel_lcdfb, 0); |
1093 | DEV_CLK(hck1, atmel_lcdfb0, hsb, 7); | |
1094 | static struct clk atmel_lcdfb0_pixclk = { | |
1095 | .name = "lcdc_clk", | |
1096 | .dev = &atmel_lcdfb0_device.dev, | |
5f97f7f9 HS |
1097 | .mode = genclk_mode, |
1098 | .get_rate = genclk_get_rate, | |
1099 | .set_rate = genclk_set_rate, | |
1100 | .set_parent = genclk_set_parent, | |
1101 | .index = 7, | |
1102 | }; | |
1103 | ||
1104 | struct platform_device *__init | |
d0a2b7af HS |
1105 | at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, |
1106 | unsigned long fbmem_start, unsigned long fbmem_len) | |
5f97f7f9 HS |
1107 | { |
1108 | struct platform_device *pdev; | |
d0a2b7af HS |
1109 | struct atmel_lcdfb_info *info; |
1110 | struct fb_monspecs *monspecs; | |
1111 | struct fb_videomode *modedb; | |
1112 | unsigned int modedb_size; | |
1113 | ||
1114 | /* | |
1115 | * Do a deep copy of the fb data, monspecs and modedb. Make | |
1116 | * sure all allocations are done before setting up the | |
1117 | * portmux. | |
1118 | */ | |
1119 | monspecs = kmemdup(data->default_monspecs, | |
1120 | sizeof(struct fb_monspecs), GFP_KERNEL); | |
1121 | if (!monspecs) | |
1122 | return NULL; | |
1123 | ||
1124 | modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len; | |
1125 | modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL); | |
1126 | if (!modedb) | |
1127 | goto err_dup_modedb; | |
1128 | monspecs->modedb = modedb; | |
5f97f7f9 HS |
1129 | |
1130 | switch (id) { | |
1131 | case 0: | |
d0a2b7af | 1132 | pdev = &atmel_lcdfb0_device; |
c3e2a79c HS |
1133 | select_peripheral(PC(19), PERIPH_A, 0); /* CC */ |
1134 | select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */ | |
1135 | select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */ | |
1136 | select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */ | |
1137 | select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */ | |
1138 | select_peripheral(PC(24), PERIPH_A, 0); /* MODE */ | |
1139 | select_peripheral(PC(25), PERIPH_A, 0); /* PWR */ | |
1140 | select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */ | |
1141 | select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */ | |
1142 | select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */ | |
1143 | select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */ | |
1144 | select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */ | |
1145 | select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */ | |
1146 | select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */ | |
1147 | select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */ | |
1148 | select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */ | |
1149 | select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */ | |
1150 | select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */ | |
1151 | select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */ | |
1152 | select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */ | |
1153 | select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */ | |
1154 | select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */ | |
1155 | select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */ | |
1156 | select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */ | |
1157 | select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */ | |
1158 | select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */ | |
1159 | select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */ | |
1160 | select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */ | |
1161 | select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */ | |
1162 | select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */ | |
1163 | select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */ | |
5f97f7f9 | 1164 | |
d0a2b7af HS |
1165 | clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); |
1166 | clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); | |
5f97f7f9 HS |
1167 | break; |
1168 | ||
1169 | default: | |
d0a2b7af | 1170 | goto err_invalid_id; |
5f97f7f9 HS |
1171 | } |
1172 | ||
d0a2b7af HS |
1173 | if (fbmem_len) { |
1174 | pdev->resource[2].start = fbmem_start; | |
1175 | pdev->resource[2].end = fbmem_start + fbmem_len - 1; | |
1176 | pdev->resource[2].flags = IORESOURCE_MEM; | |
1177 | } | |
1178 | ||
1179 | info = pdev->dev.platform_data; | |
1180 | memcpy(info, data, sizeof(struct atmel_lcdfb_info)); | |
1181 | info->default_monspecs = monspecs; | |
5f97f7f9 HS |
1182 | |
1183 | platform_device_register(pdev); | |
1184 | return pdev; | |
d0a2b7af HS |
1185 | |
1186 | err_invalid_id: | |
1187 | kfree(modedb); | |
1188 | err_dup_modedb: | |
1189 | kfree(monspecs); | |
1190 | return NULL; | |
5f97f7f9 | 1191 | } |
438ff3f3 | 1192 | #endif |
5f97f7f9 | 1193 | |
9a1e8eb1 DB |
1194 | /* -------------------------------------------------------------------- |
1195 | * PWM | |
1196 | * -------------------------------------------------------------------- */ | |
1197 | static struct resource atmel_pwm0_resource[] __initdata = { | |
1198 | PBMEM(0xfff01400), | |
1199 | IRQ(24), | |
1200 | }; | |
1201 | static struct clk atmel_pwm0_mck = { | |
1202 | .name = "mck", | |
1203 | .parent = &pbb_clk, | |
1204 | .mode = pbb_clk_mode, | |
1205 | .get_rate = pbb_clk_get_rate, | |
1206 | .index = 5, | |
1207 | }; | |
1208 | ||
1209 | struct platform_device *__init at32_add_device_pwm(u32 mask) | |
1210 | { | |
1211 | struct platform_device *pdev; | |
1212 | ||
1213 | if (!mask) | |
1214 | return NULL; | |
1215 | ||
1216 | pdev = platform_device_alloc("atmel_pwm", 0); | |
1217 | if (!pdev) | |
1218 | return NULL; | |
1219 | ||
1220 | if (platform_device_add_resources(pdev, atmel_pwm0_resource, | |
1221 | ARRAY_SIZE(atmel_pwm0_resource))) | |
1222 | goto out_free_pdev; | |
1223 | ||
1224 | if (platform_device_add_data(pdev, &mask, sizeof(mask))) | |
1225 | goto out_free_pdev; | |
1226 | ||
1227 | if (mask & (1 << 0)) | |
1228 | select_peripheral(PA(28), PERIPH_A, 0); | |
1229 | if (mask & (1 << 1)) | |
1230 | select_peripheral(PA(29), PERIPH_A, 0); | |
1231 | if (mask & (1 << 2)) | |
1232 | select_peripheral(PA(21), PERIPH_B, 0); | |
1233 | if (mask & (1 << 3)) | |
1234 | select_peripheral(PA(22), PERIPH_B, 0); | |
1235 | ||
1236 | atmel_pwm0_mck.dev = &pdev->dev; | |
1237 | ||
1238 | platform_device_add(pdev); | |
1239 | ||
1240 | return pdev; | |
1241 | ||
1242 | out_free_pdev: | |
1243 | platform_device_put(pdev); | |
1244 | return NULL; | |
1245 | } | |
1246 | ||
9cf6cf58 HCE |
1247 | /* -------------------------------------------------------------------- |
1248 | * SSC | |
1249 | * -------------------------------------------------------------------- */ | |
1250 | static struct resource ssc0_resource[] = { | |
1251 | PBMEM(0xffe01c00), | |
1252 | IRQ(10), | |
1253 | }; | |
1254 | DEFINE_DEV(ssc, 0); | |
1255 | DEV_CLK(pclk, ssc0, pba, 7); | |
1256 | ||
1257 | static struct resource ssc1_resource[] = { | |
1258 | PBMEM(0xffe02000), | |
1259 | IRQ(11), | |
1260 | }; | |
1261 | DEFINE_DEV(ssc, 1); | |
1262 | DEV_CLK(pclk, ssc1, pba, 8); | |
1263 | ||
1264 | static struct resource ssc2_resource[] = { | |
1265 | PBMEM(0xffe02400), | |
1266 | IRQ(12), | |
1267 | }; | |
1268 | DEFINE_DEV(ssc, 2); | |
1269 | DEV_CLK(pclk, ssc2, pba, 9); | |
1270 | ||
1271 | struct platform_device *__init | |
1272 | at32_add_device_ssc(unsigned int id, unsigned int flags) | |
1273 | { | |
1274 | struct platform_device *pdev; | |
1275 | ||
1276 | switch (id) { | |
1277 | case 0: | |
1278 | pdev = &ssc0_device; | |
1279 | if (flags & ATMEL_SSC_RF) | |
1280 | select_peripheral(PA(21), PERIPH_A, 0); /* RF */ | |
1281 | if (flags & ATMEL_SSC_RK) | |
1282 | select_peripheral(PA(22), PERIPH_A, 0); /* RK */ | |
1283 | if (flags & ATMEL_SSC_TK) | |
1284 | select_peripheral(PA(23), PERIPH_A, 0); /* TK */ | |
1285 | if (flags & ATMEL_SSC_TF) | |
1286 | select_peripheral(PA(24), PERIPH_A, 0); /* TF */ | |
1287 | if (flags & ATMEL_SSC_TD) | |
1288 | select_peripheral(PA(25), PERIPH_A, 0); /* TD */ | |
1289 | if (flags & ATMEL_SSC_RD) | |
1290 | select_peripheral(PA(26), PERIPH_A, 0); /* RD */ | |
1291 | break; | |
1292 | case 1: | |
1293 | pdev = &ssc1_device; | |
1294 | if (flags & ATMEL_SSC_RF) | |
1295 | select_peripheral(PA(0), PERIPH_B, 0); /* RF */ | |
1296 | if (flags & ATMEL_SSC_RK) | |
1297 | select_peripheral(PA(1), PERIPH_B, 0); /* RK */ | |
1298 | if (flags & ATMEL_SSC_TK) | |
1299 | select_peripheral(PA(2), PERIPH_B, 0); /* TK */ | |
1300 | if (flags & ATMEL_SSC_TF) | |
1301 | select_peripheral(PA(3), PERIPH_B, 0); /* TF */ | |
1302 | if (flags & ATMEL_SSC_TD) | |
1303 | select_peripheral(PA(4), PERIPH_B, 0); /* TD */ | |
1304 | if (flags & ATMEL_SSC_RD) | |
1305 | select_peripheral(PA(5), PERIPH_B, 0); /* RD */ | |
1306 | break; | |
1307 | case 2: | |
1308 | pdev = &ssc2_device; | |
1309 | if (flags & ATMEL_SSC_TD) | |
1310 | select_peripheral(PB(13), PERIPH_A, 0); /* TD */ | |
1311 | if (flags & ATMEL_SSC_RD) | |
1312 | select_peripheral(PB(14), PERIPH_A, 0); /* RD */ | |
1313 | if (flags & ATMEL_SSC_TK) | |
1314 | select_peripheral(PB(15), PERIPH_A, 0); /* TK */ | |
1315 | if (flags & ATMEL_SSC_TF) | |
1316 | select_peripheral(PB(16), PERIPH_A, 0); /* TF */ | |
1317 | if (flags & ATMEL_SSC_RF) | |
1318 | select_peripheral(PB(17), PERIPH_A, 0); /* RF */ | |
1319 | if (flags & ATMEL_SSC_RK) | |
1320 | select_peripheral(PB(18), PERIPH_A, 0); /* RK */ | |
1321 | break; | |
1322 | default: | |
1323 | return NULL; | |
1324 | } | |
1325 | ||
1326 | platform_device_register(pdev); | |
1327 | return pdev; | |
1328 | } | |
1329 | ||
6fcf0615 HS |
1330 | /* -------------------------------------------------------------------- |
1331 | * USB Device Controller | |
1332 | * -------------------------------------------------------------------- */ | |
1333 | static struct resource usba0_resource[] __initdata = { | |
1334 | { | |
1335 | .start = 0xff300000, | |
1336 | .end = 0xff3fffff, | |
1337 | .flags = IORESOURCE_MEM, | |
1338 | }, { | |
1339 | .start = 0xfff03000, | |
1340 | .end = 0xfff033ff, | |
1341 | .flags = IORESOURCE_MEM, | |
1342 | }, | |
1343 | IRQ(31), | |
1344 | }; | |
1345 | static struct clk usba0_pclk = { | |
1346 | .name = "pclk", | |
1347 | .parent = &pbb_clk, | |
1348 | .mode = pbb_clk_mode, | |
1349 | .get_rate = pbb_clk_get_rate, | |
1350 | .index = 12, | |
1351 | }; | |
1352 | static struct clk usba0_hclk = { | |
1353 | .name = "hclk", | |
1354 | .parent = &hsb_clk, | |
1355 | .mode = hsb_clk_mode, | |
1356 | .get_rate = hsb_clk_get_rate, | |
1357 | .index = 6, | |
1358 | }; | |
1359 | ||
8d855317 SP |
1360 | #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ |
1361 | [idx] = { \ | |
1362 | .name = nam, \ | |
1363 | .index = idx, \ | |
1364 | .fifo_size = maxpkt, \ | |
1365 | .nr_banks = maxbk, \ | |
1366 | .can_dma = dma, \ | |
1367 | .can_isoc = isoc, \ | |
1368 | } | |
1369 | ||
1370 | static struct usba_ep_data at32_usba_ep[] __initdata = { | |
1371 | EP("ep0", 0, 64, 1, 0, 0), | |
1372 | EP("ep1", 1, 512, 2, 1, 1), | |
1373 | EP("ep2", 2, 512, 2, 1, 1), | |
1374 | EP("ep3-int", 3, 64, 3, 1, 0), | |
1375 | EP("ep4-int", 4, 64, 3, 1, 0), | |
1376 | EP("ep5", 5, 1024, 3, 1, 1), | |
1377 | EP("ep6", 6, 1024, 3, 1, 1), | |
1378 | }; | |
1379 | ||
1380 | #undef EP | |
1381 | ||
6fcf0615 HS |
1382 | struct platform_device *__init |
1383 | at32_add_device_usba(unsigned int id, struct usba_platform_data *data) | |
1384 | { | |
8d855317 SP |
1385 | /* |
1386 | * pdata doesn't have room for any endpoints, so we need to | |
1387 | * append room for the ones we need right after it. | |
1388 | */ | |
1389 | struct { | |
1390 | struct usba_platform_data pdata; | |
1391 | struct usba_ep_data ep[7]; | |
1392 | } usba_data; | |
6fcf0615 HS |
1393 | struct platform_device *pdev; |
1394 | ||
1395 | if (id != 0) | |
1396 | return NULL; | |
1397 | ||
1398 | pdev = platform_device_alloc("atmel_usba_udc", 0); | |
1399 | if (!pdev) | |
1400 | return NULL; | |
1401 | ||
1402 | if (platform_device_add_resources(pdev, usba0_resource, | |
1403 | ARRAY_SIZE(usba0_resource))) | |
1404 | goto out_free_pdev; | |
1405 | ||
8d855317 SP |
1406 | if (data) |
1407 | usba_data.pdata.vbus_pin = data->vbus_pin; | |
1408 | else | |
1409 | usba_data.pdata.vbus_pin = -EINVAL; | |
6fcf0615 | 1410 | |
8d855317 SP |
1411 | data = &usba_data.pdata; |
1412 | data->num_ep = ARRAY_SIZE(at32_usba_ep); | |
1413 | memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep)); | |
1414 | ||
1415 | if (platform_device_add_data(pdev, data, sizeof(usba_data))) | |
1416 | goto out_free_pdev; | |
1417 | ||
1418 | if (data->vbus_pin >= 0) | |
1419 | at32_select_gpio(data->vbus_pin, 0); | |
6fcf0615 HS |
1420 | |
1421 | usba0_pclk.dev = &pdev->dev; | |
1422 | usba0_hclk.dev = &pdev->dev; | |
1423 | ||
1424 | platform_device_add(pdev); | |
1425 | ||
1426 | return pdev; | |
1427 | ||
1428 | out_free_pdev: | |
1429 | platform_device_put(pdev); | |
1430 | return NULL; | |
1431 | } | |
1432 | ||
48021bd9 | 1433 | /* -------------------------------------------------------------------- |
eaf5f925 | 1434 | * IDE / CompactFlash |
48021bd9 | 1435 | * -------------------------------------------------------------------- */ |
438ff3f3 | 1436 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001) |
eaf5f925 | 1437 | static struct resource at32_smc_cs4_resource[] __initdata = { |
48021bd9 KNG |
1438 | { |
1439 | .start = 0x04000000, | |
1440 | .end = 0x07ffffff, | |
1441 | .flags = IORESOURCE_MEM, | |
1442 | }, | |
1443 | IRQ(~0UL), /* Magic IRQ will be overridden */ | |
1444 | }; | |
eaf5f925 HS |
1445 | static struct resource at32_smc_cs5_resource[] __initdata = { |
1446 | { | |
1447 | .start = 0x20000000, | |
1448 | .end = 0x23ffffff, | |
1449 | .flags = IORESOURCE_MEM, | |
1450 | }, | |
1451 | IRQ(~0UL), /* Magic IRQ will be overridden */ | |
1452 | }; | |
48021bd9 | 1453 | |
eaf5f925 HS |
1454 | static int __init at32_init_ide_or_cf(struct platform_device *pdev, |
1455 | unsigned int cs, unsigned int extint) | |
48021bd9 | 1456 | { |
eaf5f925 HS |
1457 | static unsigned int extint_pin_map[4] __initdata = { |
1458 | GPIO_PIN_PB(25), | |
1459 | GPIO_PIN_PB(26), | |
1460 | GPIO_PIN_PB(27), | |
1461 | GPIO_PIN_PB(28), | |
1462 | }; | |
1463 | static bool common_pins_initialized __initdata = false; | |
48021bd9 | 1464 | unsigned int extint_pin; |
eaf5f925 | 1465 | int ret; |
48021bd9 | 1466 | |
eaf5f925 HS |
1467 | if (extint >= ARRAY_SIZE(extint_pin_map)) |
1468 | return -EINVAL; | |
1469 | extint_pin = extint_pin_map[extint]; | |
1470 | ||
1471 | switch (cs) { | |
1472 | case 4: | |
1473 | ret = platform_device_add_resources(pdev, | |
1474 | at32_smc_cs4_resource, | |
1475 | ARRAY_SIZE(at32_smc_cs4_resource)); | |
1476 | if (ret) | |
1477 | return ret; | |
1478 | ||
1479 | select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */ | |
1480 | set_ebi_sfr_bits(HMATRIX_BIT(CS4A)); | |
48021bd9 | 1481 | break; |
eaf5f925 HS |
1482 | case 5: |
1483 | ret = platform_device_add_resources(pdev, | |
1484 | at32_smc_cs5_resource, | |
1485 | ARRAY_SIZE(at32_smc_cs5_resource)); | |
1486 | if (ret) | |
1487 | return ret; | |
1488 | ||
1489 | select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */ | |
1490 | set_ebi_sfr_bits(HMATRIX_BIT(CS5A)); | |
48021bd9 KNG |
1491 | break; |
1492 | default: | |
eaf5f925 | 1493 | return -EINVAL; |
48021bd9 KNG |
1494 | } |
1495 | ||
eaf5f925 | 1496 | if (!common_pins_initialized) { |
48021bd9 KNG |
1497 | select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */ |
1498 | select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */ | |
48021bd9 KNG |
1499 | select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */ |
1500 | select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */ | |
eaf5f925 | 1501 | common_pins_initialized = true; |
48021bd9 KNG |
1502 | } |
1503 | ||
1504 | at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH); | |
1505 | ||
1506 | pdev->resource[1].start = EIM_IRQ_BASE + extint; | |
1507 | pdev->resource[1].end = pdev->resource[1].start; | |
1508 | ||
eaf5f925 HS |
1509 | return 0; |
1510 | } | |
48021bd9 | 1511 | |
eaf5f925 HS |
1512 | struct platform_device *__init |
1513 | at32_add_device_ide(unsigned int id, unsigned int extint, | |
1514 | struct ide_platform_data *data) | |
1515 | { | |
1516 | struct platform_device *pdev; | |
1517 | ||
1518 | pdev = platform_device_alloc("at32_ide", id); | |
1519 | if (!pdev) | |
1520 | goto fail; | |
1521 | ||
1522 | if (platform_device_add_data(pdev, data, | |
1523 | sizeof(struct ide_platform_data))) | |
1524 | goto fail; | |
1525 | ||
1526 | if (at32_init_ide_or_cf(pdev, data->cs, extint)) | |
1527 | goto fail; | |
1528 | ||
1529 | platform_device_add(pdev); | |
1530 | return pdev; | |
1531 | ||
1532 | fail: | |
1533 | platform_device_put(pdev); | |
1534 | return NULL; | |
1535 | } | |
1536 | ||
1537 | struct platform_device *__init | |
1538 | at32_add_device_cf(unsigned int id, unsigned int extint, | |
1539 | struct cf_platform_data *data) | |
1540 | { | |
1541 | struct platform_device *pdev; | |
1542 | ||
1543 | pdev = platform_device_alloc("at32_cf", id); | |
1544 | if (!pdev) | |
1545 | goto fail; | |
48021bd9 | 1546 | |
eaf5f925 HS |
1547 | if (platform_device_add_data(pdev, data, |
1548 | sizeof(struct cf_platform_data))) | |
1549 | goto fail; | |
1550 | ||
1551 | if (at32_init_ide_or_cf(pdev, data->cs, extint)) | |
1552 | goto fail; | |
1553 | ||
1554 | if (data->detect_pin != GPIO_PIN_NONE) | |
1555 | at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH); | |
1556 | if (data->reset_pin != GPIO_PIN_NONE) | |
1557 | at32_select_gpio(data->reset_pin, 0); | |
1558 | if (data->vcc_pin != GPIO_PIN_NONE) | |
1559 | at32_select_gpio(data->vcc_pin, 0); | |
1560 | /* READY is used as extint, so we can't select it as gpio */ | |
1561 | ||
1562 | platform_device_add(pdev); | |
48021bd9 | 1563 | return pdev; |
eaf5f925 HS |
1564 | |
1565 | fail: | |
1566 | platform_device_put(pdev); | |
1567 | return NULL; | |
48021bd9 | 1568 | } |
438ff3f3 | 1569 | #endif |
48021bd9 | 1570 | |
2042c1c4 HS |
1571 | /* -------------------------------------------------------------------- |
1572 | * AC97C | |
1573 | * -------------------------------------------------------------------- */ | |
1574 | static struct resource atmel_ac97c0_resource[] __initdata = { | |
1575 | PBMEM(0xfff02800), | |
1576 | IRQ(29), | |
1577 | }; | |
1578 | static struct clk atmel_ac97c0_pclk = { | |
1579 | .name = "pclk", | |
1580 | .parent = &pbb_clk, | |
1581 | .mode = pbb_clk_mode, | |
1582 | .get_rate = pbb_clk_get_rate, | |
1583 | .index = 10, | |
1584 | }; | |
1585 | ||
1586 | struct platform_device *__init at32_add_device_ac97c(unsigned int id) | |
1587 | { | |
1588 | struct platform_device *pdev; | |
1589 | ||
1590 | if (id != 0) | |
1591 | return NULL; | |
1592 | ||
1593 | pdev = platform_device_alloc("atmel_ac97c", id); | |
1594 | if (!pdev) | |
1595 | return NULL; | |
1596 | ||
1597 | if (platform_device_add_resources(pdev, atmel_ac97c0_resource, | |
1598 | ARRAY_SIZE(atmel_ac97c0_resource))) | |
1599 | goto err_add_resources; | |
1600 | ||
1601 | select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */ | |
1602 | select_peripheral(PB(21), PERIPH_B, 0); /* SDO */ | |
1603 | select_peripheral(PB(22), PERIPH_B, 0); /* SDI */ | |
1604 | select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */ | |
1605 | ||
1606 | atmel_ac97c0_pclk.dev = &pdev->dev; | |
1607 | ||
1608 | platform_device_add(pdev); | |
1609 | return pdev; | |
1610 | ||
1611 | err_add_resources: | |
1612 | platform_device_put(pdev); | |
1613 | return NULL; | |
1614 | } | |
1615 | ||
1616 | /* -------------------------------------------------------------------- | |
1617 | * ABDAC | |
1618 | * -------------------------------------------------------------------- */ | |
1619 | static struct resource abdac0_resource[] __initdata = { | |
1620 | PBMEM(0xfff02000), | |
1621 | IRQ(27), | |
1622 | }; | |
1623 | static struct clk abdac0_pclk = { | |
1624 | .name = "pclk", | |
1625 | .parent = &pbb_clk, | |
1626 | .mode = pbb_clk_mode, | |
1627 | .get_rate = pbb_clk_get_rate, | |
1628 | .index = 8, | |
1629 | }; | |
1630 | static struct clk abdac0_sample_clk = { | |
1631 | .name = "sample_clk", | |
1632 | .mode = genclk_mode, | |
1633 | .get_rate = genclk_get_rate, | |
1634 | .set_rate = genclk_set_rate, | |
1635 | .set_parent = genclk_set_parent, | |
1636 | .index = 6, | |
1637 | }; | |
1638 | ||
1639 | struct platform_device *__init at32_add_device_abdac(unsigned int id) | |
1640 | { | |
1641 | struct platform_device *pdev; | |
1642 | ||
1643 | if (id != 0) | |
1644 | return NULL; | |
1645 | ||
1646 | pdev = platform_device_alloc("abdac", id); | |
1647 | if (!pdev) | |
1648 | return NULL; | |
1649 | ||
1650 | if (platform_device_add_resources(pdev, abdac0_resource, | |
1651 | ARRAY_SIZE(abdac0_resource))) | |
1652 | goto err_add_resources; | |
1653 | ||
1654 | select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */ | |
1655 | select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */ | |
1656 | select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */ | |
1657 | select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */ | |
1658 | ||
1659 | abdac0_pclk.dev = &pdev->dev; | |
1660 | abdac0_sample_clk.dev = &pdev->dev; | |
1661 | ||
1662 | platform_device_add(pdev); | |
1663 | return pdev; | |
1664 | ||
1665 | err_add_resources: | |
1666 | platform_device_put(pdev); | |
1667 | return NULL; | |
1668 | } | |
1669 | ||
7a5fe238 HS |
1670 | /* -------------------------------------------------------------------- |
1671 | * GCLK | |
1672 | * -------------------------------------------------------------------- */ | |
1673 | static struct clk gclk0 = { | |
1674 | .name = "gclk0", | |
1675 | .mode = genclk_mode, | |
1676 | .get_rate = genclk_get_rate, | |
1677 | .set_rate = genclk_set_rate, | |
1678 | .set_parent = genclk_set_parent, | |
1679 | .index = 0, | |
1680 | }; | |
1681 | static struct clk gclk1 = { | |
1682 | .name = "gclk1", | |
1683 | .mode = genclk_mode, | |
1684 | .get_rate = genclk_get_rate, | |
1685 | .set_rate = genclk_set_rate, | |
1686 | .set_parent = genclk_set_parent, | |
1687 | .index = 1, | |
1688 | }; | |
1689 | static struct clk gclk2 = { | |
1690 | .name = "gclk2", | |
1691 | .mode = genclk_mode, | |
1692 | .get_rate = genclk_get_rate, | |
1693 | .set_rate = genclk_set_rate, | |
1694 | .set_parent = genclk_set_parent, | |
1695 | .index = 2, | |
1696 | }; | |
1697 | static struct clk gclk3 = { | |
1698 | .name = "gclk3", | |
1699 | .mode = genclk_mode, | |
1700 | .get_rate = genclk_get_rate, | |
1701 | .set_rate = genclk_set_rate, | |
1702 | .set_parent = genclk_set_parent, | |
1703 | .index = 3, | |
1704 | }; | |
1705 | static struct clk gclk4 = { | |
1706 | .name = "gclk4", | |
1707 | .mode = genclk_mode, | |
1708 | .get_rate = genclk_get_rate, | |
1709 | .set_rate = genclk_set_rate, | |
1710 | .set_parent = genclk_set_parent, | |
1711 | .index = 4, | |
1712 | }; | |
1713 | ||
5f97f7f9 HS |
1714 | struct clk *at32_clock_list[] = { |
1715 | &osc32k, | |
1716 | &osc0, | |
1717 | &osc1, | |
1718 | &pll0, | |
1719 | &pll1, | |
1720 | &cpu_clk, | |
1721 | &hsb_clk, | |
1722 | &pba_clk, | |
1723 | &pbb_clk, | |
7a5b8059 | 1724 | &at32_pm_pclk, |
5f97f7f9 | 1725 | &at32_intc0_pclk, |
9c8f8e75 | 1726 | &hmatrix_clk, |
5f97f7f9 HS |
1727 | &ebi_clk, |
1728 | &hramc_clk, | |
bc157b75 HS |
1729 | &smc0_pclk, |
1730 | &smc0_mck, | |
5f97f7f9 HS |
1731 | &pdc_hclk, |
1732 | &pdc_pclk, | |
2042c1c4 | 1733 | &dmaca0_hclk, |
5f97f7f9 HS |
1734 | &pico_clk, |
1735 | &pio0_mck, | |
1736 | &pio1_mck, | |
1737 | &pio2_mck, | |
1738 | &pio3_mck, | |
7f9f4678 | 1739 | &pio4_mck, |
7760989e | 1740 | &at32_systc0_pclk, |
1e8ea802 HS |
1741 | &atmel_usart0_usart, |
1742 | &atmel_usart1_usart, | |
1743 | &atmel_usart2_usart, | |
1744 | &atmel_usart3_usart, | |
9a1e8eb1 | 1745 | &atmel_pwm0_mck, |
438ff3f3 | 1746 | #if defined(CONFIG_CPU_AT32AP7000) |
5f97f7f9 HS |
1747 | &macb0_hclk, |
1748 | &macb0_pclk, | |
cfcb3a89 HS |
1749 | &macb1_hclk, |
1750 | &macb1_pclk, | |
438ff3f3 | 1751 | #endif |
3d60ee1b HS |
1752 | &atmel_spi0_spi_clk, |
1753 | &atmel_spi1_spi_clk, | |
2042c1c4 HS |
1754 | &atmel_twi0_pclk, |
1755 | &atmel_mci0_pclk, | |
438ff3f3 | 1756 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af HS |
1757 | &atmel_lcdfb0_hck1, |
1758 | &atmel_lcdfb0_pixclk, | |
438ff3f3 | 1759 | #endif |
9cf6cf58 HCE |
1760 | &ssc0_pclk, |
1761 | &ssc1_pclk, | |
1762 | &ssc2_pclk, | |
6fcf0615 HS |
1763 | &usba0_hclk, |
1764 | &usba0_pclk, | |
2042c1c4 HS |
1765 | &atmel_ac97c0_pclk, |
1766 | &abdac0_pclk, | |
1767 | &abdac0_sample_clk, | |
7a5fe238 HS |
1768 | &gclk0, |
1769 | &gclk1, | |
1770 | &gclk2, | |
1771 | &gclk3, | |
1772 | &gclk4, | |
5f97f7f9 HS |
1773 | }; |
1774 | unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list); | |
1775 | ||
1776 | void __init at32_portmux_init(void) | |
1777 | { | |
1778 | at32_init_pio(&pio0_device); | |
1779 | at32_init_pio(&pio1_device); | |
1780 | at32_init_pio(&pio2_device); | |
1781 | at32_init_pio(&pio3_device); | |
7f9f4678 | 1782 | at32_init_pio(&pio4_device); |
5f97f7f9 HS |
1783 | } |
1784 | ||
1785 | void __init at32_clock_init(void) | |
1786 | { | |
5f97f7f9 HS |
1787 | u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0; |
1788 | int i; | |
1789 | ||
9e58e185 | 1790 | if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) { |
5f97f7f9 | 1791 | main_clock = &pll0; |
9e58e185 HCE |
1792 | cpu_clk.parent = &pll0; |
1793 | } else { | |
5f97f7f9 | 1794 | main_clock = &osc0; |
9e58e185 HCE |
1795 | cpu_clk.parent = &osc0; |
1796 | } | |
5f97f7f9 | 1797 | |
7a5b8059 | 1798 | if (pm_readl(PLL0) & PM_BIT(PLLOSC)) |
5f97f7f9 | 1799 | pll0.parent = &osc1; |
7a5b8059 | 1800 | if (pm_readl(PLL1) & PM_BIT(PLLOSC)) |
5f97f7f9 HS |
1801 | pll1.parent = &osc1; |
1802 | ||
7a5fe238 HS |
1803 | genclk_init_parent(&gclk0); |
1804 | genclk_init_parent(&gclk1); | |
1805 | genclk_init_parent(&gclk2); | |
1806 | genclk_init_parent(&gclk3); | |
1807 | genclk_init_parent(&gclk4); | |
438ff3f3 | 1808 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af | 1809 | genclk_init_parent(&atmel_lcdfb0_pixclk); |
438ff3f3 | 1810 | #endif |
2042c1c4 | 1811 | genclk_init_parent(&abdac0_sample_clk); |
7a5fe238 | 1812 | |
5f97f7f9 HS |
1813 | /* |
1814 | * Turn on all clocks that have at least one user already, and | |
1815 | * turn off everything else. We only do this for module | |
1816 | * clocks, and even though it isn't particularly pretty to | |
1817 | * check the address of the mode function, it should do the | |
1818 | * trick... | |
1819 | */ | |
1820 | for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) { | |
1821 | struct clk *clk = at32_clock_list[i]; | |
1822 | ||
188ff65d HS |
1823 | if (clk->users == 0) |
1824 | continue; | |
1825 | ||
5f97f7f9 HS |
1826 | if (clk->mode == &cpu_clk_mode) |
1827 | cpu_mask |= 1 << clk->index; | |
1828 | else if (clk->mode == &hsb_clk_mode) | |
1829 | hsb_mask |= 1 << clk->index; | |
1830 | else if (clk->mode == &pba_clk_mode) | |
1831 | pba_mask |= 1 << clk->index; | |
1832 | else if (clk->mode == &pbb_clk_mode) | |
1833 | pbb_mask |= 1 << clk->index; | |
1834 | } | |
1835 | ||
7a5b8059 HS |
1836 | pm_writel(CPU_MASK, cpu_mask); |
1837 | pm_writel(HSB_MASK, hsb_mask); | |
1838 | pm_writel(PBA_MASK, pba_mask); | |
1839 | pm_writel(PBB_MASK, pbb_mask); | |
5f97f7f9 | 1840 | } |