Commit | Line | Data |
---|---|---|
5f97f7f9 HS |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | #include <linux/clk.h> | |
35bf50cc | 9 | #include <linux/delay.h> |
3bfb1d20 | 10 | #include <linux/dw_dmac.h> |
d0a2b7af | 11 | #include <linux/fb.h> |
5f97f7f9 HS |
12 | #include <linux/init.h> |
13 | #include <linux/platform_device.h> | |
6b84bbfc | 14 | #include <linux/dma-mapping.h> |
3c26e170 | 15 | #include <linux/gpio.h> |
41d8ca45 | 16 | #include <linux/spi/spi.h> |
8d855317 | 17 | #include <linux/usb/atmel_usba_udc.h> |
c42aa775 | 18 | #include <linux/atmel-mci.h> |
5f97f7f9 HS |
19 | |
20 | #include <asm/io.h> | |
e7ba176b | 21 | #include <asm/irq.h> |
5f97f7f9 | 22 | |
3663b736 HS |
23 | #include <mach/at32ap700x.h> |
24 | #include <mach/board.h> | |
b47eb409 | 25 | #include <mach/hmatrix.h> |
3663b736 HS |
26 | #include <mach/portmux.h> |
27 | #include <mach/sram.h> | |
5f97f7f9 | 28 | |
6b0c9351 | 29 | #include <sound/atmel-abdac.h> |
2f47c8c5 | 30 | #include <sound/atmel-ac97c.h> |
6b0c9351 | 31 | |
d0a2b7af HS |
32 | #include <video/atmel_lcdc.h> |
33 | ||
5f97f7f9 HS |
34 | #include "clock.h" |
35 | #include "pio.h" | |
7a5b8059 HS |
36 | #include "pm.h" |
37 | ||
5f97f7f9 HS |
38 | |
39 | #define PBMEM(base) \ | |
40 | { \ | |
41 | .start = base, \ | |
42 | .end = base + 0x3ff, \ | |
43 | .flags = IORESOURCE_MEM, \ | |
44 | } | |
45 | #define IRQ(num) \ | |
46 | { \ | |
47 | .start = num, \ | |
48 | .end = num, \ | |
49 | .flags = IORESOURCE_IRQ, \ | |
50 | } | |
51 | #define NAMED_IRQ(num, _name) \ | |
52 | { \ | |
53 | .start = num, \ | |
54 | .end = num, \ | |
55 | .name = _name, \ | |
56 | .flags = IORESOURCE_IRQ, \ | |
57 | } | |
58 | ||
6b84bbfc DB |
59 | /* REVISIT these assume *every* device supports DMA, but several |
60 | * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more. | |
61 | */ | |
5f97f7f9 | 62 | #define DEFINE_DEV(_name, _id) \ |
6b84bbfc | 63 | static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \ |
5f97f7f9 HS |
64 | static struct platform_device _name##_id##_device = { \ |
65 | .name = #_name, \ | |
66 | .id = _id, \ | |
6b84bbfc DB |
67 | .dev = { \ |
68 | .dma_mask = &_name##_id##_dma_mask, \ | |
69 | .coherent_dma_mask = DMA_32BIT_MASK, \ | |
70 | }, \ | |
5f97f7f9 HS |
71 | .resource = _name##_id##_resource, \ |
72 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
73 | } | |
74 | #define DEFINE_DEV_DATA(_name, _id) \ | |
6b84bbfc | 75 | static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \ |
5f97f7f9 HS |
76 | static struct platform_device _name##_id##_device = { \ |
77 | .name = #_name, \ | |
78 | .id = _id, \ | |
79 | .dev = { \ | |
6b84bbfc | 80 | .dma_mask = &_name##_id##_dma_mask, \ |
5f97f7f9 | 81 | .platform_data = &_name##_id##_data, \ |
6b84bbfc | 82 | .coherent_dma_mask = DMA_32BIT_MASK, \ |
5f97f7f9 HS |
83 | }, \ |
84 | .resource = _name##_id##_resource, \ | |
85 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
86 | } | |
87 | ||
caf18f19 JM |
88 | #define select_peripheral(port, pin_mask, periph, flags) \ |
89 | at32_select_periph(GPIO_##port##_BASE, pin_mask, \ | |
90 | GPIO_##periph, flags) | |
c3e2a79c | 91 | |
5f97f7f9 HS |
92 | #define DEV_CLK(_name, devname, bus, _index) \ |
93 | static struct clk devname##_##_name = { \ | |
94 | .name = #_name, \ | |
95 | .dev = &devname##_device.dev, \ | |
96 | .parent = &bus##_clk, \ | |
97 | .mode = bus##_clk_mode, \ | |
98 | .get_rate = bus##_clk_get_rate, \ | |
99 | .index = _index, \ | |
100 | } | |
101 | ||
7a5b8059 HS |
102 | static DEFINE_SPINLOCK(pm_lock); |
103 | ||
35bf50cc HCE |
104 | static struct clk osc0; |
105 | static struct clk osc1; | |
106 | ||
5f97f7f9 HS |
107 | static unsigned long osc_get_rate(struct clk *clk) |
108 | { | |
60ed7951 | 109 | return at32_board_osc_rates[clk->index]; |
5f97f7f9 HS |
110 | } |
111 | ||
112 | static unsigned long pll_get_rate(struct clk *clk, unsigned long control) | |
113 | { | |
114 | unsigned long div, mul, rate; | |
115 | ||
7a5b8059 HS |
116 | div = PM_BFEXT(PLLDIV, control) + 1; |
117 | mul = PM_BFEXT(PLLMUL, control) + 1; | |
5f97f7f9 HS |
118 | |
119 | rate = clk->parent->get_rate(clk->parent); | |
120 | rate = (rate + div / 2) / div; | |
121 | rate *= mul; | |
122 | ||
123 | return rate; | |
124 | } | |
125 | ||
35bf50cc HCE |
126 | static long pll_set_rate(struct clk *clk, unsigned long rate, |
127 | u32 *pll_ctrl) | |
128 | { | |
129 | unsigned long mul; | |
130 | unsigned long mul_best_fit = 0; | |
131 | unsigned long div; | |
132 | unsigned long div_min; | |
133 | unsigned long div_max; | |
134 | unsigned long div_best_fit = 0; | |
135 | unsigned long base; | |
136 | unsigned long pll_in; | |
137 | unsigned long actual = 0; | |
138 | unsigned long rate_error; | |
139 | unsigned long rate_error_prev = ~0UL; | |
140 | u32 ctrl; | |
141 | ||
142 | /* Rate must be between 80 MHz and 200 Mhz. */ | |
143 | if (rate < 80000000UL || rate > 200000000UL) | |
144 | return -EINVAL; | |
145 | ||
146 | ctrl = PM_BF(PLLOPT, 4); | |
147 | base = clk->parent->get_rate(clk->parent); | |
148 | ||
149 | /* PLL input frequency must be between 6 MHz and 32 MHz. */ | |
150 | div_min = DIV_ROUND_UP(base, 32000000UL); | |
151 | div_max = base / 6000000UL; | |
152 | ||
153 | if (div_max < div_min) | |
154 | return -EINVAL; | |
155 | ||
156 | for (div = div_min; div <= div_max; div++) { | |
157 | pll_in = (base + div / 2) / div; | |
158 | mul = (rate + pll_in / 2) / pll_in; | |
159 | ||
160 | if (mul == 0) | |
161 | continue; | |
162 | ||
163 | actual = pll_in * mul; | |
164 | rate_error = abs(actual - rate); | |
165 | ||
166 | if (rate_error < rate_error_prev) { | |
167 | mul_best_fit = mul; | |
168 | div_best_fit = div; | |
169 | rate_error_prev = rate_error; | |
170 | } | |
171 | ||
172 | if (rate_error == 0) | |
173 | break; | |
174 | } | |
175 | ||
176 | if (div_best_fit == 0) | |
177 | return -EINVAL; | |
178 | ||
179 | ctrl |= PM_BF(PLLMUL, mul_best_fit - 1); | |
180 | ctrl |= PM_BF(PLLDIV, div_best_fit - 1); | |
181 | ctrl |= PM_BF(PLLCOUNT, 16); | |
182 | ||
183 | if (clk->parent == &osc1) | |
184 | ctrl |= PM_BIT(PLLOSC); | |
185 | ||
186 | *pll_ctrl = ctrl; | |
187 | ||
188 | return actual; | |
189 | } | |
190 | ||
5f97f7f9 HS |
191 | static unsigned long pll0_get_rate(struct clk *clk) |
192 | { | |
193 | u32 control; | |
194 | ||
7a5b8059 | 195 | control = pm_readl(PLL0); |
5f97f7f9 HS |
196 | |
197 | return pll_get_rate(clk, control); | |
198 | } | |
199 | ||
35bf50cc HCE |
200 | static void pll1_mode(struct clk *clk, int enabled) |
201 | { | |
202 | unsigned long timeout; | |
203 | u32 status; | |
204 | u32 ctrl; | |
205 | ||
206 | ctrl = pm_readl(PLL1); | |
207 | ||
208 | if (enabled) { | |
209 | if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) { | |
210 | pr_debug("clk %s: failed to enable, rate not set\n", | |
211 | clk->name); | |
212 | return; | |
213 | } | |
214 | ||
215 | ctrl |= PM_BIT(PLLEN); | |
216 | pm_writel(PLL1, ctrl); | |
217 | ||
218 | /* Wait for PLL lock. */ | |
219 | for (timeout = 10000; timeout; timeout--) { | |
220 | status = pm_readl(ISR); | |
221 | if (status & PM_BIT(LOCK1)) | |
222 | break; | |
223 | udelay(10); | |
224 | } | |
225 | ||
226 | if (!(status & PM_BIT(LOCK1))) | |
227 | printk(KERN_ERR "clk %s: timeout waiting for lock\n", | |
228 | clk->name); | |
229 | } else { | |
230 | ctrl &= ~PM_BIT(PLLEN); | |
231 | pm_writel(PLL1, ctrl); | |
232 | } | |
233 | } | |
234 | ||
5f97f7f9 HS |
235 | static unsigned long pll1_get_rate(struct clk *clk) |
236 | { | |
237 | u32 control; | |
238 | ||
7a5b8059 | 239 | control = pm_readl(PLL1); |
5f97f7f9 HS |
240 | |
241 | return pll_get_rate(clk, control); | |
242 | } | |
243 | ||
35bf50cc HCE |
244 | static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply) |
245 | { | |
246 | u32 ctrl = 0; | |
247 | unsigned long actual_rate; | |
248 | ||
249 | actual_rate = pll_set_rate(clk, rate, &ctrl); | |
250 | ||
251 | if (apply) { | |
252 | if (actual_rate != rate) | |
253 | return -EINVAL; | |
254 | if (clk->users > 0) | |
255 | return -EBUSY; | |
256 | pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n", | |
257 | clk->name, rate, actual_rate); | |
258 | pm_writel(PLL1, ctrl); | |
259 | } | |
260 | ||
261 | return actual_rate; | |
262 | } | |
263 | ||
264 | static int pll1_set_parent(struct clk *clk, struct clk *parent) | |
265 | { | |
266 | u32 ctrl; | |
267 | ||
268 | if (clk->users > 0) | |
269 | return -EBUSY; | |
270 | ||
271 | ctrl = pm_readl(PLL1); | |
272 | WARN_ON(ctrl & PM_BIT(PLLEN)); | |
273 | ||
274 | if (parent == &osc0) | |
275 | ctrl &= ~PM_BIT(PLLOSC); | |
276 | else if (parent == &osc1) | |
277 | ctrl |= PM_BIT(PLLOSC); | |
278 | else | |
279 | return -EINVAL; | |
280 | ||
281 | pm_writel(PLL1, ctrl); | |
282 | clk->parent = parent; | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
5f97f7f9 HS |
287 | /* |
288 | * The AT32AP7000 has five primary clock sources: One 32kHz | |
289 | * oscillator, two crystal oscillators and two PLLs. | |
290 | */ | |
291 | static struct clk osc32k = { | |
292 | .name = "osc32k", | |
293 | .get_rate = osc_get_rate, | |
294 | .users = 1, | |
295 | .index = 0, | |
296 | }; | |
297 | static struct clk osc0 = { | |
298 | .name = "osc0", | |
299 | .get_rate = osc_get_rate, | |
300 | .users = 1, | |
301 | .index = 1, | |
302 | }; | |
303 | static struct clk osc1 = { | |
304 | .name = "osc1", | |
305 | .get_rate = osc_get_rate, | |
306 | .index = 2, | |
307 | }; | |
308 | static struct clk pll0 = { | |
309 | .name = "pll0", | |
310 | .get_rate = pll0_get_rate, | |
311 | .parent = &osc0, | |
312 | }; | |
313 | static struct clk pll1 = { | |
314 | .name = "pll1", | |
35bf50cc | 315 | .mode = pll1_mode, |
5f97f7f9 | 316 | .get_rate = pll1_get_rate, |
35bf50cc HCE |
317 | .set_rate = pll1_set_rate, |
318 | .set_parent = pll1_set_parent, | |
5f97f7f9 HS |
319 | .parent = &osc0, |
320 | }; | |
321 | ||
322 | /* | |
323 | * The main clock can be either osc0 or pll0. The boot loader may | |
324 | * have chosen one for us, so we don't really know which one until we | |
325 | * have a look at the SM. | |
326 | */ | |
327 | static struct clk *main_clock; | |
328 | ||
329 | /* | |
330 | * Synchronous clocks are generated from the main clock. The clocks | |
331 | * must satisfy the constraint | |
332 | * fCPU >= fHSB >= fPB | |
333 | * i.e. each clock must not be faster than its parent. | |
334 | */ | |
335 | static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift) | |
336 | { | |
337 | return main_clock->get_rate(main_clock) >> shift; | |
338 | }; | |
339 | ||
340 | static void cpu_clk_mode(struct clk *clk, int enabled) | |
341 | { | |
5f97f7f9 HS |
342 | unsigned long flags; |
343 | u32 mask; | |
344 | ||
7a5b8059 HS |
345 | spin_lock_irqsave(&pm_lock, flags); |
346 | mask = pm_readl(CPU_MASK); | |
5f97f7f9 HS |
347 | if (enabled) |
348 | mask |= 1 << clk->index; | |
349 | else | |
350 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
351 | pm_writel(CPU_MASK, mask); |
352 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
353 | } |
354 | ||
355 | static unsigned long cpu_clk_get_rate(struct clk *clk) | |
356 | { | |
357 | unsigned long cksel, shift = 0; | |
358 | ||
7a5b8059 HS |
359 | cksel = pm_readl(CKSEL); |
360 | if (cksel & PM_BIT(CPUDIV)) | |
361 | shift = PM_BFEXT(CPUSEL, cksel) + 1; | |
5f97f7f9 HS |
362 | |
363 | return bus_clk_get_rate(clk, shift); | |
364 | } | |
365 | ||
9e58e185 HCE |
366 | static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply) |
367 | { | |
368 | u32 control; | |
369 | unsigned long parent_rate, child_div, actual_rate, div; | |
370 | ||
371 | parent_rate = clk->parent->get_rate(clk->parent); | |
372 | control = pm_readl(CKSEL); | |
373 | ||
374 | if (control & PM_BIT(HSBDIV)) | |
375 | child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1); | |
376 | else | |
377 | child_div = 1; | |
378 | ||
379 | if (rate > 3 * (parent_rate / 4) || child_div == 1) { | |
380 | actual_rate = parent_rate; | |
381 | control &= ~PM_BIT(CPUDIV); | |
382 | } else { | |
383 | unsigned int cpusel; | |
384 | div = (parent_rate + rate / 2) / rate; | |
385 | if (div > child_div) | |
386 | div = child_div; | |
387 | cpusel = (div > 1) ? (fls(div) - 2) : 0; | |
388 | control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control); | |
389 | actual_rate = parent_rate / (1 << (cpusel + 1)); | |
390 | } | |
391 | ||
392 | pr_debug("clk %s: new rate %lu (actual rate %lu)\n", | |
393 | clk->name, rate, actual_rate); | |
394 | ||
395 | if (apply) | |
396 | pm_writel(CKSEL, control); | |
397 | ||
398 | return actual_rate; | |
399 | } | |
400 | ||
5f97f7f9 HS |
401 | static void hsb_clk_mode(struct clk *clk, int enabled) |
402 | { | |
5f97f7f9 HS |
403 | unsigned long flags; |
404 | u32 mask; | |
405 | ||
7a5b8059 HS |
406 | spin_lock_irqsave(&pm_lock, flags); |
407 | mask = pm_readl(HSB_MASK); | |
5f97f7f9 HS |
408 | if (enabled) |
409 | mask |= 1 << clk->index; | |
410 | else | |
411 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
412 | pm_writel(HSB_MASK, mask); |
413 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
414 | } |
415 | ||
416 | static unsigned long hsb_clk_get_rate(struct clk *clk) | |
417 | { | |
418 | unsigned long cksel, shift = 0; | |
419 | ||
7a5b8059 HS |
420 | cksel = pm_readl(CKSEL); |
421 | if (cksel & PM_BIT(HSBDIV)) | |
422 | shift = PM_BFEXT(HSBSEL, cksel) + 1; | |
5f97f7f9 HS |
423 | |
424 | return bus_clk_get_rate(clk, shift); | |
425 | } | |
426 | ||
dd5e1339 | 427 | void pba_clk_mode(struct clk *clk, int enabled) |
5f97f7f9 | 428 | { |
5f97f7f9 HS |
429 | unsigned long flags; |
430 | u32 mask; | |
431 | ||
7a5b8059 HS |
432 | spin_lock_irqsave(&pm_lock, flags); |
433 | mask = pm_readl(PBA_MASK); | |
5f97f7f9 HS |
434 | if (enabled) |
435 | mask |= 1 << clk->index; | |
436 | else | |
437 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
438 | pm_writel(PBA_MASK, mask); |
439 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
440 | } |
441 | ||
dd5e1339 | 442 | unsigned long pba_clk_get_rate(struct clk *clk) |
5f97f7f9 HS |
443 | { |
444 | unsigned long cksel, shift = 0; | |
445 | ||
7a5b8059 HS |
446 | cksel = pm_readl(CKSEL); |
447 | if (cksel & PM_BIT(PBADIV)) | |
448 | shift = PM_BFEXT(PBASEL, cksel) + 1; | |
5f97f7f9 HS |
449 | |
450 | return bus_clk_get_rate(clk, shift); | |
451 | } | |
452 | ||
453 | static void pbb_clk_mode(struct clk *clk, int enabled) | |
454 | { | |
5f97f7f9 HS |
455 | unsigned long flags; |
456 | u32 mask; | |
457 | ||
7a5b8059 HS |
458 | spin_lock_irqsave(&pm_lock, flags); |
459 | mask = pm_readl(PBB_MASK); | |
5f97f7f9 HS |
460 | if (enabled) |
461 | mask |= 1 << clk->index; | |
462 | else | |
463 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
464 | pm_writel(PBB_MASK, mask); |
465 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
466 | } |
467 | ||
468 | static unsigned long pbb_clk_get_rate(struct clk *clk) | |
469 | { | |
470 | unsigned long cksel, shift = 0; | |
471 | ||
7a5b8059 HS |
472 | cksel = pm_readl(CKSEL); |
473 | if (cksel & PM_BIT(PBBDIV)) | |
474 | shift = PM_BFEXT(PBBSEL, cksel) + 1; | |
5f97f7f9 HS |
475 | |
476 | return bus_clk_get_rate(clk, shift); | |
477 | } | |
478 | ||
479 | static struct clk cpu_clk = { | |
480 | .name = "cpu", | |
481 | .get_rate = cpu_clk_get_rate, | |
9e58e185 | 482 | .set_rate = cpu_clk_set_rate, |
5f97f7f9 HS |
483 | .users = 1, |
484 | }; | |
485 | static struct clk hsb_clk = { | |
486 | .name = "hsb", | |
487 | .parent = &cpu_clk, | |
488 | .get_rate = hsb_clk_get_rate, | |
489 | }; | |
490 | static struct clk pba_clk = { | |
491 | .name = "pba", | |
492 | .parent = &hsb_clk, | |
493 | .mode = hsb_clk_mode, | |
494 | .get_rate = pba_clk_get_rate, | |
495 | .index = 1, | |
496 | }; | |
497 | static struct clk pbb_clk = { | |
498 | .name = "pbb", | |
499 | .parent = &hsb_clk, | |
500 | .mode = hsb_clk_mode, | |
501 | .get_rate = pbb_clk_get_rate, | |
502 | .users = 1, | |
503 | .index = 2, | |
504 | }; | |
505 | ||
506 | /* -------------------------------------------------------------------- | |
507 | * Generic Clock operations | |
508 | * -------------------------------------------------------------------- */ | |
509 | ||
510 | static void genclk_mode(struct clk *clk, int enabled) | |
511 | { | |
512 | u32 control; | |
513 | ||
7a5b8059 | 514 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 | 515 | if (enabled) |
7a5b8059 | 516 | control |= PM_BIT(CEN); |
5f97f7f9 | 517 | else |
7a5b8059 HS |
518 | control &= ~PM_BIT(CEN); |
519 | pm_writel(GCCTRL(clk->index), control); | |
5f97f7f9 HS |
520 | } |
521 | ||
522 | static unsigned long genclk_get_rate(struct clk *clk) | |
523 | { | |
524 | u32 control; | |
525 | unsigned long div = 1; | |
526 | ||
7a5b8059 HS |
527 | control = pm_readl(GCCTRL(clk->index)); |
528 | if (control & PM_BIT(DIVEN)) | |
529 | div = 2 * (PM_BFEXT(DIV, control) + 1); | |
5f97f7f9 HS |
530 | |
531 | return clk->parent->get_rate(clk->parent) / div; | |
532 | } | |
533 | ||
534 | static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply) | |
535 | { | |
536 | u32 control; | |
537 | unsigned long parent_rate, actual_rate, div; | |
538 | ||
5f97f7f9 | 539 | parent_rate = clk->parent->get_rate(clk->parent); |
7a5b8059 | 540 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
541 | |
542 | if (rate > 3 * parent_rate / 4) { | |
543 | actual_rate = parent_rate; | |
7a5b8059 | 544 | control &= ~PM_BIT(DIVEN); |
5f97f7f9 HS |
545 | } else { |
546 | div = (parent_rate + rate) / (2 * rate) - 1; | |
7a5b8059 | 547 | control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN); |
5f97f7f9 HS |
548 | actual_rate = parent_rate / (2 * (div + 1)); |
549 | } | |
550 | ||
7a5b8059 HS |
551 | dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n", |
552 | clk->name, rate, actual_rate); | |
5f97f7f9 HS |
553 | |
554 | if (apply) | |
7a5b8059 | 555 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
556 | |
557 | return actual_rate; | |
558 | } | |
559 | ||
560 | int genclk_set_parent(struct clk *clk, struct clk *parent) | |
561 | { | |
562 | u32 control; | |
563 | ||
7a5b8059 HS |
564 | dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n", |
565 | clk->name, parent->name, clk->parent->name); | |
5f97f7f9 | 566 | |
7a5b8059 | 567 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
568 | |
569 | if (parent == &osc1 || parent == &pll1) | |
7a5b8059 | 570 | control |= PM_BIT(OSCSEL); |
5f97f7f9 | 571 | else if (parent == &osc0 || parent == &pll0) |
7a5b8059 | 572 | control &= ~PM_BIT(OSCSEL); |
5f97f7f9 HS |
573 | else |
574 | return -EINVAL; | |
575 | ||
576 | if (parent == &pll0 || parent == &pll1) | |
7a5b8059 | 577 | control |= PM_BIT(PLLSEL); |
5f97f7f9 | 578 | else |
7a5b8059 | 579 | control &= ~PM_BIT(PLLSEL); |
5f97f7f9 | 580 | |
7a5b8059 | 581 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
582 | clk->parent = parent; |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
7a5fe238 HS |
587 | static void __init genclk_init_parent(struct clk *clk) |
588 | { | |
589 | u32 control; | |
590 | struct clk *parent; | |
591 | ||
592 | BUG_ON(clk->index > 7); | |
593 | ||
7a5b8059 HS |
594 | control = pm_readl(GCCTRL(clk->index)); |
595 | if (control & PM_BIT(OSCSEL)) | |
596 | parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1; | |
7a5fe238 | 597 | else |
7a5b8059 | 598 | parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0; |
7a5fe238 HS |
599 | |
600 | clk->parent = parent; | |
601 | } | |
602 | ||
3bfb1d20 HS |
603 | static struct dw_dma_platform_data dw_dmac0_data = { |
604 | .nr_channels = 3, | |
605 | }; | |
606 | ||
607 | static struct resource dw_dmac0_resource[] = { | |
608 | PBMEM(0xff200000), | |
609 | IRQ(2), | |
610 | }; | |
611 | DEFINE_DEV_DATA(dw_dmac, 0); | |
612 | DEV_CLK(hclk, dw_dmac0, hsb, 10); | |
613 | ||
5f97f7f9 HS |
614 | /* -------------------------------------------------------------------- |
615 | * System peripherals | |
616 | * -------------------------------------------------------------------- */ | |
7a5b8059 HS |
617 | static struct resource at32_pm0_resource[] = { |
618 | { | |
619 | .start = 0xfff00000, | |
620 | .end = 0xfff0007f, | |
621 | .flags = IORESOURCE_MEM, | |
622 | }, | |
623 | IRQ(20), | |
5f97f7f9 | 624 | }; |
7a5b8059 HS |
625 | |
626 | static struct resource at32ap700x_rtc0_resource[] = { | |
627 | { | |
628 | .start = 0xfff00080, | |
629 | .end = 0xfff000af, | |
630 | .flags = IORESOURCE_MEM, | |
631 | }, | |
632 | IRQ(21), | |
5f97f7f9 | 633 | }; |
7a5b8059 HS |
634 | |
635 | static struct resource at32_wdt0_resource[] = { | |
636 | { | |
637 | .start = 0xfff000b0, | |
9797bed2 | 638 | .end = 0xfff000cf, |
7a5b8059 HS |
639 | .flags = IORESOURCE_MEM, |
640 | }, | |
641 | }; | |
642 | ||
643 | static struct resource at32_eic0_resource[] = { | |
644 | { | |
645 | .start = 0xfff00100, | |
646 | .end = 0xfff0013f, | |
647 | .flags = IORESOURCE_MEM, | |
648 | }, | |
649 | IRQ(19), | |
650 | }; | |
651 | ||
652 | DEFINE_DEV(at32_pm, 0); | |
653 | DEFINE_DEV(at32ap700x_rtc, 0); | |
654 | DEFINE_DEV(at32_wdt, 0); | |
655 | DEFINE_DEV(at32_eic, 0); | |
656 | ||
657 | /* | |
658 | * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this | |
659 | * is always running. | |
660 | */ | |
661 | static struct clk at32_pm_pclk = { | |
188ff65d | 662 | .name = "pclk", |
7a5b8059 | 663 | .dev = &at32_pm0_device.dev, |
188ff65d HS |
664 | .parent = &pbb_clk, |
665 | .mode = pbb_clk_mode, | |
666 | .get_rate = pbb_clk_get_rate, | |
667 | .users = 1, | |
668 | .index = 0, | |
669 | }; | |
5f97f7f9 HS |
670 | |
671 | static struct resource intc0_resource[] = { | |
672 | PBMEM(0xfff00400), | |
673 | }; | |
674 | struct platform_device at32_intc0_device = { | |
675 | .name = "intc", | |
676 | .id = 0, | |
677 | .resource = intc0_resource, | |
678 | .num_resources = ARRAY_SIZE(intc0_resource), | |
679 | }; | |
680 | DEV_CLK(pclk, at32_intc0, pbb, 1); | |
681 | ||
682 | static struct clk ebi_clk = { | |
683 | .name = "ebi", | |
684 | .parent = &hsb_clk, | |
685 | .mode = hsb_clk_mode, | |
686 | .get_rate = hsb_clk_get_rate, | |
687 | .users = 1, | |
688 | }; | |
689 | static struct clk hramc_clk = { | |
690 | .name = "hramc", | |
691 | .parent = &hsb_clk, | |
692 | .mode = hsb_clk_mode, | |
693 | .get_rate = hsb_clk_get_rate, | |
694 | .users = 1, | |
188ff65d | 695 | .index = 3, |
5f97f7f9 | 696 | }; |
7951f188 HS |
697 | static struct clk sdramc_clk = { |
698 | .name = "sdramc_clk", | |
699 | .parent = &pbb_clk, | |
700 | .mode = pbb_clk_mode, | |
701 | .get_rate = pbb_clk_get_rate, | |
702 | .users = 1, | |
703 | .index = 14, | |
704 | }; | |
5f97f7f9 | 705 | |
bc157b75 HS |
706 | static struct resource smc0_resource[] = { |
707 | PBMEM(0xfff03400), | |
708 | }; | |
709 | DEFINE_DEV(smc, 0); | |
710 | DEV_CLK(pclk, smc0, pbb, 13); | |
711 | DEV_CLK(mck, smc0, hsb, 0); | |
712 | ||
5f97f7f9 HS |
713 | static struct platform_device pdc_device = { |
714 | .name = "pdc", | |
715 | .id = 0, | |
716 | }; | |
717 | DEV_CLK(hclk, pdc, hsb, 4); | |
718 | DEV_CLK(pclk, pdc, pba, 16); | |
719 | ||
720 | static struct clk pico_clk = { | |
721 | .name = "pico", | |
722 | .parent = &cpu_clk, | |
723 | .mode = cpu_clk_mode, | |
724 | .get_rate = cpu_clk_get_rate, | |
725 | .users = 1, | |
726 | }; | |
727 | ||
9c8f8e75 HS |
728 | /* -------------------------------------------------------------------- |
729 | * HMATRIX | |
730 | * -------------------------------------------------------------------- */ | |
731 | ||
b47eb409 | 732 | struct clk at32_hmatrix_clk = { |
9c8f8e75 HS |
733 | .name = "hmatrix_clk", |
734 | .parent = &pbb_clk, | |
735 | .mode = pbb_clk_mode, | |
736 | .get_rate = pbb_clk_get_rate, | |
737 | .index = 2, | |
738 | .users = 1, | |
739 | }; | |
9c8f8e75 HS |
740 | |
741 | /* | |
742 | * Set bits in the HMATRIX Special Function Register (SFR) used by the | |
743 | * External Bus Interface (EBI). This can be used to enable special | |
744 | * features like CompactFlash support, NAND Flash support, etc. on | |
745 | * certain chipselects. | |
746 | */ | |
747 | static inline void set_ebi_sfr_bits(u32 mask) | |
748 | { | |
b47eb409 | 749 | hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask); |
9c8f8e75 HS |
750 | } |
751 | ||
7760989e | 752 | /* -------------------------------------------------------------------- |
e723ff66 | 753 | * Timer/Counter (TC) |
7760989e | 754 | * -------------------------------------------------------------------- */ |
e723ff66 DB |
755 | |
756 | static struct resource at32_tcb0_resource[] = { | |
7760989e HCE |
757 | PBMEM(0xfff00c00), |
758 | IRQ(22), | |
759 | }; | |
e723ff66 DB |
760 | static struct platform_device at32_tcb0_device = { |
761 | .name = "atmel_tcb", | |
7760989e | 762 | .id = 0, |
e723ff66 DB |
763 | .resource = at32_tcb0_resource, |
764 | .num_resources = ARRAY_SIZE(at32_tcb0_resource), | |
765 | }; | |
766 | DEV_CLK(t0_clk, at32_tcb0, pbb, 3); | |
767 | ||
768 | static struct resource at32_tcb1_resource[] = { | |
769 | PBMEM(0xfff01000), | |
770 | IRQ(23), | |
771 | }; | |
772 | static struct platform_device at32_tcb1_device = { | |
773 | .name = "atmel_tcb", | |
774 | .id = 1, | |
775 | .resource = at32_tcb1_resource, | |
776 | .num_resources = ARRAY_SIZE(at32_tcb1_resource), | |
7760989e | 777 | }; |
e723ff66 | 778 | DEV_CLK(t0_clk, at32_tcb1, pbb, 4); |
7760989e | 779 | |
5f97f7f9 HS |
780 | /* -------------------------------------------------------------------- |
781 | * PIO | |
782 | * -------------------------------------------------------------------- */ | |
783 | ||
784 | static struct resource pio0_resource[] = { | |
785 | PBMEM(0xffe02800), | |
786 | IRQ(13), | |
787 | }; | |
788 | DEFINE_DEV(pio, 0); | |
789 | DEV_CLK(mck, pio0, pba, 10); | |
790 | ||
791 | static struct resource pio1_resource[] = { | |
792 | PBMEM(0xffe02c00), | |
793 | IRQ(14), | |
794 | }; | |
795 | DEFINE_DEV(pio, 1); | |
796 | DEV_CLK(mck, pio1, pba, 11); | |
797 | ||
798 | static struct resource pio2_resource[] = { | |
799 | PBMEM(0xffe03000), | |
800 | IRQ(15), | |
801 | }; | |
802 | DEFINE_DEV(pio, 2); | |
803 | DEV_CLK(mck, pio2, pba, 12); | |
804 | ||
805 | static struct resource pio3_resource[] = { | |
806 | PBMEM(0xffe03400), | |
807 | IRQ(16), | |
808 | }; | |
809 | DEFINE_DEV(pio, 3); | |
810 | DEV_CLK(mck, pio3, pba, 13); | |
811 | ||
7f9f4678 HS |
812 | static struct resource pio4_resource[] = { |
813 | PBMEM(0xffe03800), | |
814 | IRQ(17), | |
815 | }; | |
816 | DEFINE_DEV(pio, 4); | |
817 | DEV_CLK(mck, pio4, pba, 14); | |
818 | ||
e82c6106 | 819 | static int __init system_device_init(void) |
5f97f7f9 | 820 | { |
7a5b8059 | 821 | platform_device_register(&at32_pm0_device); |
5f97f7f9 | 822 | platform_device_register(&at32_intc0_device); |
7a5b8059 HS |
823 | platform_device_register(&at32ap700x_rtc0_device); |
824 | platform_device_register(&at32_wdt0_device); | |
825 | platform_device_register(&at32_eic0_device); | |
bc157b75 | 826 | platform_device_register(&smc0_device); |
5f97f7f9 | 827 | platform_device_register(&pdc_device); |
3bfb1d20 | 828 | platform_device_register(&dw_dmac0_device); |
5f97f7f9 | 829 | |
e723ff66 DB |
830 | platform_device_register(&at32_tcb0_device); |
831 | platform_device_register(&at32_tcb1_device); | |
7760989e | 832 | |
5f97f7f9 HS |
833 | platform_device_register(&pio0_device); |
834 | platform_device_register(&pio1_device); | |
835 | platform_device_register(&pio2_device); | |
836 | platform_device_register(&pio3_device); | |
7f9f4678 | 837 | platform_device_register(&pio4_device); |
e82c6106 HS |
838 | |
839 | return 0; | |
5f97f7f9 | 840 | } |
e82c6106 | 841 | core_initcall(system_device_init); |
5f97f7f9 | 842 | |
d86d314f HCE |
843 | /* -------------------------------------------------------------------- |
844 | * PSIF | |
845 | * -------------------------------------------------------------------- */ | |
846 | static struct resource atmel_psif0_resource[] __initdata = { | |
847 | { | |
848 | .start = 0xffe03c00, | |
849 | .end = 0xffe03cff, | |
850 | .flags = IORESOURCE_MEM, | |
851 | }, | |
852 | IRQ(18), | |
853 | }; | |
854 | static struct clk atmel_psif0_pclk = { | |
855 | .name = "pclk", | |
856 | .parent = &pba_clk, | |
857 | .mode = pba_clk_mode, | |
858 | .get_rate = pba_clk_get_rate, | |
859 | .index = 15, | |
860 | }; | |
861 | ||
862 | static struct resource atmel_psif1_resource[] __initdata = { | |
863 | { | |
864 | .start = 0xffe03d00, | |
865 | .end = 0xffe03dff, | |
866 | .flags = IORESOURCE_MEM, | |
867 | }, | |
868 | IRQ(18), | |
869 | }; | |
870 | static struct clk atmel_psif1_pclk = { | |
871 | .name = "pclk", | |
872 | .parent = &pba_clk, | |
873 | .mode = pba_clk_mode, | |
874 | .get_rate = pba_clk_get_rate, | |
875 | .index = 15, | |
876 | }; | |
877 | ||
878 | struct platform_device *__init at32_add_device_psif(unsigned int id) | |
879 | { | |
880 | struct platform_device *pdev; | |
caf18f19 | 881 | u32 pin_mask; |
d86d314f HCE |
882 | |
883 | if (!(id == 0 || id == 1)) | |
884 | return NULL; | |
885 | ||
886 | pdev = platform_device_alloc("atmel_psif", id); | |
887 | if (!pdev) | |
888 | return NULL; | |
889 | ||
890 | switch (id) { | |
891 | case 0: | |
caf18f19 JM |
892 | pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */ |
893 | ||
d86d314f HCE |
894 | if (platform_device_add_resources(pdev, atmel_psif0_resource, |
895 | ARRAY_SIZE(atmel_psif0_resource))) | |
896 | goto err_add_resources; | |
897 | atmel_psif0_pclk.dev = &pdev->dev; | |
caf18f19 | 898 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); |
d86d314f HCE |
899 | break; |
900 | case 1: | |
caf18f19 JM |
901 | pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */ |
902 | ||
d86d314f HCE |
903 | if (platform_device_add_resources(pdev, atmel_psif1_resource, |
904 | ARRAY_SIZE(atmel_psif1_resource))) | |
905 | goto err_add_resources; | |
906 | atmel_psif1_pclk.dev = &pdev->dev; | |
caf18f19 | 907 | select_peripheral(PIOB, pin_mask, PERIPH_A, 0); |
d86d314f HCE |
908 | break; |
909 | default: | |
910 | return NULL; | |
911 | } | |
912 | ||
913 | platform_device_add(pdev); | |
914 | return pdev; | |
915 | ||
916 | err_add_resources: | |
917 | platform_device_put(pdev); | |
918 | return NULL; | |
919 | } | |
920 | ||
5f97f7f9 HS |
921 | /* -------------------------------------------------------------------- |
922 | * USART | |
923 | * -------------------------------------------------------------------- */ | |
924 | ||
75d35213 HS |
925 | static struct atmel_uart_data atmel_usart0_data = { |
926 | .use_dma_tx = 1, | |
927 | .use_dma_rx = 1, | |
928 | }; | |
1e8ea802 | 929 | static struct resource atmel_usart0_resource[] = { |
5f97f7f9 | 930 | PBMEM(0xffe00c00), |
a3d912c8 | 931 | IRQ(6), |
5f97f7f9 | 932 | }; |
75d35213 | 933 | DEFINE_DEV_DATA(atmel_usart, 0); |
80f76c54 | 934 | DEV_CLK(usart, atmel_usart0, pba, 3); |
5f97f7f9 | 935 | |
75d35213 HS |
936 | static struct atmel_uart_data atmel_usart1_data = { |
937 | .use_dma_tx = 1, | |
938 | .use_dma_rx = 1, | |
939 | }; | |
1e8ea802 | 940 | static struct resource atmel_usart1_resource[] = { |
5f97f7f9 HS |
941 | PBMEM(0xffe01000), |
942 | IRQ(7), | |
943 | }; | |
75d35213 | 944 | DEFINE_DEV_DATA(atmel_usart, 1); |
1e8ea802 | 945 | DEV_CLK(usart, atmel_usart1, pba, 4); |
5f97f7f9 | 946 | |
75d35213 HS |
947 | static struct atmel_uart_data atmel_usart2_data = { |
948 | .use_dma_tx = 1, | |
949 | .use_dma_rx = 1, | |
950 | }; | |
1e8ea802 | 951 | static struct resource atmel_usart2_resource[] = { |
5f97f7f9 HS |
952 | PBMEM(0xffe01400), |
953 | IRQ(8), | |
954 | }; | |
75d35213 | 955 | DEFINE_DEV_DATA(atmel_usart, 2); |
1e8ea802 | 956 | DEV_CLK(usart, atmel_usart2, pba, 5); |
5f97f7f9 | 957 | |
75d35213 HS |
958 | static struct atmel_uart_data atmel_usart3_data = { |
959 | .use_dma_tx = 1, | |
960 | .use_dma_rx = 1, | |
961 | }; | |
1e8ea802 | 962 | static struct resource atmel_usart3_resource[] = { |
5f97f7f9 HS |
963 | PBMEM(0xffe01800), |
964 | IRQ(9), | |
965 | }; | |
75d35213 | 966 | DEFINE_DEV_DATA(atmel_usart, 3); |
1e8ea802 | 967 | DEV_CLK(usart, atmel_usart3, pba, 6); |
5f97f7f9 HS |
968 | |
969 | static inline void configure_usart0_pins(void) | |
970 | { | |
caf18f19 JM |
971 | u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */ |
972 | ||
10546263 | 973 | select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); |
5f97f7f9 HS |
974 | } |
975 | ||
976 | static inline void configure_usart1_pins(void) | |
977 | { | |
caf18f19 JM |
978 | u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */ |
979 | ||
10546263 | 980 | select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP); |
5f97f7f9 HS |
981 | } |
982 | ||
983 | static inline void configure_usart2_pins(void) | |
984 | { | |
caf18f19 JM |
985 | u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */ |
986 | ||
10546263 | 987 | select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); |
5f97f7f9 HS |
988 | } |
989 | ||
990 | static inline void configure_usart3_pins(void) | |
991 | { | |
caf18f19 JM |
992 | u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */ |
993 | ||
10546263 | 994 | select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP); |
5f97f7f9 HS |
995 | } |
996 | ||
a3d912c8 | 997 | static struct platform_device *__initdata at32_usarts[4]; |
c194588d HS |
998 | |
999 | void __init at32_map_usart(unsigned int hw_id, unsigned int line) | |
5f97f7f9 HS |
1000 | { |
1001 | struct platform_device *pdev; | |
1002 | ||
c194588d | 1003 | switch (hw_id) { |
5f97f7f9 | 1004 | case 0: |
1e8ea802 | 1005 | pdev = &atmel_usart0_device; |
5f97f7f9 HS |
1006 | configure_usart0_pins(); |
1007 | break; | |
1008 | case 1: | |
1e8ea802 | 1009 | pdev = &atmel_usart1_device; |
5f97f7f9 HS |
1010 | configure_usart1_pins(); |
1011 | break; | |
1012 | case 2: | |
1e8ea802 | 1013 | pdev = &atmel_usart2_device; |
5f97f7f9 HS |
1014 | configure_usart2_pins(); |
1015 | break; | |
1016 | case 3: | |
1e8ea802 | 1017 | pdev = &atmel_usart3_device; |
5f97f7f9 HS |
1018 | configure_usart3_pins(); |
1019 | break; | |
1020 | default: | |
c194588d | 1021 | return; |
75d35213 HS |
1022 | } |
1023 | ||
1024 | if (PXSEG(pdev->resource[0].start) == P4SEG) { | |
1025 | /* Addresses in the P4 segment are permanently mapped 1:1 */ | |
1026 | struct atmel_uart_data *data = pdev->dev.platform_data; | |
1027 | data->regs = (void __iomem *)pdev->resource[0].start; | |
5f97f7f9 HS |
1028 | } |
1029 | ||
c194588d HS |
1030 | pdev->id = line; |
1031 | at32_usarts[line] = pdev; | |
5f97f7f9 HS |
1032 | } |
1033 | ||
1034 | struct platform_device *__init at32_add_device_usart(unsigned int id) | |
1035 | { | |
c194588d HS |
1036 | platform_device_register(at32_usarts[id]); |
1037 | return at32_usarts[id]; | |
5f97f7f9 HS |
1038 | } |
1039 | ||
73e2798b | 1040 | struct platform_device *atmel_default_console_device; |
5f97f7f9 HS |
1041 | |
1042 | void __init at32_setup_serial_console(unsigned int usart_id) | |
1043 | { | |
c194588d | 1044 | atmel_default_console_device = at32_usarts[usart_id]; |
5f97f7f9 HS |
1045 | } |
1046 | ||
1047 | /* -------------------------------------------------------------------- | |
1048 | * Ethernet | |
1049 | * -------------------------------------------------------------------- */ | |
1050 | ||
438ff3f3 | 1051 | #ifdef CONFIG_CPU_AT32AP7000 |
5f97f7f9 HS |
1052 | static struct eth_platform_data macb0_data; |
1053 | static struct resource macb0_resource[] = { | |
1054 | PBMEM(0xfff01800), | |
1055 | IRQ(25), | |
1056 | }; | |
1057 | DEFINE_DEV_DATA(macb, 0); | |
1058 | DEV_CLK(hclk, macb0, hsb, 8); | |
1059 | DEV_CLK(pclk, macb0, pbb, 6); | |
1060 | ||
cfcb3a89 HS |
1061 | static struct eth_platform_data macb1_data; |
1062 | static struct resource macb1_resource[] = { | |
1063 | PBMEM(0xfff01c00), | |
1064 | IRQ(26), | |
1065 | }; | |
1066 | DEFINE_DEV_DATA(macb, 1); | |
1067 | DEV_CLK(hclk, macb1, hsb, 9); | |
1068 | DEV_CLK(pclk, macb1, pbb, 7); | |
1069 | ||
5f97f7f9 HS |
1070 | struct platform_device *__init |
1071 | at32_add_device_eth(unsigned int id, struct eth_platform_data *data) | |
1072 | { | |
1073 | struct platform_device *pdev; | |
caf18f19 | 1074 | u32 pin_mask; |
5f97f7f9 HS |
1075 | |
1076 | switch (id) { | |
1077 | case 0: | |
1078 | pdev = &macb0_device; | |
1079 | ||
caf18f19 JM |
1080 | pin_mask = (1 << 3); /* TXD0 */ |
1081 | pin_mask |= (1 << 4); /* TXD1 */ | |
1082 | pin_mask |= (1 << 7); /* TXEN */ | |
1083 | pin_mask |= (1 << 8); /* TXCK */ | |
1084 | pin_mask |= (1 << 9); /* RXD0 */ | |
1085 | pin_mask |= (1 << 10); /* RXD1 */ | |
1086 | pin_mask |= (1 << 13); /* RXER */ | |
1087 | pin_mask |= (1 << 15); /* RXDV */ | |
1088 | pin_mask |= (1 << 16); /* MDC */ | |
1089 | pin_mask |= (1 << 17); /* MDIO */ | |
5f97f7f9 HS |
1090 | |
1091 | if (!data->is_rmii) { | |
caf18f19 JM |
1092 | pin_mask |= (1 << 0); /* COL */ |
1093 | pin_mask |= (1 << 1); /* CRS */ | |
1094 | pin_mask |= (1 << 2); /* TXER */ | |
1095 | pin_mask |= (1 << 5); /* TXD2 */ | |
1096 | pin_mask |= (1 << 6); /* TXD3 */ | |
1097 | pin_mask |= (1 << 11); /* RXD2 */ | |
1098 | pin_mask |= (1 << 12); /* RXD3 */ | |
1099 | pin_mask |= (1 << 14); /* RXCK */ | |
198f2935 | 1100 | #ifndef CONFIG_BOARD_MIMC200 |
caf18f19 | 1101 | pin_mask |= (1 << 18); /* SPD */ |
198f2935 | 1102 | #endif |
5f97f7f9 | 1103 | } |
caf18f19 JM |
1104 | |
1105 | select_peripheral(PIOC, pin_mask, PERIPH_A, 0); | |
1106 | ||
5f97f7f9 HS |
1107 | break; |
1108 | ||
cfcb3a89 HS |
1109 | case 1: |
1110 | pdev = &macb1_device; | |
1111 | ||
caf18f19 JM |
1112 | pin_mask = (1 << 13); /* TXD0 */ |
1113 | pin_mask |= (1 << 14); /* TXD1 */ | |
1114 | pin_mask |= (1 << 11); /* TXEN */ | |
1115 | pin_mask |= (1 << 12); /* TXCK */ | |
1116 | pin_mask |= (1 << 10); /* RXD0 */ | |
1117 | pin_mask |= (1 << 6); /* RXD1 */ | |
1118 | pin_mask |= (1 << 5); /* RXER */ | |
1119 | pin_mask |= (1 << 4); /* RXDV */ | |
1120 | pin_mask |= (1 << 3); /* MDC */ | |
1121 | pin_mask |= (1 << 2); /* MDIO */ | |
1122 | ||
198f2935 | 1123 | #ifndef CONFIG_BOARD_MIMC200 |
caf18f19 JM |
1124 | if (!data->is_rmii) |
1125 | pin_mask |= (1 << 15); /* SPD */ | |
198f2935 | 1126 | #endif |
caf18f19 JM |
1127 | |
1128 | select_peripheral(PIOD, pin_mask, PERIPH_B, 0); | |
cfcb3a89 HS |
1129 | |
1130 | if (!data->is_rmii) { | |
caf18f19 JM |
1131 | pin_mask = (1 << 19); /* COL */ |
1132 | pin_mask |= (1 << 23); /* CRS */ | |
1133 | pin_mask |= (1 << 26); /* TXER */ | |
1134 | pin_mask |= (1 << 27); /* TXD2 */ | |
1135 | pin_mask |= (1 << 28); /* TXD3 */ | |
1136 | pin_mask |= (1 << 29); /* RXD2 */ | |
1137 | pin_mask |= (1 << 30); /* RXD3 */ | |
1138 | pin_mask |= (1 << 24); /* RXCK */ | |
1139 | ||
1140 | select_peripheral(PIOC, pin_mask, PERIPH_B, 0); | |
cfcb3a89 HS |
1141 | } |
1142 | break; | |
1143 | ||
5f97f7f9 HS |
1144 | default: |
1145 | return NULL; | |
1146 | } | |
1147 | ||
1148 | memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data)); | |
1149 | platform_device_register(pdev); | |
1150 | ||
1151 | return pdev; | |
1152 | } | |
438ff3f3 | 1153 | #endif |
5f97f7f9 HS |
1154 | |
1155 | /* -------------------------------------------------------------------- | |
1156 | * SPI | |
1157 | * -------------------------------------------------------------------- */ | |
3d60ee1b | 1158 | static struct resource atmel_spi0_resource[] = { |
5f97f7f9 HS |
1159 | PBMEM(0xffe00000), |
1160 | IRQ(3), | |
1161 | }; | |
3d60ee1b HS |
1162 | DEFINE_DEV(atmel_spi, 0); |
1163 | DEV_CLK(spi_clk, atmel_spi0, pba, 0); | |
1164 | ||
1165 | static struct resource atmel_spi1_resource[] = { | |
1166 | PBMEM(0xffe00400), | |
1167 | IRQ(4), | |
1168 | }; | |
1169 | DEFINE_DEV(atmel_spi, 1); | |
1170 | DEV_CLK(spi_clk, atmel_spi1, pba, 1); | |
5f97f7f9 | 1171 | |
9a596a62 | 1172 | static void __init |
41d8ca45 HS |
1173 | at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, |
1174 | unsigned int n, const u8 *pins) | |
5f97f7f9 | 1175 | { |
41d8ca45 HS |
1176 | unsigned int pin, mode; |
1177 | ||
1178 | for (; n; n--, b++) { | |
1179 | b->bus_num = bus_num; | |
1180 | if (b->chip_select >= 4) | |
1181 | continue; | |
1182 | pin = (unsigned)b->controller_data; | |
1183 | if (!pin) { | |
1184 | pin = pins[b->chip_select]; | |
1185 | b->controller_data = (void *)pin; | |
1186 | } | |
1187 | mode = AT32_GPIOF_OUTPUT; | |
1188 | if (!(b->mode & SPI_CS_HIGH)) | |
1189 | mode |= AT32_GPIOF_HIGH; | |
1190 | at32_select_gpio(pin, mode); | |
1191 | } | |
1192 | } | |
1193 | ||
1194 | struct platform_device *__init | |
1195 | at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n) | |
1196 | { | |
1197 | /* | |
1198 | * Manage the chipselects as GPIOs, normally using the same pins | |
1199 | * the SPI controller expects; but boards can use other pins. | |
1200 | */ | |
1201 | static u8 __initdata spi0_pins[] = | |
1202 | { GPIO_PIN_PA(3), GPIO_PIN_PA(4), | |
1203 | GPIO_PIN_PA(5), GPIO_PIN_PA(20), }; | |
1204 | static u8 __initdata spi1_pins[] = | |
1205 | { GPIO_PIN_PB(2), GPIO_PIN_PB(3), | |
1206 | GPIO_PIN_PB(4), GPIO_PIN_PA(27), }; | |
5f97f7f9 | 1207 | struct platform_device *pdev; |
caf18f19 | 1208 | u32 pin_mask; |
5f97f7f9 HS |
1209 | |
1210 | switch (id) { | |
1211 | case 0: | |
3d60ee1b | 1212 | pdev = &atmel_spi0_device; |
caf18f19 JM |
1213 | pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */ |
1214 | ||
9c2baf78 | 1215 | /* pullup MISO so a level is always defined */ |
caf18f19 JM |
1216 | select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP); |
1217 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); | |
1218 | ||
41d8ca45 | 1219 | at32_spi_setup_slaves(0, b, n, spi0_pins); |
3d60ee1b HS |
1220 | break; |
1221 | ||
1222 | case 1: | |
1223 | pdev = &atmel_spi1_device; | |
caf18f19 JM |
1224 | pin_mask = (1 << 1) | (1 << 5); /* MOSI */ |
1225 | ||
9c2baf78 | 1226 | /* pullup MISO so a level is always defined */ |
caf18f19 JM |
1227 | select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP); |
1228 | select_peripheral(PIOB, pin_mask, PERIPH_B, 0); | |
1229 | ||
41d8ca45 | 1230 | at32_spi_setup_slaves(1, b, n, spi1_pins); |
5f97f7f9 HS |
1231 | break; |
1232 | ||
1233 | default: | |
1234 | return NULL; | |
1235 | } | |
1236 | ||
41d8ca45 | 1237 | spi_register_board_info(b, n); |
5f97f7f9 HS |
1238 | platform_device_register(pdev); |
1239 | return pdev; | |
1240 | } | |
1241 | ||
2042c1c4 HS |
1242 | /* -------------------------------------------------------------------- |
1243 | * TWI | |
1244 | * -------------------------------------------------------------------- */ | |
1245 | static struct resource atmel_twi0_resource[] __initdata = { | |
1246 | PBMEM(0xffe00800), | |
1247 | IRQ(5), | |
1248 | }; | |
1249 | static struct clk atmel_twi0_pclk = { | |
1250 | .name = "twi_pclk", | |
1251 | .parent = &pba_clk, | |
1252 | .mode = pba_clk_mode, | |
1253 | .get_rate = pba_clk_get_rate, | |
1254 | .index = 2, | |
1255 | }; | |
1256 | ||
040b28fc BN |
1257 | struct platform_device *__init at32_add_device_twi(unsigned int id, |
1258 | struct i2c_board_info *b, | |
1259 | unsigned int n) | |
2042c1c4 HS |
1260 | { |
1261 | struct platform_device *pdev; | |
caf18f19 | 1262 | u32 pin_mask; |
2042c1c4 HS |
1263 | |
1264 | if (id != 0) | |
1265 | return NULL; | |
1266 | ||
1267 | pdev = platform_device_alloc("atmel_twi", id); | |
1268 | if (!pdev) | |
1269 | return NULL; | |
1270 | ||
1271 | if (platform_device_add_resources(pdev, atmel_twi0_resource, | |
1272 | ARRAY_SIZE(atmel_twi0_resource))) | |
1273 | goto err_add_resources; | |
1274 | ||
caf18f19 JM |
1275 | pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */ |
1276 | ||
1277 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); | |
2042c1c4 HS |
1278 | |
1279 | atmel_twi0_pclk.dev = &pdev->dev; | |
1280 | ||
040b28fc BN |
1281 | if (b) |
1282 | i2c_register_board_info(id, b, n); | |
1283 | ||
2042c1c4 HS |
1284 | platform_device_add(pdev); |
1285 | return pdev; | |
1286 | ||
1287 | err_add_resources: | |
1288 | platform_device_put(pdev); | |
1289 | return NULL; | |
1290 | } | |
1291 | ||
1292 | /* -------------------------------------------------------------------- | |
1293 | * MMC | |
1294 | * -------------------------------------------------------------------- */ | |
1295 | static struct resource atmel_mci0_resource[] __initdata = { | |
1296 | PBMEM(0xfff02400), | |
1297 | IRQ(28), | |
1298 | }; | |
1299 | static struct clk atmel_mci0_pclk = { | |
1300 | .name = "mci_clk", | |
1301 | .parent = &pbb_clk, | |
1302 | .mode = pbb_clk_mode, | |
1303 | .get_rate = pbb_clk_get_rate, | |
1304 | .index = 9, | |
1305 | }; | |
1306 | ||
7d2be074 HS |
1307 | struct platform_device *__init |
1308 | at32_add_device_mci(unsigned int id, struct mci_platform_data *data) | |
2042c1c4 | 1309 | { |
7d2be074 | 1310 | struct platform_device *pdev; |
74465b4f | 1311 | struct dw_dma_slave *dws = &data->dma_slave; |
caf18f19 JM |
1312 | u32 pioa_mask; |
1313 | u32 piob_mask; | |
2042c1c4 | 1314 | |
6b918657 HS |
1315 | if (id != 0 || !data) |
1316 | return NULL; | |
1317 | ||
1318 | /* Must have at least one usable slot */ | |
1319 | if (!data->slot[0].bus_width && !data->slot[1].bus_width) | |
2042c1c4 HS |
1320 | return NULL; |
1321 | ||
1322 | pdev = platform_device_alloc("atmel_mci", id); | |
1323 | if (!pdev) | |
7d2be074 | 1324 | goto fail; |
2042c1c4 HS |
1325 | |
1326 | if (platform_device_add_resources(pdev, atmel_mci0_resource, | |
1327 | ARRAY_SIZE(atmel_mci0_resource))) | |
7d2be074 HS |
1328 | goto fail; |
1329 | ||
74465b4f DW |
1330 | dws->dma_dev = &dw_dmac0_device.dev; |
1331 | dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT; | |
65e8b083 HS |
1332 | dws->cfg_hi = (DWC_CFGH_SRC_PER(0) |
1333 | | DWC_CFGH_DST_PER(1)); | |
1334 | dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | |
1335 | | DWC_CFGL_HS_SRC_POL); | |
1336 | ||
7d2be074 HS |
1337 | if (platform_device_add_data(pdev, data, |
1338 | sizeof(struct mci_platform_data))) | |
1339 | goto fail; | |
2042c1c4 | 1340 | |
6b918657 | 1341 | /* CLK line is common to both slots */ |
caf18f19 | 1342 | pioa_mask = 1 << 10; |
6b918657 HS |
1343 | |
1344 | switch (data->slot[0].bus_width) { | |
1345 | case 4: | |
caf18f19 JM |
1346 | pioa_mask |= 1 << 13; /* DATA1 */ |
1347 | pioa_mask |= 1 << 14; /* DATA2 */ | |
1348 | pioa_mask |= 1 << 15; /* DATA3 */ | |
6b918657 HS |
1349 | /* fall through */ |
1350 | case 1: | |
caf18f19 JM |
1351 | pioa_mask |= 1 << 11; /* CMD */ |
1352 | pioa_mask |= 1 << 12; /* DATA0 */ | |
6b918657 HS |
1353 | |
1354 | if (gpio_is_valid(data->slot[0].detect_pin)) | |
1355 | at32_select_gpio(data->slot[0].detect_pin, 0); | |
1356 | if (gpio_is_valid(data->slot[0].wp_pin)) | |
1357 | at32_select_gpio(data->slot[0].wp_pin, 0); | |
1358 | break; | |
1359 | case 0: | |
1360 | /* Slot is unused */ | |
1361 | break; | |
1362 | default: | |
1363 | goto fail; | |
1364 | } | |
1365 | ||
caf18f19 JM |
1366 | select_peripheral(PIOA, pioa_mask, PERIPH_A, 0); |
1367 | piob_mask = 0; | |
1368 | ||
6b918657 HS |
1369 | switch (data->slot[1].bus_width) { |
1370 | case 4: | |
caf18f19 JM |
1371 | piob_mask |= 1 << 8; /* DATA1 */ |
1372 | piob_mask |= 1 << 9; /* DATA2 */ | |
1373 | piob_mask |= 1 << 10; /* DATA3 */ | |
6b918657 HS |
1374 | /* fall through */ |
1375 | case 1: | |
caf18f19 JM |
1376 | piob_mask |= 1 << 6; /* CMD */ |
1377 | piob_mask |= 1 << 7; /* DATA0 */ | |
1378 | select_peripheral(PIOB, piob_mask, PERIPH_B, 0); | |
6b918657 HS |
1379 | |
1380 | if (gpio_is_valid(data->slot[1].detect_pin)) | |
1381 | at32_select_gpio(data->slot[1].detect_pin, 0); | |
1382 | if (gpio_is_valid(data->slot[1].wp_pin)) | |
1383 | at32_select_gpio(data->slot[1].wp_pin, 0); | |
1384 | break; | |
1385 | case 0: | |
1386 | /* Slot is unused */ | |
1387 | break; | |
1388 | default: | |
1389 | if (!data->slot[0].bus_width) | |
1390 | goto fail; | |
1391 | ||
1392 | data->slot[1].bus_width = 0; | |
1393 | break; | |
1394 | } | |
7d2be074 | 1395 | |
2042c1c4 HS |
1396 | atmel_mci0_pclk.dev = &pdev->dev; |
1397 | ||
1398 | platform_device_add(pdev); | |
1399 | return pdev; | |
1400 | ||
7d2be074 | 1401 | fail: |
2042c1c4 HS |
1402 | platform_device_put(pdev); |
1403 | return NULL; | |
1404 | } | |
1405 | ||
5f97f7f9 HS |
1406 | /* -------------------------------------------------------------------- |
1407 | * LCDC | |
1408 | * -------------------------------------------------------------------- */ | |
438ff3f3 | 1409 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af HS |
1410 | static struct atmel_lcdfb_info atmel_lcdfb0_data; |
1411 | static struct resource atmel_lcdfb0_resource[] = { | |
5f97f7f9 HS |
1412 | { |
1413 | .start = 0xff000000, | |
1414 | .end = 0xff000fff, | |
1415 | .flags = IORESOURCE_MEM, | |
1416 | }, | |
1417 | IRQ(1), | |
d0a2b7af HS |
1418 | { |
1419 | /* Placeholder for pre-allocated fb memory */ | |
1420 | .start = 0x00000000, | |
1421 | .end = 0x00000000, | |
1422 | .flags = 0, | |
1423 | }, | |
5f97f7f9 | 1424 | }; |
d0a2b7af HS |
1425 | DEFINE_DEV_DATA(atmel_lcdfb, 0); |
1426 | DEV_CLK(hck1, atmel_lcdfb0, hsb, 7); | |
1427 | static struct clk atmel_lcdfb0_pixclk = { | |
1428 | .name = "lcdc_clk", | |
1429 | .dev = &atmel_lcdfb0_device.dev, | |
5f97f7f9 HS |
1430 | .mode = genclk_mode, |
1431 | .get_rate = genclk_get_rate, | |
1432 | .set_rate = genclk_set_rate, | |
1433 | .set_parent = genclk_set_parent, | |
1434 | .index = 7, | |
1435 | }; | |
1436 | ||
1437 | struct platform_device *__init | |
d0a2b7af | 1438 | at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, |
47882cf6 | 1439 | unsigned long fbmem_start, unsigned long fbmem_len, |
70664124 | 1440 | u64 pin_mask) |
5f97f7f9 HS |
1441 | { |
1442 | struct platform_device *pdev; | |
d0a2b7af HS |
1443 | struct atmel_lcdfb_info *info; |
1444 | struct fb_monspecs *monspecs; | |
1445 | struct fb_videomode *modedb; | |
1446 | unsigned int modedb_size; | |
caf18f19 | 1447 | u32 portc_mask, portd_mask, porte_mask; |
d0a2b7af HS |
1448 | |
1449 | /* | |
1450 | * Do a deep copy of the fb data, monspecs and modedb. Make | |
1451 | * sure all allocations are done before setting up the | |
1452 | * portmux. | |
1453 | */ | |
1454 | monspecs = kmemdup(data->default_monspecs, | |
1455 | sizeof(struct fb_monspecs), GFP_KERNEL); | |
1456 | if (!monspecs) | |
1457 | return NULL; | |
1458 | ||
1459 | modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len; | |
1460 | modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL); | |
1461 | if (!modedb) | |
1462 | goto err_dup_modedb; | |
1463 | monspecs->modedb = modedb; | |
5f97f7f9 HS |
1464 | |
1465 | switch (id) { | |
1466 | case 0: | |
d0a2b7af | 1467 | pdev = &atmel_lcdfb0_device; |
47882cf6 | 1468 | |
70664124 JM |
1469 | if (pin_mask == 0ULL) |
1470 | /* Default to "full" lcdc control signals and 24bit */ | |
1471 | pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL; | |
1472 | ||
1473 | /* LCDC on port C */ | |
60900656 | 1474 | portc_mask = pin_mask & 0xfff80000; |
caf18f19 | 1475 | select_peripheral(PIOC, portc_mask, PERIPH_A, 0); |
70664124 JM |
1476 | |
1477 | /* LCDC on port D */ | |
caf18f19 JM |
1478 | portd_mask = pin_mask & 0x0003ffff; |
1479 | select_peripheral(PIOD, portd_mask, PERIPH_A, 0); | |
70664124 JM |
1480 | |
1481 | /* LCDC on port E */ | |
caf18f19 JM |
1482 | porte_mask = (pin_mask >> 32) & 0x0007ffff; |
1483 | select_peripheral(PIOE, porte_mask, PERIPH_B, 0); | |
5f97f7f9 | 1484 | |
d0a2b7af HS |
1485 | clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); |
1486 | clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); | |
5f97f7f9 HS |
1487 | break; |
1488 | ||
1489 | default: | |
d0a2b7af | 1490 | goto err_invalid_id; |
5f97f7f9 HS |
1491 | } |
1492 | ||
d0a2b7af HS |
1493 | if (fbmem_len) { |
1494 | pdev->resource[2].start = fbmem_start; | |
1495 | pdev->resource[2].end = fbmem_start + fbmem_len - 1; | |
1496 | pdev->resource[2].flags = IORESOURCE_MEM; | |
1497 | } | |
1498 | ||
1499 | info = pdev->dev.platform_data; | |
1500 | memcpy(info, data, sizeof(struct atmel_lcdfb_info)); | |
1501 | info->default_monspecs = monspecs; | |
5f97f7f9 HS |
1502 | |
1503 | platform_device_register(pdev); | |
1504 | return pdev; | |
d0a2b7af HS |
1505 | |
1506 | err_invalid_id: | |
1507 | kfree(modedb); | |
1508 | err_dup_modedb: | |
1509 | kfree(monspecs); | |
1510 | return NULL; | |
5f97f7f9 | 1511 | } |
438ff3f3 | 1512 | #endif |
5f97f7f9 | 1513 | |
9a1e8eb1 DB |
1514 | /* -------------------------------------------------------------------- |
1515 | * PWM | |
1516 | * -------------------------------------------------------------------- */ | |
1517 | static struct resource atmel_pwm0_resource[] __initdata = { | |
1518 | PBMEM(0xfff01400), | |
1519 | IRQ(24), | |
1520 | }; | |
1521 | static struct clk atmel_pwm0_mck = { | |
8405996f | 1522 | .name = "pwm_clk", |
9a1e8eb1 DB |
1523 | .parent = &pbb_clk, |
1524 | .mode = pbb_clk_mode, | |
1525 | .get_rate = pbb_clk_get_rate, | |
1526 | .index = 5, | |
1527 | }; | |
1528 | ||
1529 | struct platform_device *__init at32_add_device_pwm(u32 mask) | |
1530 | { | |
1531 | struct platform_device *pdev; | |
caf18f19 | 1532 | u32 pin_mask; |
9a1e8eb1 DB |
1533 | |
1534 | if (!mask) | |
1535 | return NULL; | |
1536 | ||
1537 | pdev = platform_device_alloc("atmel_pwm", 0); | |
1538 | if (!pdev) | |
1539 | return NULL; | |
1540 | ||
1541 | if (platform_device_add_resources(pdev, atmel_pwm0_resource, | |
1542 | ARRAY_SIZE(atmel_pwm0_resource))) | |
1543 | goto out_free_pdev; | |
1544 | ||
1545 | if (platform_device_add_data(pdev, &mask, sizeof(mask))) | |
1546 | goto out_free_pdev; | |
1547 | ||
caf18f19 | 1548 | pin_mask = 0; |
9a1e8eb1 | 1549 | if (mask & (1 << 0)) |
caf18f19 | 1550 | pin_mask |= (1 << 28); |
9a1e8eb1 | 1551 | if (mask & (1 << 1)) |
caf18f19 JM |
1552 | pin_mask |= (1 << 29); |
1553 | if (pin_mask > 0) | |
1554 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); | |
1555 | ||
1556 | pin_mask = 0; | |
9a1e8eb1 | 1557 | if (mask & (1 << 2)) |
caf18f19 | 1558 | pin_mask |= (1 << 21); |
9a1e8eb1 | 1559 | if (mask & (1 << 3)) |
caf18f19 JM |
1560 | pin_mask |= (1 << 22); |
1561 | if (pin_mask > 0) | |
1562 | select_peripheral(PIOA, pin_mask, PERIPH_B, 0); | |
9a1e8eb1 DB |
1563 | |
1564 | atmel_pwm0_mck.dev = &pdev->dev; | |
1565 | ||
1566 | platform_device_add(pdev); | |
1567 | ||
1568 | return pdev; | |
1569 | ||
1570 | out_free_pdev: | |
1571 | platform_device_put(pdev); | |
1572 | return NULL; | |
1573 | } | |
1574 | ||
9cf6cf58 HCE |
1575 | /* -------------------------------------------------------------------- |
1576 | * SSC | |
1577 | * -------------------------------------------------------------------- */ | |
1578 | static struct resource ssc0_resource[] = { | |
1579 | PBMEM(0xffe01c00), | |
1580 | IRQ(10), | |
1581 | }; | |
1582 | DEFINE_DEV(ssc, 0); | |
1583 | DEV_CLK(pclk, ssc0, pba, 7); | |
1584 | ||
1585 | static struct resource ssc1_resource[] = { | |
1586 | PBMEM(0xffe02000), | |
1587 | IRQ(11), | |
1588 | }; | |
1589 | DEFINE_DEV(ssc, 1); | |
1590 | DEV_CLK(pclk, ssc1, pba, 8); | |
1591 | ||
1592 | static struct resource ssc2_resource[] = { | |
1593 | PBMEM(0xffe02400), | |
1594 | IRQ(12), | |
1595 | }; | |
1596 | DEFINE_DEV(ssc, 2); | |
1597 | DEV_CLK(pclk, ssc2, pba, 9); | |
1598 | ||
1599 | struct platform_device *__init | |
1600 | at32_add_device_ssc(unsigned int id, unsigned int flags) | |
1601 | { | |
1602 | struct platform_device *pdev; | |
caf18f19 | 1603 | u32 pin_mask = 0; |
9cf6cf58 HCE |
1604 | |
1605 | switch (id) { | |
1606 | case 0: | |
1607 | pdev = &ssc0_device; | |
1608 | if (flags & ATMEL_SSC_RF) | |
caf18f19 | 1609 | pin_mask |= (1 << 21); /* RF */ |
9cf6cf58 | 1610 | if (flags & ATMEL_SSC_RK) |
caf18f19 | 1611 | pin_mask |= (1 << 22); /* RK */ |
9cf6cf58 | 1612 | if (flags & ATMEL_SSC_TK) |
caf18f19 | 1613 | pin_mask |= (1 << 23); /* TK */ |
9cf6cf58 | 1614 | if (flags & ATMEL_SSC_TF) |
caf18f19 | 1615 | pin_mask |= (1 << 24); /* TF */ |
9cf6cf58 | 1616 | if (flags & ATMEL_SSC_TD) |
caf18f19 | 1617 | pin_mask |= (1 << 25); /* TD */ |
9cf6cf58 | 1618 | if (flags & ATMEL_SSC_RD) |
caf18f19 JM |
1619 | pin_mask |= (1 << 26); /* RD */ |
1620 | ||
1621 | if (pin_mask > 0) | |
1622 | select_peripheral(PIOA, pin_mask, PERIPH_A, 0); | |
1623 | ||
9cf6cf58 HCE |
1624 | break; |
1625 | case 1: | |
1626 | pdev = &ssc1_device; | |
1627 | if (flags & ATMEL_SSC_RF) | |
caf18f19 | 1628 | pin_mask |= (1 << 0); /* RF */ |
9cf6cf58 | 1629 | if (flags & ATMEL_SSC_RK) |
caf18f19 | 1630 | pin_mask |= (1 << 1); /* RK */ |
9cf6cf58 | 1631 | if (flags & ATMEL_SSC_TK) |
caf18f19 | 1632 | pin_mask |= (1 << 2); /* TK */ |
9cf6cf58 | 1633 | if (flags & ATMEL_SSC_TF) |
caf18f19 | 1634 | pin_mask |= (1 << 3); /* TF */ |
9cf6cf58 | 1635 | if (flags & ATMEL_SSC_TD) |
caf18f19 | 1636 | pin_mask |= (1 << 4); /* TD */ |
9cf6cf58 | 1637 | if (flags & ATMEL_SSC_RD) |
caf18f19 JM |
1638 | pin_mask |= (1 << 5); /* RD */ |
1639 | ||
1640 | if (pin_mask > 0) | |
1641 | select_peripheral(PIOA, pin_mask, PERIPH_B, 0); | |
1642 | ||
9cf6cf58 HCE |
1643 | break; |
1644 | case 2: | |
1645 | pdev = &ssc2_device; | |
1646 | if (flags & ATMEL_SSC_TD) | |
caf18f19 | 1647 | pin_mask |= (1 << 13); /* TD */ |
9cf6cf58 | 1648 | if (flags & ATMEL_SSC_RD) |
caf18f19 | 1649 | pin_mask |= (1 << 14); /* RD */ |
9cf6cf58 | 1650 | if (flags & ATMEL_SSC_TK) |
caf18f19 | 1651 | pin_mask |= (1 << 15); /* TK */ |
9cf6cf58 | 1652 | if (flags & ATMEL_SSC_TF) |
caf18f19 | 1653 | pin_mask |= (1 << 16); /* TF */ |
9cf6cf58 | 1654 | if (flags & ATMEL_SSC_RF) |
caf18f19 | 1655 | pin_mask |= (1 << 17); /* RF */ |
9cf6cf58 | 1656 | if (flags & ATMEL_SSC_RK) |
caf18f19 JM |
1657 | pin_mask |= (1 << 18); /* RK */ |
1658 | ||
1659 | if (pin_mask > 0) | |
1660 | select_peripheral(PIOB, pin_mask, PERIPH_A, 0); | |
1661 | ||
9cf6cf58 HCE |
1662 | break; |
1663 | default: | |
1664 | return NULL; | |
1665 | } | |
1666 | ||
1667 | platform_device_register(pdev); | |
1668 | return pdev; | |
1669 | } | |
1670 | ||
6fcf0615 HS |
1671 | /* -------------------------------------------------------------------- |
1672 | * USB Device Controller | |
1673 | * -------------------------------------------------------------------- */ | |
1674 | static struct resource usba0_resource[] __initdata = { | |
1675 | { | |
1676 | .start = 0xff300000, | |
1677 | .end = 0xff3fffff, | |
1678 | .flags = IORESOURCE_MEM, | |
1679 | }, { | |
1680 | .start = 0xfff03000, | |
1681 | .end = 0xfff033ff, | |
1682 | .flags = IORESOURCE_MEM, | |
1683 | }, | |
1684 | IRQ(31), | |
1685 | }; | |
1686 | static struct clk usba0_pclk = { | |
1687 | .name = "pclk", | |
1688 | .parent = &pbb_clk, | |
1689 | .mode = pbb_clk_mode, | |
1690 | .get_rate = pbb_clk_get_rate, | |
1691 | .index = 12, | |
1692 | }; | |
1693 | static struct clk usba0_hclk = { | |
1694 | .name = "hclk", | |
1695 | .parent = &hsb_clk, | |
1696 | .mode = hsb_clk_mode, | |
1697 | .get_rate = hsb_clk_get_rate, | |
1698 | .index = 6, | |
1699 | }; | |
1700 | ||
8d855317 SP |
1701 | #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ |
1702 | [idx] = { \ | |
1703 | .name = nam, \ | |
1704 | .index = idx, \ | |
1705 | .fifo_size = maxpkt, \ | |
1706 | .nr_banks = maxbk, \ | |
1707 | .can_dma = dma, \ | |
1708 | .can_isoc = isoc, \ | |
1709 | } | |
1710 | ||
1711 | static struct usba_ep_data at32_usba_ep[] __initdata = { | |
1712 | EP("ep0", 0, 64, 1, 0, 0), | |
1713 | EP("ep1", 1, 512, 2, 1, 1), | |
1714 | EP("ep2", 2, 512, 2, 1, 1), | |
1715 | EP("ep3-int", 3, 64, 3, 1, 0), | |
1716 | EP("ep4-int", 4, 64, 3, 1, 0), | |
1717 | EP("ep5", 5, 1024, 3, 1, 1), | |
1718 | EP("ep6", 6, 1024, 3, 1, 1), | |
1719 | }; | |
1720 | ||
1721 | #undef EP | |
1722 | ||
6fcf0615 HS |
1723 | struct platform_device *__init |
1724 | at32_add_device_usba(unsigned int id, struct usba_platform_data *data) | |
1725 | { | |
8d855317 SP |
1726 | /* |
1727 | * pdata doesn't have room for any endpoints, so we need to | |
1728 | * append room for the ones we need right after it. | |
1729 | */ | |
1730 | struct { | |
1731 | struct usba_platform_data pdata; | |
1732 | struct usba_ep_data ep[7]; | |
1733 | } usba_data; | |
6fcf0615 HS |
1734 | struct platform_device *pdev; |
1735 | ||
1736 | if (id != 0) | |
1737 | return NULL; | |
1738 | ||
1739 | pdev = platform_device_alloc("atmel_usba_udc", 0); | |
1740 | if (!pdev) | |
1741 | return NULL; | |
1742 | ||
1743 | if (platform_device_add_resources(pdev, usba0_resource, | |
1744 | ARRAY_SIZE(usba0_resource))) | |
1745 | goto out_free_pdev; | |
1746 | ||
8d855317 SP |
1747 | if (data) |
1748 | usba_data.pdata.vbus_pin = data->vbus_pin; | |
1749 | else | |
1750 | usba_data.pdata.vbus_pin = -EINVAL; | |
6fcf0615 | 1751 | |
8d855317 SP |
1752 | data = &usba_data.pdata; |
1753 | data->num_ep = ARRAY_SIZE(at32_usba_ep); | |
1754 | memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep)); | |
1755 | ||
1756 | if (platform_device_add_data(pdev, data, sizeof(usba_data))) | |
1757 | goto out_free_pdev; | |
1758 | ||
9477ab2b | 1759 | if (gpio_is_valid(data->vbus_pin)) |
8d855317 | 1760 | at32_select_gpio(data->vbus_pin, 0); |
6fcf0615 HS |
1761 | |
1762 | usba0_pclk.dev = &pdev->dev; | |
1763 | usba0_hclk.dev = &pdev->dev; | |
1764 | ||
1765 | platform_device_add(pdev); | |
1766 | ||
1767 | return pdev; | |
1768 | ||
1769 | out_free_pdev: | |
1770 | platform_device_put(pdev); | |
1771 | return NULL; | |
1772 | } | |
1773 | ||
48021bd9 | 1774 | /* -------------------------------------------------------------------- |
eaf5f925 | 1775 | * IDE / CompactFlash |
48021bd9 | 1776 | * -------------------------------------------------------------------- */ |
438ff3f3 | 1777 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001) |
eaf5f925 | 1778 | static struct resource at32_smc_cs4_resource[] __initdata = { |
48021bd9 KNG |
1779 | { |
1780 | .start = 0x04000000, | |
1781 | .end = 0x07ffffff, | |
1782 | .flags = IORESOURCE_MEM, | |
1783 | }, | |
1784 | IRQ(~0UL), /* Magic IRQ will be overridden */ | |
1785 | }; | |
eaf5f925 HS |
1786 | static struct resource at32_smc_cs5_resource[] __initdata = { |
1787 | { | |
1788 | .start = 0x20000000, | |
1789 | .end = 0x23ffffff, | |
1790 | .flags = IORESOURCE_MEM, | |
1791 | }, | |
1792 | IRQ(~0UL), /* Magic IRQ will be overridden */ | |
1793 | }; | |
48021bd9 | 1794 | |
eaf5f925 HS |
1795 | static int __init at32_init_ide_or_cf(struct platform_device *pdev, |
1796 | unsigned int cs, unsigned int extint) | |
48021bd9 | 1797 | { |
eaf5f925 | 1798 | static unsigned int extint_pin_map[4] __initdata = { |
caf18f19 JM |
1799 | (1 << 25), |
1800 | (1 << 26), | |
1801 | (1 << 27), | |
1802 | (1 << 28), | |
eaf5f925 HS |
1803 | }; |
1804 | static bool common_pins_initialized __initdata = false; | |
48021bd9 | 1805 | unsigned int extint_pin; |
eaf5f925 | 1806 | int ret; |
caf18f19 | 1807 | u32 pin_mask; |
48021bd9 | 1808 | |
eaf5f925 HS |
1809 | if (extint >= ARRAY_SIZE(extint_pin_map)) |
1810 | return -EINVAL; | |
1811 | extint_pin = extint_pin_map[extint]; | |
1812 | ||
1813 | switch (cs) { | |
1814 | case 4: | |
1815 | ret = platform_device_add_resources(pdev, | |
1816 | at32_smc_cs4_resource, | |
1817 | ARRAY_SIZE(at32_smc_cs4_resource)); | |
1818 | if (ret) | |
1819 | return ret; | |
1820 | ||
caf18f19 JM |
1821 | /* NCS4 -> OE_N */ |
1822 | select_peripheral(PIOE, (1 << 21), PERIPH_A, 0); | |
b47eb409 | 1823 | hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE); |
48021bd9 | 1824 | break; |
eaf5f925 HS |
1825 | case 5: |
1826 | ret = platform_device_add_resources(pdev, | |
1827 | at32_smc_cs5_resource, | |
1828 | ARRAY_SIZE(at32_smc_cs5_resource)); | |
1829 | if (ret) | |
1830 | return ret; | |
1831 | ||
caf18f19 JM |
1832 | /* NCS5 -> OE_N */ |
1833 | select_peripheral(PIOE, (1 << 22), PERIPH_A, 0); | |
b47eb409 | 1834 | hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE); |
48021bd9 KNG |
1835 | break; |
1836 | default: | |
eaf5f925 | 1837 | return -EINVAL; |
48021bd9 KNG |
1838 | } |
1839 | ||
eaf5f925 | 1840 | if (!common_pins_initialized) { |
caf18f19 JM |
1841 | pin_mask = (1 << 19); /* CFCE1 -> CS0_N */ |
1842 | pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */ | |
1843 | pin_mask |= (1 << 23); /* CFRNW -> DIR */ | |
1844 | pin_mask |= (1 << 24); /* NWAIT <- IORDY */ | |
1845 | ||
1846 | select_peripheral(PIOE, pin_mask, PERIPH_A, 0); | |
1847 | ||
eaf5f925 | 1848 | common_pins_initialized = true; |
48021bd9 KNG |
1849 | } |
1850 | ||
caf18f19 | 1851 | select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH); |
48021bd9 KNG |
1852 | |
1853 | pdev->resource[1].start = EIM_IRQ_BASE + extint; | |
1854 | pdev->resource[1].end = pdev->resource[1].start; | |
1855 | ||
eaf5f925 HS |
1856 | return 0; |
1857 | } | |
48021bd9 | 1858 | |
eaf5f925 HS |
1859 | struct platform_device *__init |
1860 | at32_add_device_ide(unsigned int id, unsigned int extint, | |
1861 | struct ide_platform_data *data) | |
1862 | { | |
1863 | struct platform_device *pdev; | |
1864 | ||
1865 | pdev = platform_device_alloc("at32_ide", id); | |
1866 | if (!pdev) | |
1867 | goto fail; | |
1868 | ||
1869 | if (platform_device_add_data(pdev, data, | |
1870 | sizeof(struct ide_platform_data))) | |
1871 | goto fail; | |
1872 | ||
1873 | if (at32_init_ide_or_cf(pdev, data->cs, extint)) | |
1874 | goto fail; | |
1875 | ||
1876 | platform_device_add(pdev); | |
1877 | return pdev; | |
1878 | ||
1879 | fail: | |
1880 | platform_device_put(pdev); | |
1881 | return NULL; | |
1882 | } | |
1883 | ||
1884 | struct platform_device *__init | |
1885 | at32_add_device_cf(unsigned int id, unsigned int extint, | |
1886 | struct cf_platform_data *data) | |
1887 | { | |
1888 | struct platform_device *pdev; | |
1889 | ||
1890 | pdev = platform_device_alloc("at32_cf", id); | |
1891 | if (!pdev) | |
1892 | goto fail; | |
48021bd9 | 1893 | |
eaf5f925 HS |
1894 | if (platform_device_add_data(pdev, data, |
1895 | sizeof(struct cf_platform_data))) | |
1896 | goto fail; | |
1897 | ||
1898 | if (at32_init_ide_or_cf(pdev, data->cs, extint)) | |
1899 | goto fail; | |
1900 | ||
3c26e170 | 1901 | if (gpio_is_valid(data->detect_pin)) |
eaf5f925 | 1902 | at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH); |
3c26e170 | 1903 | if (gpio_is_valid(data->reset_pin)) |
eaf5f925 | 1904 | at32_select_gpio(data->reset_pin, 0); |
3c26e170 | 1905 | if (gpio_is_valid(data->vcc_pin)) |
eaf5f925 HS |
1906 | at32_select_gpio(data->vcc_pin, 0); |
1907 | /* READY is used as extint, so we can't select it as gpio */ | |
1908 | ||
1909 | platform_device_add(pdev); | |
48021bd9 | 1910 | return pdev; |
eaf5f925 HS |
1911 | |
1912 | fail: | |
1913 | platform_device_put(pdev); | |
1914 | return NULL; | |
48021bd9 | 1915 | } |
438ff3f3 | 1916 | #endif |
48021bd9 | 1917 | |
62090a08 HS |
1918 | /* -------------------------------------------------------------------- |
1919 | * NAND Flash / SmartMedia | |
1920 | * -------------------------------------------------------------------- */ | |
1921 | static struct resource smc_cs3_resource[] __initdata = { | |
1922 | { | |
1923 | .start = 0x0c000000, | |
1924 | .end = 0x0fffffff, | |
1925 | .flags = IORESOURCE_MEM, | |
1926 | }, { | |
1927 | .start = 0xfff03c00, | |
1928 | .end = 0xfff03fff, | |
1929 | .flags = IORESOURCE_MEM, | |
1930 | }, | |
1931 | }; | |
1932 | ||
1933 | struct platform_device *__init | |
1934 | at32_add_device_nand(unsigned int id, struct atmel_nand_data *data) | |
1935 | { | |
1936 | struct platform_device *pdev; | |
1937 | ||
1938 | if (id != 0 || !data) | |
1939 | return NULL; | |
1940 | ||
1941 | pdev = platform_device_alloc("atmel_nand", id); | |
1942 | if (!pdev) | |
1943 | goto fail; | |
1944 | ||
1945 | if (platform_device_add_resources(pdev, smc_cs3_resource, | |
1946 | ARRAY_SIZE(smc_cs3_resource))) | |
1947 | goto fail; | |
1948 | ||
1949 | if (platform_device_add_data(pdev, data, | |
1950 | sizeof(struct atmel_nand_data))) | |
1951 | goto fail; | |
1952 | ||
b47eb409 | 1953 | hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE); |
62090a08 HS |
1954 | if (data->enable_pin) |
1955 | at32_select_gpio(data->enable_pin, | |
1956 | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH); | |
1957 | if (data->rdy_pin) | |
1958 | at32_select_gpio(data->rdy_pin, 0); | |
1959 | if (data->det_pin) | |
1960 | at32_select_gpio(data->det_pin, 0); | |
1961 | ||
1962 | platform_device_add(pdev); | |
1963 | return pdev; | |
1964 | ||
1965 | fail: | |
1966 | platform_device_put(pdev); | |
1967 | return NULL; | |
1968 | } | |
1969 | ||
2042c1c4 HS |
1970 | /* -------------------------------------------------------------------- |
1971 | * AC97C | |
1972 | * -------------------------------------------------------------------- */ | |
1973 | static struct resource atmel_ac97c0_resource[] __initdata = { | |
1974 | PBMEM(0xfff02800), | |
1975 | IRQ(29), | |
1976 | }; | |
1977 | static struct clk atmel_ac97c0_pclk = { | |
1978 | .name = "pclk", | |
1979 | .parent = &pbb_clk, | |
1980 | .mode = pbb_clk_mode, | |
1981 | .get_rate = pbb_clk_get_rate, | |
1982 | .index = 10, | |
1983 | }; | |
1984 | ||
218df4a2 | 1985 | struct platform_device *__init |
2f47c8c5 HCE |
1986 | at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data, |
1987 | unsigned int flags) | |
2042c1c4 | 1988 | { |
2f47c8c5 HCE |
1989 | struct platform_device *pdev; |
1990 | struct dw_dma_slave *rx_dws; | |
1991 | struct dw_dma_slave *tx_dws; | |
1992 | struct ac97c_platform_data _data; | |
1993 | u32 pin_mask; | |
2042c1c4 HS |
1994 | |
1995 | if (id != 0) | |
1996 | return NULL; | |
1997 | ||
1998 | pdev = platform_device_alloc("atmel_ac97c", id); | |
1999 | if (!pdev) | |
2000 | return NULL; | |
2001 | ||
2002 | if (platform_device_add_resources(pdev, atmel_ac97c0_resource, | |
2003 | ARRAY_SIZE(atmel_ac97c0_resource))) | |
2f47c8c5 | 2004 | goto out_free_resources; |
218df4a2 HCE |
2005 | |
2006 | if (!data) { | |
2007 | data = &_data; | |
2008 | memset(data, 0, sizeof(struct ac97c_platform_data)); | |
2f47c8c5 HCE |
2009 | data->reset_pin = -ENODEV; |
2010 | } | |
2011 | ||
2012 | rx_dws = &data->rx_dws; | |
2013 | tx_dws = &data->tx_dws; | |
2014 | ||
2015 | /* Check if DMA slave interface for capture should be configured. */ | |
2016 | if (flags & AC97C_CAPTURE) { | |
2017 | rx_dws->dma_dev = &dw_dmac0_device.dev; | |
2018 | rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT; | |
2019 | rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3); | |
2020 | rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); | |
218df4a2 HCE |
2021 | } |
2022 | ||
2f47c8c5 HCE |
2023 | /* Check if DMA slave interface for playback should be configured. */ |
2024 | if (flags & AC97C_PLAYBACK) { | |
2025 | tx_dws->dma_dev = &dw_dmac0_device.dev; | |
2026 | tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT; | |
2027 | tx_dws->cfg_hi = DWC_CFGH_DST_PER(4); | |
2028 | tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); | |
2029 | } | |
2042c1c4 | 2030 | |
218df4a2 HCE |
2031 | if (platform_device_add_data(pdev, data, |
2032 | sizeof(struct ac97c_platform_data))) | |
2f47c8c5 | 2033 | goto out_free_resources; |
218df4a2 | 2034 | |
2f47c8c5 HCE |
2035 | /* SDO | SYNC | SCLK | SDI */ |
2036 | pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23); | |
caf18f19 JM |
2037 | |
2038 | select_peripheral(PIOB, pin_mask, PERIPH_B, 0); | |
218df4a2 | 2039 | |
2f47c8c5 HCE |
2040 | if (gpio_is_valid(data->reset_pin)) |
2041 | at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT | |
2042 | | AT32_GPIOF_HIGH); | |
2042c1c4 HS |
2043 | |
2044 | atmel_ac97c0_pclk.dev = &pdev->dev; | |
2045 | ||
2046 | platform_device_add(pdev); | |
2047 | return pdev; | |
2048 | ||
2f47c8c5 | 2049 | out_free_resources: |
2042c1c4 HS |
2050 | platform_device_put(pdev); |
2051 | return NULL; | |
2052 | } | |
2053 | ||
2054 | /* -------------------------------------------------------------------- | |
2055 | * ABDAC | |
2056 | * -------------------------------------------------------------------- */ | |
2057 | static struct resource abdac0_resource[] __initdata = { | |
2058 | PBMEM(0xfff02000), | |
2059 | IRQ(27), | |
2060 | }; | |
2061 | static struct clk abdac0_pclk = { | |
2062 | .name = "pclk", | |
2063 | .parent = &pbb_clk, | |
2064 | .mode = pbb_clk_mode, | |
2065 | .get_rate = pbb_clk_get_rate, | |
2066 | .index = 8, | |
2067 | }; | |
2068 | static struct clk abdac0_sample_clk = { | |
2069 | .name = "sample_clk", | |
2070 | .mode = genclk_mode, | |
2071 | .get_rate = genclk_get_rate, | |
2072 | .set_rate = genclk_set_rate, | |
2073 | .set_parent = genclk_set_parent, | |
2074 | .index = 6, | |
2075 | }; | |
2076 | ||
6b0c9351 HCE |
2077 | struct platform_device *__init |
2078 | at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data) | |
2042c1c4 | 2079 | { |
6b0c9351 HCE |
2080 | struct platform_device *pdev; |
2081 | struct dw_dma_slave *dws; | |
2082 | u32 pin_mask; | |
2042c1c4 | 2083 | |
6b0c9351 | 2084 | if (id != 0 || !data) |
2042c1c4 HS |
2085 | return NULL; |
2086 | ||
6b0c9351 | 2087 | pdev = platform_device_alloc("atmel_abdac", id); |
2042c1c4 HS |
2088 | if (!pdev) |
2089 | return NULL; | |
2090 | ||
2091 | if (platform_device_add_resources(pdev, abdac0_resource, | |
2092 | ARRAY_SIZE(abdac0_resource))) | |
6b0c9351 HCE |
2093 | goto out_free_resources; |
2094 | ||
2095 | dws = &data->dws; | |
2096 | ||
2097 | dws->dma_dev = &dw_dmac0_device.dev; | |
2098 | dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT; | |
2099 | dws->cfg_hi = DWC_CFGH_DST_PER(2); | |
2100 | dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); | |
2101 | ||
2102 | if (platform_device_add_data(pdev, data, | |
2103 | sizeof(struct atmel_abdac_pdata))) | |
2104 | goto out_free_resources; | |
2042c1c4 | 2105 | |
caf18f19 JM |
2106 | pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */ |
2107 | pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */ | |
2108 | ||
2109 | select_peripheral(PIOB, pin_mask, PERIPH_A, 0); | |
2042c1c4 HS |
2110 | |
2111 | abdac0_pclk.dev = &pdev->dev; | |
2112 | abdac0_sample_clk.dev = &pdev->dev; | |
2113 | ||
2114 | platform_device_add(pdev); | |
2115 | return pdev; | |
2116 | ||
6b0c9351 | 2117 | out_free_resources: |
2042c1c4 HS |
2118 | platform_device_put(pdev); |
2119 | return NULL; | |
2120 | } | |
2121 | ||
7a5fe238 HS |
2122 | /* -------------------------------------------------------------------- |
2123 | * GCLK | |
2124 | * -------------------------------------------------------------------- */ | |
2125 | static struct clk gclk0 = { | |
2126 | .name = "gclk0", | |
2127 | .mode = genclk_mode, | |
2128 | .get_rate = genclk_get_rate, | |
2129 | .set_rate = genclk_set_rate, | |
2130 | .set_parent = genclk_set_parent, | |
2131 | .index = 0, | |
2132 | }; | |
2133 | static struct clk gclk1 = { | |
2134 | .name = "gclk1", | |
2135 | .mode = genclk_mode, | |
2136 | .get_rate = genclk_get_rate, | |
2137 | .set_rate = genclk_set_rate, | |
2138 | .set_parent = genclk_set_parent, | |
2139 | .index = 1, | |
2140 | }; | |
2141 | static struct clk gclk2 = { | |
2142 | .name = "gclk2", | |
2143 | .mode = genclk_mode, | |
2144 | .get_rate = genclk_get_rate, | |
2145 | .set_rate = genclk_set_rate, | |
2146 | .set_parent = genclk_set_parent, | |
2147 | .index = 2, | |
2148 | }; | |
2149 | static struct clk gclk3 = { | |
2150 | .name = "gclk3", | |
2151 | .mode = genclk_mode, | |
2152 | .get_rate = genclk_get_rate, | |
2153 | .set_rate = genclk_set_rate, | |
2154 | .set_parent = genclk_set_parent, | |
2155 | .index = 3, | |
2156 | }; | |
2157 | static struct clk gclk4 = { | |
2158 | .name = "gclk4", | |
2159 | .mode = genclk_mode, | |
2160 | .get_rate = genclk_get_rate, | |
2161 | .set_rate = genclk_set_rate, | |
2162 | .set_parent = genclk_set_parent, | |
2163 | .index = 4, | |
2164 | }; | |
2165 | ||
300bb762 | 2166 | static __initdata struct clk *init_clocks[] = { |
5f97f7f9 HS |
2167 | &osc32k, |
2168 | &osc0, | |
2169 | &osc1, | |
2170 | &pll0, | |
2171 | &pll1, | |
2172 | &cpu_clk, | |
2173 | &hsb_clk, | |
2174 | &pba_clk, | |
2175 | &pbb_clk, | |
7a5b8059 | 2176 | &at32_pm_pclk, |
5f97f7f9 | 2177 | &at32_intc0_pclk, |
b47eb409 | 2178 | &at32_hmatrix_clk, |
5f97f7f9 HS |
2179 | &ebi_clk, |
2180 | &hramc_clk, | |
7951f188 | 2181 | &sdramc_clk, |
bc157b75 HS |
2182 | &smc0_pclk, |
2183 | &smc0_mck, | |
5f97f7f9 HS |
2184 | &pdc_hclk, |
2185 | &pdc_pclk, | |
3bfb1d20 | 2186 | &dw_dmac0_hclk, |
5f97f7f9 HS |
2187 | &pico_clk, |
2188 | &pio0_mck, | |
2189 | &pio1_mck, | |
2190 | &pio2_mck, | |
2191 | &pio3_mck, | |
7f9f4678 | 2192 | &pio4_mck, |
e723ff66 DB |
2193 | &at32_tcb0_t0_clk, |
2194 | &at32_tcb1_t0_clk, | |
d86d314f HCE |
2195 | &atmel_psif0_pclk, |
2196 | &atmel_psif1_pclk, | |
1e8ea802 HS |
2197 | &atmel_usart0_usart, |
2198 | &atmel_usart1_usart, | |
2199 | &atmel_usart2_usart, | |
2200 | &atmel_usart3_usart, | |
9a1e8eb1 | 2201 | &atmel_pwm0_mck, |
438ff3f3 | 2202 | #if defined(CONFIG_CPU_AT32AP7000) |
5f97f7f9 HS |
2203 | &macb0_hclk, |
2204 | &macb0_pclk, | |
cfcb3a89 HS |
2205 | &macb1_hclk, |
2206 | &macb1_pclk, | |
438ff3f3 | 2207 | #endif |
3d60ee1b HS |
2208 | &atmel_spi0_spi_clk, |
2209 | &atmel_spi1_spi_clk, | |
2042c1c4 HS |
2210 | &atmel_twi0_pclk, |
2211 | &atmel_mci0_pclk, | |
438ff3f3 | 2212 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af HS |
2213 | &atmel_lcdfb0_hck1, |
2214 | &atmel_lcdfb0_pixclk, | |
438ff3f3 | 2215 | #endif |
9cf6cf58 HCE |
2216 | &ssc0_pclk, |
2217 | &ssc1_pclk, | |
2218 | &ssc2_pclk, | |
6fcf0615 HS |
2219 | &usba0_hclk, |
2220 | &usba0_pclk, | |
2042c1c4 HS |
2221 | &atmel_ac97c0_pclk, |
2222 | &abdac0_pclk, | |
2223 | &abdac0_sample_clk, | |
7a5fe238 HS |
2224 | &gclk0, |
2225 | &gclk1, | |
2226 | &gclk2, | |
2227 | &gclk3, | |
2228 | &gclk4, | |
5f97f7f9 | 2229 | }; |
5f97f7f9 | 2230 | |
65033ed7 | 2231 | void __init setup_platform(void) |
5f97f7f9 | 2232 | { |
5f97f7f9 HS |
2233 | u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0; |
2234 | int i; | |
2235 | ||
9e58e185 | 2236 | if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) { |
5f97f7f9 | 2237 | main_clock = &pll0; |
9e58e185 HCE |
2238 | cpu_clk.parent = &pll0; |
2239 | } else { | |
5f97f7f9 | 2240 | main_clock = &osc0; |
9e58e185 HCE |
2241 | cpu_clk.parent = &osc0; |
2242 | } | |
5f97f7f9 | 2243 | |
7a5b8059 | 2244 | if (pm_readl(PLL0) & PM_BIT(PLLOSC)) |
5f97f7f9 | 2245 | pll0.parent = &osc1; |
7a5b8059 | 2246 | if (pm_readl(PLL1) & PM_BIT(PLLOSC)) |
5f97f7f9 HS |
2247 | pll1.parent = &osc1; |
2248 | ||
7a5fe238 HS |
2249 | genclk_init_parent(&gclk0); |
2250 | genclk_init_parent(&gclk1); | |
2251 | genclk_init_parent(&gclk2); | |
2252 | genclk_init_parent(&gclk3); | |
2253 | genclk_init_parent(&gclk4); | |
438ff3f3 | 2254 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af | 2255 | genclk_init_parent(&atmel_lcdfb0_pixclk); |
438ff3f3 | 2256 | #endif |
2042c1c4 | 2257 | genclk_init_parent(&abdac0_sample_clk); |
7a5fe238 | 2258 | |
5f97f7f9 | 2259 | /* |
300bb762 AR |
2260 | * Build initial dynamic clock list by registering all clocks |
2261 | * from the array. | |
2262 | * At the same time, turn on all clocks that have at least one | |
2263 | * user already, and turn off everything else. We only do this | |
2264 | * for module clocks, and even though it isn't particularly | |
2265 | * pretty to check the address of the mode function, it should | |
2266 | * do the trick... | |
5f97f7f9 | 2267 | */ |
300bb762 AR |
2268 | for (i = 0; i < ARRAY_SIZE(init_clocks); i++) { |
2269 | struct clk *clk = init_clocks[i]; | |
2270 | ||
2271 | /* first, register clock */ | |
2272 | at32_clk_register(clk); | |
5f97f7f9 | 2273 | |
188ff65d HS |
2274 | if (clk->users == 0) |
2275 | continue; | |
2276 | ||
5f97f7f9 HS |
2277 | if (clk->mode == &cpu_clk_mode) |
2278 | cpu_mask |= 1 << clk->index; | |
2279 | else if (clk->mode == &hsb_clk_mode) | |
2280 | hsb_mask |= 1 << clk->index; | |
2281 | else if (clk->mode == &pba_clk_mode) | |
2282 | pba_mask |= 1 << clk->index; | |
2283 | else if (clk->mode == &pbb_clk_mode) | |
2284 | pbb_mask |= 1 << clk->index; | |
2285 | } | |
2286 | ||
7a5b8059 HS |
2287 | pm_writel(CPU_MASK, cpu_mask); |
2288 | pm_writel(HSB_MASK, hsb_mask); | |
2289 | pm_writel(PBA_MASK, pba_mask); | |
2290 | pm_writel(PBB_MASK, pbb_mask); | |
65033ed7 HS |
2291 | |
2292 | /* Initialize the port muxes */ | |
2293 | at32_init_pio(&pio0_device); | |
2294 | at32_init_pio(&pio1_device); | |
2295 | at32_init_pio(&pio2_device); | |
2296 | at32_init_pio(&pio3_device); | |
2297 | at32_init_pio(&pio4_device); | |
5f97f7f9 | 2298 | } |
b83d6ee1 HS |
2299 | |
2300 | struct gen_pool *sram_pool; | |
2301 | ||
2302 | static int __init sram_init(void) | |
2303 | { | |
2304 | struct gen_pool *pool; | |
2305 | ||
2306 | /* 1KiB granularity */ | |
2307 | pool = gen_pool_create(10, -1); | |
2308 | if (!pool) | |
2309 | goto fail; | |
2310 | ||
2311 | if (gen_pool_add(pool, 0x24000000, 0x8000, -1)) | |
2312 | goto err_pool_add; | |
2313 | ||
2314 | sram_pool = pool; | |
2315 | return 0; | |
2316 | ||
2317 | err_pool_add: | |
2318 | gen_pool_destroy(pool); | |
2319 | fail: | |
2320 | pr_err("Failed to create SRAM pool\n"); | |
2321 | return -ENOMEM; | |
2322 | } | |
2323 | core_initcall(sram_init); |