Commit | Line | Data |
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5f97f7f9 HS |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | #include <linux/clk.h> | |
35bf50cc | 9 | #include <linux/delay.h> |
d0a2b7af | 10 | #include <linux/fb.h> |
5f97f7f9 HS |
11 | #include <linux/init.h> |
12 | #include <linux/platform_device.h> | |
6b84bbfc | 13 | #include <linux/dma-mapping.h> |
41d8ca45 | 14 | #include <linux/spi/spi.h> |
8d855317 | 15 | #include <linux/usb/atmel_usba_udc.h> |
5f97f7f9 HS |
16 | |
17 | #include <asm/io.h> | |
e7ba176b | 18 | #include <asm/irq.h> |
5f97f7f9 | 19 | |
438ff3f3 | 20 | #include <asm/arch/at32ap700x.h> |
5f97f7f9 HS |
21 | #include <asm/arch/board.h> |
22 | #include <asm/arch/portmux.h> | |
5f97f7f9 | 23 | |
d0a2b7af HS |
24 | #include <video/atmel_lcdc.h> |
25 | ||
5f97f7f9 | 26 | #include "clock.h" |
9c8f8e75 | 27 | #include "hmatrix.h" |
5f97f7f9 | 28 | #include "pio.h" |
7a5b8059 HS |
29 | #include "pm.h" |
30 | ||
5f97f7f9 HS |
31 | |
32 | #define PBMEM(base) \ | |
33 | { \ | |
34 | .start = base, \ | |
35 | .end = base + 0x3ff, \ | |
36 | .flags = IORESOURCE_MEM, \ | |
37 | } | |
38 | #define IRQ(num) \ | |
39 | { \ | |
40 | .start = num, \ | |
41 | .end = num, \ | |
42 | .flags = IORESOURCE_IRQ, \ | |
43 | } | |
44 | #define NAMED_IRQ(num, _name) \ | |
45 | { \ | |
46 | .start = num, \ | |
47 | .end = num, \ | |
48 | .name = _name, \ | |
49 | .flags = IORESOURCE_IRQ, \ | |
50 | } | |
51 | ||
6b84bbfc DB |
52 | /* REVISIT these assume *every* device supports DMA, but several |
53 | * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more. | |
54 | */ | |
5f97f7f9 | 55 | #define DEFINE_DEV(_name, _id) \ |
6b84bbfc | 56 | static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \ |
5f97f7f9 HS |
57 | static struct platform_device _name##_id##_device = { \ |
58 | .name = #_name, \ | |
59 | .id = _id, \ | |
6b84bbfc DB |
60 | .dev = { \ |
61 | .dma_mask = &_name##_id##_dma_mask, \ | |
62 | .coherent_dma_mask = DMA_32BIT_MASK, \ | |
63 | }, \ | |
5f97f7f9 HS |
64 | .resource = _name##_id##_resource, \ |
65 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
66 | } | |
67 | #define DEFINE_DEV_DATA(_name, _id) \ | |
6b84bbfc | 68 | static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \ |
5f97f7f9 HS |
69 | static struct platform_device _name##_id##_device = { \ |
70 | .name = #_name, \ | |
71 | .id = _id, \ | |
72 | .dev = { \ | |
6b84bbfc | 73 | .dma_mask = &_name##_id##_dma_mask, \ |
5f97f7f9 | 74 | .platform_data = &_name##_id##_data, \ |
6b84bbfc | 75 | .coherent_dma_mask = DMA_32BIT_MASK, \ |
5f97f7f9 HS |
76 | }, \ |
77 | .resource = _name##_id##_resource, \ | |
78 | .num_resources = ARRAY_SIZE(_name##_id##_resource), \ | |
79 | } | |
80 | ||
c3e2a79c HS |
81 | #define select_peripheral(pin, periph, flags) \ |
82 | at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags) | |
83 | ||
5f97f7f9 HS |
84 | #define DEV_CLK(_name, devname, bus, _index) \ |
85 | static struct clk devname##_##_name = { \ | |
86 | .name = #_name, \ | |
87 | .dev = &devname##_device.dev, \ | |
88 | .parent = &bus##_clk, \ | |
89 | .mode = bus##_clk_mode, \ | |
90 | .get_rate = bus##_clk_get_rate, \ | |
91 | .index = _index, \ | |
92 | } | |
93 | ||
7a5b8059 HS |
94 | static DEFINE_SPINLOCK(pm_lock); |
95 | ||
35bf50cc HCE |
96 | static struct clk osc0; |
97 | static struct clk osc1; | |
98 | ||
5f97f7f9 HS |
99 | static unsigned long osc_get_rate(struct clk *clk) |
100 | { | |
60ed7951 | 101 | return at32_board_osc_rates[clk->index]; |
5f97f7f9 HS |
102 | } |
103 | ||
104 | static unsigned long pll_get_rate(struct clk *clk, unsigned long control) | |
105 | { | |
106 | unsigned long div, mul, rate; | |
107 | ||
7a5b8059 HS |
108 | div = PM_BFEXT(PLLDIV, control) + 1; |
109 | mul = PM_BFEXT(PLLMUL, control) + 1; | |
5f97f7f9 HS |
110 | |
111 | rate = clk->parent->get_rate(clk->parent); | |
112 | rate = (rate + div / 2) / div; | |
113 | rate *= mul; | |
114 | ||
115 | return rate; | |
116 | } | |
117 | ||
35bf50cc HCE |
118 | static long pll_set_rate(struct clk *clk, unsigned long rate, |
119 | u32 *pll_ctrl) | |
120 | { | |
121 | unsigned long mul; | |
122 | unsigned long mul_best_fit = 0; | |
123 | unsigned long div; | |
124 | unsigned long div_min; | |
125 | unsigned long div_max; | |
126 | unsigned long div_best_fit = 0; | |
127 | unsigned long base; | |
128 | unsigned long pll_in; | |
129 | unsigned long actual = 0; | |
130 | unsigned long rate_error; | |
131 | unsigned long rate_error_prev = ~0UL; | |
132 | u32 ctrl; | |
133 | ||
134 | /* Rate must be between 80 MHz and 200 Mhz. */ | |
135 | if (rate < 80000000UL || rate > 200000000UL) | |
136 | return -EINVAL; | |
137 | ||
138 | ctrl = PM_BF(PLLOPT, 4); | |
139 | base = clk->parent->get_rate(clk->parent); | |
140 | ||
141 | /* PLL input frequency must be between 6 MHz and 32 MHz. */ | |
142 | div_min = DIV_ROUND_UP(base, 32000000UL); | |
143 | div_max = base / 6000000UL; | |
144 | ||
145 | if (div_max < div_min) | |
146 | return -EINVAL; | |
147 | ||
148 | for (div = div_min; div <= div_max; div++) { | |
149 | pll_in = (base + div / 2) / div; | |
150 | mul = (rate + pll_in / 2) / pll_in; | |
151 | ||
152 | if (mul == 0) | |
153 | continue; | |
154 | ||
155 | actual = pll_in * mul; | |
156 | rate_error = abs(actual - rate); | |
157 | ||
158 | if (rate_error < rate_error_prev) { | |
159 | mul_best_fit = mul; | |
160 | div_best_fit = div; | |
161 | rate_error_prev = rate_error; | |
162 | } | |
163 | ||
164 | if (rate_error == 0) | |
165 | break; | |
166 | } | |
167 | ||
168 | if (div_best_fit == 0) | |
169 | return -EINVAL; | |
170 | ||
171 | ctrl |= PM_BF(PLLMUL, mul_best_fit - 1); | |
172 | ctrl |= PM_BF(PLLDIV, div_best_fit - 1); | |
173 | ctrl |= PM_BF(PLLCOUNT, 16); | |
174 | ||
175 | if (clk->parent == &osc1) | |
176 | ctrl |= PM_BIT(PLLOSC); | |
177 | ||
178 | *pll_ctrl = ctrl; | |
179 | ||
180 | return actual; | |
181 | } | |
182 | ||
5f97f7f9 HS |
183 | static unsigned long pll0_get_rate(struct clk *clk) |
184 | { | |
185 | u32 control; | |
186 | ||
7a5b8059 | 187 | control = pm_readl(PLL0); |
5f97f7f9 HS |
188 | |
189 | return pll_get_rate(clk, control); | |
190 | } | |
191 | ||
35bf50cc HCE |
192 | static void pll1_mode(struct clk *clk, int enabled) |
193 | { | |
194 | unsigned long timeout; | |
195 | u32 status; | |
196 | u32 ctrl; | |
197 | ||
198 | ctrl = pm_readl(PLL1); | |
199 | ||
200 | if (enabled) { | |
201 | if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) { | |
202 | pr_debug("clk %s: failed to enable, rate not set\n", | |
203 | clk->name); | |
204 | return; | |
205 | } | |
206 | ||
207 | ctrl |= PM_BIT(PLLEN); | |
208 | pm_writel(PLL1, ctrl); | |
209 | ||
210 | /* Wait for PLL lock. */ | |
211 | for (timeout = 10000; timeout; timeout--) { | |
212 | status = pm_readl(ISR); | |
213 | if (status & PM_BIT(LOCK1)) | |
214 | break; | |
215 | udelay(10); | |
216 | } | |
217 | ||
218 | if (!(status & PM_BIT(LOCK1))) | |
219 | printk(KERN_ERR "clk %s: timeout waiting for lock\n", | |
220 | clk->name); | |
221 | } else { | |
222 | ctrl &= ~PM_BIT(PLLEN); | |
223 | pm_writel(PLL1, ctrl); | |
224 | } | |
225 | } | |
226 | ||
5f97f7f9 HS |
227 | static unsigned long pll1_get_rate(struct clk *clk) |
228 | { | |
229 | u32 control; | |
230 | ||
7a5b8059 | 231 | control = pm_readl(PLL1); |
5f97f7f9 HS |
232 | |
233 | return pll_get_rate(clk, control); | |
234 | } | |
235 | ||
35bf50cc HCE |
236 | static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply) |
237 | { | |
238 | u32 ctrl = 0; | |
239 | unsigned long actual_rate; | |
240 | ||
241 | actual_rate = pll_set_rate(clk, rate, &ctrl); | |
242 | ||
243 | if (apply) { | |
244 | if (actual_rate != rate) | |
245 | return -EINVAL; | |
246 | if (clk->users > 0) | |
247 | return -EBUSY; | |
248 | pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n", | |
249 | clk->name, rate, actual_rate); | |
250 | pm_writel(PLL1, ctrl); | |
251 | } | |
252 | ||
253 | return actual_rate; | |
254 | } | |
255 | ||
256 | static int pll1_set_parent(struct clk *clk, struct clk *parent) | |
257 | { | |
258 | u32 ctrl; | |
259 | ||
260 | if (clk->users > 0) | |
261 | return -EBUSY; | |
262 | ||
263 | ctrl = pm_readl(PLL1); | |
264 | WARN_ON(ctrl & PM_BIT(PLLEN)); | |
265 | ||
266 | if (parent == &osc0) | |
267 | ctrl &= ~PM_BIT(PLLOSC); | |
268 | else if (parent == &osc1) | |
269 | ctrl |= PM_BIT(PLLOSC); | |
270 | else | |
271 | return -EINVAL; | |
272 | ||
273 | pm_writel(PLL1, ctrl); | |
274 | clk->parent = parent; | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
5f97f7f9 HS |
279 | /* |
280 | * The AT32AP7000 has five primary clock sources: One 32kHz | |
281 | * oscillator, two crystal oscillators and two PLLs. | |
282 | */ | |
283 | static struct clk osc32k = { | |
284 | .name = "osc32k", | |
285 | .get_rate = osc_get_rate, | |
286 | .users = 1, | |
287 | .index = 0, | |
288 | }; | |
289 | static struct clk osc0 = { | |
290 | .name = "osc0", | |
291 | .get_rate = osc_get_rate, | |
292 | .users = 1, | |
293 | .index = 1, | |
294 | }; | |
295 | static struct clk osc1 = { | |
296 | .name = "osc1", | |
297 | .get_rate = osc_get_rate, | |
298 | .index = 2, | |
299 | }; | |
300 | static struct clk pll0 = { | |
301 | .name = "pll0", | |
302 | .get_rate = pll0_get_rate, | |
303 | .parent = &osc0, | |
304 | }; | |
305 | static struct clk pll1 = { | |
306 | .name = "pll1", | |
35bf50cc | 307 | .mode = pll1_mode, |
5f97f7f9 | 308 | .get_rate = pll1_get_rate, |
35bf50cc HCE |
309 | .set_rate = pll1_set_rate, |
310 | .set_parent = pll1_set_parent, | |
5f97f7f9 HS |
311 | .parent = &osc0, |
312 | }; | |
313 | ||
314 | /* | |
315 | * The main clock can be either osc0 or pll0. The boot loader may | |
316 | * have chosen one for us, so we don't really know which one until we | |
317 | * have a look at the SM. | |
318 | */ | |
319 | static struct clk *main_clock; | |
320 | ||
321 | /* | |
322 | * Synchronous clocks are generated from the main clock. The clocks | |
323 | * must satisfy the constraint | |
324 | * fCPU >= fHSB >= fPB | |
325 | * i.e. each clock must not be faster than its parent. | |
326 | */ | |
327 | static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift) | |
328 | { | |
329 | return main_clock->get_rate(main_clock) >> shift; | |
330 | }; | |
331 | ||
332 | static void cpu_clk_mode(struct clk *clk, int enabled) | |
333 | { | |
5f97f7f9 HS |
334 | unsigned long flags; |
335 | u32 mask; | |
336 | ||
7a5b8059 HS |
337 | spin_lock_irqsave(&pm_lock, flags); |
338 | mask = pm_readl(CPU_MASK); | |
5f97f7f9 HS |
339 | if (enabled) |
340 | mask |= 1 << clk->index; | |
341 | else | |
342 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
343 | pm_writel(CPU_MASK, mask); |
344 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
345 | } |
346 | ||
347 | static unsigned long cpu_clk_get_rate(struct clk *clk) | |
348 | { | |
349 | unsigned long cksel, shift = 0; | |
350 | ||
7a5b8059 HS |
351 | cksel = pm_readl(CKSEL); |
352 | if (cksel & PM_BIT(CPUDIV)) | |
353 | shift = PM_BFEXT(CPUSEL, cksel) + 1; | |
5f97f7f9 HS |
354 | |
355 | return bus_clk_get_rate(clk, shift); | |
356 | } | |
357 | ||
9e58e185 HCE |
358 | static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply) |
359 | { | |
360 | u32 control; | |
361 | unsigned long parent_rate, child_div, actual_rate, div; | |
362 | ||
363 | parent_rate = clk->parent->get_rate(clk->parent); | |
364 | control = pm_readl(CKSEL); | |
365 | ||
366 | if (control & PM_BIT(HSBDIV)) | |
367 | child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1); | |
368 | else | |
369 | child_div = 1; | |
370 | ||
371 | if (rate > 3 * (parent_rate / 4) || child_div == 1) { | |
372 | actual_rate = parent_rate; | |
373 | control &= ~PM_BIT(CPUDIV); | |
374 | } else { | |
375 | unsigned int cpusel; | |
376 | div = (parent_rate + rate / 2) / rate; | |
377 | if (div > child_div) | |
378 | div = child_div; | |
379 | cpusel = (div > 1) ? (fls(div) - 2) : 0; | |
380 | control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control); | |
381 | actual_rate = parent_rate / (1 << (cpusel + 1)); | |
382 | } | |
383 | ||
384 | pr_debug("clk %s: new rate %lu (actual rate %lu)\n", | |
385 | clk->name, rate, actual_rate); | |
386 | ||
387 | if (apply) | |
388 | pm_writel(CKSEL, control); | |
389 | ||
390 | return actual_rate; | |
391 | } | |
392 | ||
5f97f7f9 HS |
393 | static void hsb_clk_mode(struct clk *clk, int enabled) |
394 | { | |
5f97f7f9 HS |
395 | unsigned long flags; |
396 | u32 mask; | |
397 | ||
7a5b8059 HS |
398 | spin_lock_irqsave(&pm_lock, flags); |
399 | mask = pm_readl(HSB_MASK); | |
5f97f7f9 HS |
400 | if (enabled) |
401 | mask |= 1 << clk->index; | |
402 | else | |
403 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
404 | pm_writel(HSB_MASK, mask); |
405 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
406 | } |
407 | ||
408 | static unsigned long hsb_clk_get_rate(struct clk *clk) | |
409 | { | |
410 | unsigned long cksel, shift = 0; | |
411 | ||
7a5b8059 HS |
412 | cksel = pm_readl(CKSEL); |
413 | if (cksel & PM_BIT(HSBDIV)) | |
414 | shift = PM_BFEXT(HSBSEL, cksel) + 1; | |
5f97f7f9 HS |
415 | |
416 | return bus_clk_get_rate(clk, shift); | |
417 | } | |
418 | ||
419 | static void pba_clk_mode(struct clk *clk, int enabled) | |
420 | { | |
5f97f7f9 HS |
421 | unsigned long flags; |
422 | u32 mask; | |
423 | ||
7a5b8059 HS |
424 | spin_lock_irqsave(&pm_lock, flags); |
425 | mask = pm_readl(PBA_MASK); | |
5f97f7f9 HS |
426 | if (enabled) |
427 | mask |= 1 << clk->index; | |
428 | else | |
429 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
430 | pm_writel(PBA_MASK, mask); |
431 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
432 | } |
433 | ||
434 | static unsigned long pba_clk_get_rate(struct clk *clk) | |
435 | { | |
436 | unsigned long cksel, shift = 0; | |
437 | ||
7a5b8059 HS |
438 | cksel = pm_readl(CKSEL); |
439 | if (cksel & PM_BIT(PBADIV)) | |
440 | shift = PM_BFEXT(PBASEL, cksel) + 1; | |
5f97f7f9 HS |
441 | |
442 | return bus_clk_get_rate(clk, shift); | |
443 | } | |
444 | ||
445 | static void pbb_clk_mode(struct clk *clk, int enabled) | |
446 | { | |
5f97f7f9 HS |
447 | unsigned long flags; |
448 | u32 mask; | |
449 | ||
7a5b8059 HS |
450 | spin_lock_irqsave(&pm_lock, flags); |
451 | mask = pm_readl(PBB_MASK); | |
5f97f7f9 HS |
452 | if (enabled) |
453 | mask |= 1 << clk->index; | |
454 | else | |
455 | mask &= ~(1 << clk->index); | |
7a5b8059 HS |
456 | pm_writel(PBB_MASK, mask); |
457 | spin_unlock_irqrestore(&pm_lock, flags); | |
5f97f7f9 HS |
458 | } |
459 | ||
460 | static unsigned long pbb_clk_get_rate(struct clk *clk) | |
461 | { | |
462 | unsigned long cksel, shift = 0; | |
463 | ||
7a5b8059 HS |
464 | cksel = pm_readl(CKSEL); |
465 | if (cksel & PM_BIT(PBBDIV)) | |
466 | shift = PM_BFEXT(PBBSEL, cksel) + 1; | |
5f97f7f9 HS |
467 | |
468 | return bus_clk_get_rate(clk, shift); | |
469 | } | |
470 | ||
471 | static struct clk cpu_clk = { | |
472 | .name = "cpu", | |
473 | .get_rate = cpu_clk_get_rate, | |
9e58e185 | 474 | .set_rate = cpu_clk_set_rate, |
5f97f7f9 HS |
475 | .users = 1, |
476 | }; | |
477 | static struct clk hsb_clk = { | |
478 | .name = "hsb", | |
479 | .parent = &cpu_clk, | |
480 | .get_rate = hsb_clk_get_rate, | |
481 | }; | |
482 | static struct clk pba_clk = { | |
483 | .name = "pba", | |
484 | .parent = &hsb_clk, | |
485 | .mode = hsb_clk_mode, | |
486 | .get_rate = pba_clk_get_rate, | |
487 | .index = 1, | |
488 | }; | |
489 | static struct clk pbb_clk = { | |
490 | .name = "pbb", | |
491 | .parent = &hsb_clk, | |
492 | .mode = hsb_clk_mode, | |
493 | .get_rate = pbb_clk_get_rate, | |
494 | .users = 1, | |
495 | .index = 2, | |
496 | }; | |
497 | ||
498 | /* -------------------------------------------------------------------- | |
499 | * Generic Clock operations | |
500 | * -------------------------------------------------------------------- */ | |
501 | ||
502 | static void genclk_mode(struct clk *clk, int enabled) | |
503 | { | |
504 | u32 control; | |
505 | ||
7a5b8059 | 506 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 | 507 | if (enabled) |
7a5b8059 | 508 | control |= PM_BIT(CEN); |
5f97f7f9 | 509 | else |
7a5b8059 HS |
510 | control &= ~PM_BIT(CEN); |
511 | pm_writel(GCCTRL(clk->index), control); | |
5f97f7f9 HS |
512 | } |
513 | ||
514 | static unsigned long genclk_get_rate(struct clk *clk) | |
515 | { | |
516 | u32 control; | |
517 | unsigned long div = 1; | |
518 | ||
7a5b8059 HS |
519 | control = pm_readl(GCCTRL(clk->index)); |
520 | if (control & PM_BIT(DIVEN)) | |
521 | div = 2 * (PM_BFEXT(DIV, control) + 1); | |
5f97f7f9 HS |
522 | |
523 | return clk->parent->get_rate(clk->parent) / div; | |
524 | } | |
525 | ||
526 | static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply) | |
527 | { | |
528 | u32 control; | |
529 | unsigned long parent_rate, actual_rate, div; | |
530 | ||
5f97f7f9 | 531 | parent_rate = clk->parent->get_rate(clk->parent); |
7a5b8059 | 532 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
533 | |
534 | if (rate > 3 * parent_rate / 4) { | |
535 | actual_rate = parent_rate; | |
7a5b8059 | 536 | control &= ~PM_BIT(DIVEN); |
5f97f7f9 HS |
537 | } else { |
538 | div = (parent_rate + rate) / (2 * rate) - 1; | |
7a5b8059 | 539 | control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN); |
5f97f7f9 HS |
540 | actual_rate = parent_rate / (2 * (div + 1)); |
541 | } | |
542 | ||
7a5b8059 HS |
543 | dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n", |
544 | clk->name, rate, actual_rate); | |
5f97f7f9 HS |
545 | |
546 | if (apply) | |
7a5b8059 | 547 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
548 | |
549 | return actual_rate; | |
550 | } | |
551 | ||
552 | int genclk_set_parent(struct clk *clk, struct clk *parent) | |
553 | { | |
554 | u32 control; | |
555 | ||
7a5b8059 HS |
556 | dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n", |
557 | clk->name, parent->name, clk->parent->name); | |
5f97f7f9 | 558 | |
7a5b8059 | 559 | control = pm_readl(GCCTRL(clk->index)); |
5f97f7f9 HS |
560 | |
561 | if (parent == &osc1 || parent == &pll1) | |
7a5b8059 | 562 | control |= PM_BIT(OSCSEL); |
5f97f7f9 | 563 | else if (parent == &osc0 || parent == &pll0) |
7a5b8059 | 564 | control &= ~PM_BIT(OSCSEL); |
5f97f7f9 HS |
565 | else |
566 | return -EINVAL; | |
567 | ||
568 | if (parent == &pll0 || parent == &pll1) | |
7a5b8059 | 569 | control |= PM_BIT(PLLSEL); |
5f97f7f9 | 570 | else |
7a5b8059 | 571 | control &= ~PM_BIT(PLLSEL); |
5f97f7f9 | 572 | |
7a5b8059 | 573 | pm_writel(GCCTRL(clk->index), control); |
5f97f7f9 HS |
574 | clk->parent = parent; |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
7a5fe238 HS |
579 | static void __init genclk_init_parent(struct clk *clk) |
580 | { | |
581 | u32 control; | |
582 | struct clk *parent; | |
583 | ||
584 | BUG_ON(clk->index > 7); | |
585 | ||
7a5b8059 HS |
586 | control = pm_readl(GCCTRL(clk->index)); |
587 | if (control & PM_BIT(OSCSEL)) | |
588 | parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1; | |
7a5fe238 | 589 | else |
7a5b8059 | 590 | parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0; |
7a5fe238 HS |
591 | |
592 | clk->parent = parent; | |
593 | } | |
594 | ||
5f97f7f9 HS |
595 | /* -------------------------------------------------------------------- |
596 | * System peripherals | |
597 | * -------------------------------------------------------------------- */ | |
7a5b8059 HS |
598 | static struct resource at32_pm0_resource[] = { |
599 | { | |
600 | .start = 0xfff00000, | |
601 | .end = 0xfff0007f, | |
602 | .flags = IORESOURCE_MEM, | |
603 | }, | |
604 | IRQ(20), | |
5f97f7f9 | 605 | }; |
7a5b8059 HS |
606 | |
607 | static struct resource at32ap700x_rtc0_resource[] = { | |
608 | { | |
609 | .start = 0xfff00080, | |
610 | .end = 0xfff000af, | |
611 | .flags = IORESOURCE_MEM, | |
612 | }, | |
613 | IRQ(21), | |
5f97f7f9 | 614 | }; |
7a5b8059 HS |
615 | |
616 | static struct resource at32_wdt0_resource[] = { | |
617 | { | |
618 | .start = 0xfff000b0, | |
9797bed2 | 619 | .end = 0xfff000cf, |
7a5b8059 HS |
620 | .flags = IORESOURCE_MEM, |
621 | }, | |
622 | }; | |
623 | ||
624 | static struct resource at32_eic0_resource[] = { | |
625 | { | |
626 | .start = 0xfff00100, | |
627 | .end = 0xfff0013f, | |
628 | .flags = IORESOURCE_MEM, | |
629 | }, | |
630 | IRQ(19), | |
631 | }; | |
632 | ||
633 | DEFINE_DEV(at32_pm, 0); | |
634 | DEFINE_DEV(at32ap700x_rtc, 0); | |
635 | DEFINE_DEV(at32_wdt, 0); | |
636 | DEFINE_DEV(at32_eic, 0); | |
637 | ||
638 | /* | |
639 | * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this | |
640 | * is always running. | |
641 | */ | |
642 | static struct clk at32_pm_pclk = { | |
188ff65d | 643 | .name = "pclk", |
7a5b8059 | 644 | .dev = &at32_pm0_device.dev, |
188ff65d HS |
645 | .parent = &pbb_clk, |
646 | .mode = pbb_clk_mode, | |
647 | .get_rate = pbb_clk_get_rate, | |
648 | .users = 1, | |
649 | .index = 0, | |
650 | }; | |
5f97f7f9 HS |
651 | |
652 | static struct resource intc0_resource[] = { | |
653 | PBMEM(0xfff00400), | |
654 | }; | |
655 | struct platform_device at32_intc0_device = { | |
656 | .name = "intc", | |
657 | .id = 0, | |
658 | .resource = intc0_resource, | |
659 | .num_resources = ARRAY_SIZE(intc0_resource), | |
660 | }; | |
661 | DEV_CLK(pclk, at32_intc0, pbb, 1); | |
662 | ||
663 | static struct clk ebi_clk = { | |
664 | .name = "ebi", | |
665 | .parent = &hsb_clk, | |
666 | .mode = hsb_clk_mode, | |
667 | .get_rate = hsb_clk_get_rate, | |
668 | .users = 1, | |
669 | }; | |
670 | static struct clk hramc_clk = { | |
671 | .name = "hramc", | |
672 | .parent = &hsb_clk, | |
673 | .mode = hsb_clk_mode, | |
674 | .get_rate = hsb_clk_get_rate, | |
675 | .users = 1, | |
188ff65d | 676 | .index = 3, |
5f97f7f9 HS |
677 | }; |
678 | ||
bc157b75 HS |
679 | static struct resource smc0_resource[] = { |
680 | PBMEM(0xfff03400), | |
681 | }; | |
682 | DEFINE_DEV(smc, 0); | |
683 | DEV_CLK(pclk, smc0, pbb, 13); | |
684 | DEV_CLK(mck, smc0, hsb, 0); | |
685 | ||
5f97f7f9 HS |
686 | static struct platform_device pdc_device = { |
687 | .name = "pdc", | |
688 | .id = 0, | |
689 | }; | |
690 | DEV_CLK(hclk, pdc, hsb, 4); | |
691 | DEV_CLK(pclk, pdc, pba, 16); | |
692 | ||
693 | static struct clk pico_clk = { | |
694 | .name = "pico", | |
695 | .parent = &cpu_clk, | |
696 | .mode = cpu_clk_mode, | |
697 | .get_rate = cpu_clk_get_rate, | |
698 | .users = 1, | |
699 | }; | |
700 | ||
2042c1c4 HS |
701 | static struct resource dmaca0_resource[] = { |
702 | { | |
703 | .start = 0xff200000, | |
704 | .end = 0xff20ffff, | |
705 | .flags = IORESOURCE_MEM, | |
706 | }, | |
707 | IRQ(2), | |
708 | }; | |
709 | DEFINE_DEV(dmaca, 0); | |
710 | DEV_CLK(hclk, dmaca0, hsb, 10); | |
711 | ||
9c8f8e75 HS |
712 | /* -------------------------------------------------------------------- |
713 | * HMATRIX | |
714 | * -------------------------------------------------------------------- */ | |
715 | ||
716 | static struct clk hmatrix_clk = { | |
717 | .name = "hmatrix_clk", | |
718 | .parent = &pbb_clk, | |
719 | .mode = pbb_clk_mode, | |
720 | .get_rate = pbb_clk_get_rate, | |
721 | .index = 2, | |
722 | .users = 1, | |
723 | }; | |
724 | #define HMATRIX_BASE ((void __iomem *)0xfff00800) | |
725 | ||
726 | #define hmatrix_readl(reg) \ | |
727 | __raw_readl((HMATRIX_BASE) + HMATRIX_##reg) | |
728 | #define hmatrix_writel(reg,value) \ | |
729 | __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg) | |
730 | ||
731 | /* | |
732 | * Set bits in the HMATRIX Special Function Register (SFR) used by the | |
733 | * External Bus Interface (EBI). This can be used to enable special | |
734 | * features like CompactFlash support, NAND Flash support, etc. on | |
735 | * certain chipselects. | |
736 | */ | |
737 | static inline void set_ebi_sfr_bits(u32 mask) | |
738 | { | |
739 | u32 sfr; | |
740 | ||
741 | clk_enable(&hmatrix_clk); | |
742 | sfr = hmatrix_readl(SFR4); | |
743 | sfr |= mask; | |
744 | hmatrix_writel(SFR4, sfr); | |
745 | clk_disable(&hmatrix_clk); | |
746 | } | |
747 | ||
7760989e | 748 | /* -------------------------------------------------------------------- |
e723ff66 | 749 | * Timer/Counter (TC) |
7760989e | 750 | * -------------------------------------------------------------------- */ |
e723ff66 DB |
751 | |
752 | static struct resource at32_tcb0_resource[] = { | |
7760989e HCE |
753 | PBMEM(0xfff00c00), |
754 | IRQ(22), | |
755 | }; | |
e723ff66 DB |
756 | static struct platform_device at32_tcb0_device = { |
757 | .name = "atmel_tcb", | |
7760989e | 758 | .id = 0, |
e723ff66 DB |
759 | .resource = at32_tcb0_resource, |
760 | .num_resources = ARRAY_SIZE(at32_tcb0_resource), | |
761 | }; | |
762 | DEV_CLK(t0_clk, at32_tcb0, pbb, 3); | |
763 | ||
764 | static struct resource at32_tcb1_resource[] = { | |
765 | PBMEM(0xfff01000), | |
766 | IRQ(23), | |
767 | }; | |
768 | static struct platform_device at32_tcb1_device = { | |
769 | .name = "atmel_tcb", | |
770 | .id = 1, | |
771 | .resource = at32_tcb1_resource, | |
772 | .num_resources = ARRAY_SIZE(at32_tcb1_resource), | |
7760989e | 773 | }; |
e723ff66 | 774 | DEV_CLK(t0_clk, at32_tcb1, pbb, 4); |
7760989e | 775 | |
5f97f7f9 HS |
776 | /* -------------------------------------------------------------------- |
777 | * PIO | |
778 | * -------------------------------------------------------------------- */ | |
779 | ||
780 | static struct resource pio0_resource[] = { | |
781 | PBMEM(0xffe02800), | |
782 | IRQ(13), | |
783 | }; | |
784 | DEFINE_DEV(pio, 0); | |
785 | DEV_CLK(mck, pio0, pba, 10); | |
786 | ||
787 | static struct resource pio1_resource[] = { | |
788 | PBMEM(0xffe02c00), | |
789 | IRQ(14), | |
790 | }; | |
791 | DEFINE_DEV(pio, 1); | |
792 | DEV_CLK(mck, pio1, pba, 11); | |
793 | ||
794 | static struct resource pio2_resource[] = { | |
795 | PBMEM(0xffe03000), | |
796 | IRQ(15), | |
797 | }; | |
798 | DEFINE_DEV(pio, 2); | |
799 | DEV_CLK(mck, pio2, pba, 12); | |
800 | ||
801 | static struct resource pio3_resource[] = { | |
802 | PBMEM(0xffe03400), | |
803 | IRQ(16), | |
804 | }; | |
805 | DEFINE_DEV(pio, 3); | |
806 | DEV_CLK(mck, pio3, pba, 13); | |
807 | ||
7f9f4678 HS |
808 | static struct resource pio4_resource[] = { |
809 | PBMEM(0xffe03800), | |
810 | IRQ(17), | |
811 | }; | |
812 | DEFINE_DEV(pio, 4); | |
813 | DEV_CLK(mck, pio4, pba, 14); | |
814 | ||
5f97f7f9 HS |
815 | void __init at32_add_system_devices(void) |
816 | { | |
7a5b8059 | 817 | platform_device_register(&at32_pm0_device); |
5f97f7f9 | 818 | platform_device_register(&at32_intc0_device); |
7a5b8059 HS |
819 | platform_device_register(&at32ap700x_rtc0_device); |
820 | platform_device_register(&at32_wdt0_device); | |
821 | platform_device_register(&at32_eic0_device); | |
bc157b75 | 822 | platform_device_register(&smc0_device); |
5f97f7f9 | 823 | platform_device_register(&pdc_device); |
2042c1c4 | 824 | platform_device_register(&dmaca0_device); |
5f97f7f9 | 825 | |
e723ff66 DB |
826 | platform_device_register(&at32_tcb0_device); |
827 | platform_device_register(&at32_tcb1_device); | |
7760989e | 828 | |
5f97f7f9 HS |
829 | platform_device_register(&pio0_device); |
830 | platform_device_register(&pio1_device); | |
831 | platform_device_register(&pio2_device); | |
832 | platform_device_register(&pio3_device); | |
7f9f4678 | 833 | platform_device_register(&pio4_device); |
5f97f7f9 HS |
834 | } |
835 | ||
d86d314f HCE |
836 | /* -------------------------------------------------------------------- |
837 | * PSIF | |
838 | * -------------------------------------------------------------------- */ | |
839 | static struct resource atmel_psif0_resource[] __initdata = { | |
840 | { | |
841 | .start = 0xffe03c00, | |
842 | .end = 0xffe03cff, | |
843 | .flags = IORESOURCE_MEM, | |
844 | }, | |
845 | IRQ(18), | |
846 | }; | |
847 | static struct clk atmel_psif0_pclk = { | |
848 | .name = "pclk", | |
849 | .parent = &pba_clk, | |
850 | .mode = pba_clk_mode, | |
851 | .get_rate = pba_clk_get_rate, | |
852 | .index = 15, | |
853 | }; | |
854 | ||
855 | static struct resource atmel_psif1_resource[] __initdata = { | |
856 | { | |
857 | .start = 0xffe03d00, | |
858 | .end = 0xffe03dff, | |
859 | .flags = IORESOURCE_MEM, | |
860 | }, | |
861 | IRQ(18), | |
862 | }; | |
863 | static struct clk atmel_psif1_pclk = { | |
864 | .name = "pclk", | |
865 | .parent = &pba_clk, | |
866 | .mode = pba_clk_mode, | |
867 | .get_rate = pba_clk_get_rate, | |
868 | .index = 15, | |
869 | }; | |
870 | ||
871 | struct platform_device *__init at32_add_device_psif(unsigned int id) | |
872 | { | |
873 | struct platform_device *pdev; | |
874 | ||
875 | if (!(id == 0 || id == 1)) | |
876 | return NULL; | |
877 | ||
878 | pdev = platform_device_alloc("atmel_psif", id); | |
879 | if (!pdev) | |
880 | return NULL; | |
881 | ||
882 | switch (id) { | |
883 | case 0: | |
884 | if (platform_device_add_resources(pdev, atmel_psif0_resource, | |
885 | ARRAY_SIZE(atmel_psif0_resource))) | |
886 | goto err_add_resources; | |
887 | atmel_psif0_pclk.dev = &pdev->dev; | |
888 | select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */ | |
889 | select_peripheral(PA(9), PERIPH_A, 0); /* DATA */ | |
890 | break; | |
891 | case 1: | |
892 | if (platform_device_add_resources(pdev, atmel_psif1_resource, | |
893 | ARRAY_SIZE(atmel_psif1_resource))) | |
894 | goto err_add_resources; | |
895 | atmel_psif1_pclk.dev = &pdev->dev; | |
896 | select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */ | |
897 | select_peripheral(PB(12), PERIPH_A, 0); /* DATA */ | |
898 | break; | |
899 | default: | |
900 | return NULL; | |
901 | } | |
902 | ||
903 | platform_device_add(pdev); | |
904 | return pdev; | |
905 | ||
906 | err_add_resources: | |
907 | platform_device_put(pdev); | |
908 | return NULL; | |
909 | } | |
910 | ||
5f97f7f9 HS |
911 | /* -------------------------------------------------------------------- |
912 | * USART | |
913 | * -------------------------------------------------------------------- */ | |
914 | ||
75d35213 HS |
915 | static struct atmel_uart_data atmel_usart0_data = { |
916 | .use_dma_tx = 1, | |
917 | .use_dma_rx = 1, | |
918 | }; | |
1e8ea802 | 919 | static struct resource atmel_usart0_resource[] = { |
5f97f7f9 | 920 | PBMEM(0xffe00c00), |
a3d912c8 | 921 | IRQ(6), |
5f97f7f9 | 922 | }; |
75d35213 | 923 | DEFINE_DEV_DATA(atmel_usart, 0); |
80f76c54 | 924 | DEV_CLK(usart, atmel_usart0, pba, 3); |
5f97f7f9 | 925 | |
75d35213 HS |
926 | static struct atmel_uart_data atmel_usart1_data = { |
927 | .use_dma_tx = 1, | |
928 | .use_dma_rx = 1, | |
929 | }; | |
1e8ea802 | 930 | static struct resource atmel_usart1_resource[] = { |
5f97f7f9 HS |
931 | PBMEM(0xffe01000), |
932 | IRQ(7), | |
933 | }; | |
75d35213 | 934 | DEFINE_DEV_DATA(atmel_usart, 1); |
1e8ea802 | 935 | DEV_CLK(usart, atmel_usart1, pba, 4); |
5f97f7f9 | 936 | |
75d35213 HS |
937 | static struct atmel_uart_data atmel_usart2_data = { |
938 | .use_dma_tx = 1, | |
939 | .use_dma_rx = 1, | |
940 | }; | |
1e8ea802 | 941 | static struct resource atmel_usart2_resource[] = { |
5f97f7f9 HS |
942 | PBMEM(0xffe01400), |
943 | IRQ(8), | |
944 | }; | |
75d35213 | 945 | DEFINE_DEV_DATA(atmel_usart, 2); |
1e8ea802 | 946 | DEV_CLK(usart, atmel_usart2, pba, 5); |
5f97f7f9 | 947 | |
75d35213 HS |
948 | static struct atmel_uart_data atmel_usart3_data = { |
949 | .use_dma_tx = 1, | |
950 | .use_dma_rx = 1, | |
951 | }; | |
1e8ea802 | 952 | static struct resource atmel_usart3_resource[] = { |
5f97f7f9 HS |
953 | PBMEM(0xffe01800), |
954 | IRQ(9), | |
955 | }; | |
75d35213 | 956 | DEFINE_DEV_DATA(atmel_usart, 3); |
1e8ea802 | 957 | DEV_CLK(usart, atmel_usart3, pba, 6); |
5f97f7f9 HS |
958 | |
959 | static inline void configure_usart0_pins(void) | |
960 | { | |
c3e2a79c HS |
961 | select_peripheral(PA(8), PERIPH_B, 0); /* RXD */ |
962 | select_peripheral(PA(9), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
963 | } |
964 | ||
965 | static inline void configure_usart1_pins(void) | |
966 | { | |
c3e2a79c HS |
967 | select_peripheral(PA(17), PERIPH_A, 0); /* RXD */ |
968 | select_peripheral(PA(18), PERIPH_A, 0); /* TXD */ | |
5f97f7f9 HS |
969 | } |
970 | ||
971 | static inline void configure_usart2_pins(void) | |
972 | { | |
c3e2a79c HS |
973 | select_peripheral(PB(26), PERIPH_B, 0); /* RXD */ |
974 | select_peripheral(PB(27), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
975 | } |
976 | ||
977 | static inline void configure_usart3_pins(void) | |
978 | { | |
c3e2a79c HS |
979 | select_peripheral(PB(18), PERIPH_B, 0); /* RXD */ |
980 | select_peripheral(PB(17), PERIPH_B, 0); /* TXD */ | |
5f97f7f9 HS |
981 | } |
982 | ||
a3d912c8 | 983 | static struct platform_device *__initdata at32_usarts[4]; |
c194588d HS |
984 | |
985 | void __init at32_map_usart(unsigned int hw_id, unsigned int line) | |
5f97f7f9 HS |
986 | { |
987 | struct platform_device *pdev; | |
988 | ||
c194588d | 989 | switch (hw_id) { |
5f97f7f9 | 990 | case 0: |
1e8ea802 | 991 | pdev = &atmel_usart0_device; |
5f97f7f9 HS |
992 | configure_usart0_pins(); |
993 | break; | |
994 | case 1: | |
1e8ea802 | 995 | pdev = &atmel_usart1_device; |
5f97f7f9 HS |
996 | configure_usart1_pins(); |
997 | break; | |
998 | case 2: | |
1e8ea802 | 999 | pdev = &atmel_usart2_device; |
5f97f7f9 HS |
1000 | configure_usart2_pins(); |
1001 | break; | |
1002 | case 3: | |
1e8ea802 | 1003 | pdev = &atmel_usart3_device; |
5f97f7f9 HS |
1004 | configure_usart3_pins(); |
1005 | break; | |
1006 | default: | |
c194588d | 1007 | return; |
75d35213 HS |
1008 | } |
1009 | ||
1010 | if (PXSEG(pdev->resource[0].start) == P4SEG) { | |
1011 | /* Addresses in the P4 segment are permanently mapped 1:1 */ | |
1012 | struct atmel_uart_data *data = pdev->dev.platform_data; | |
1013 | data->regs = (void __iomem *)pdev->resource[0].start; | |
5f97f7f9 HS |
1014 | } |
1015 | ||
c194588d HS |
1016 | pdev->id = line; |
1017 | at32_usarts[line] = pdev; | |
5f97f7f9 HS |
1018 | } |
1019 | ||
1020 | struct platform_device *__init at32_add_device_usart(unsigned int id) | |
1021 | { | |
c194588d HS |
1022 | platform_device_register(at32_usarts[id]); |
1023 | return at32_usarts[id]; | |
5f97f7f9 HS |
1024 | } |
1025 | ||
73e2798b | 1026 | struct platform_device *atmel_default_console_device; |
5f97f7f9 HS |
1027 | |
1028 | void __init at32_setup_serial_console(unsigned int usart_id) | |
1029 | { | |
c194588d | 1030 | atmel_default_console_device = at32_usarts[usart_id]; |
5f97f7f9 HS |
1031 | } |
1032 | ||
1033 | /* -------------------------------------------------------------------- | |
1034 | * Ethernet | |
1035 | * -------------------------------------------------------------------- */ | |
1036 | ||
438ff3f3 | 1037 | #ifdef CONFIG_CPU_AT32AP7000 |
5f97f7f9 HS |
1038 | static struct eth_platform_data macb0_data; |
1039 | static struct resource macb0_resource[] = { | |
1040 | PBMEM(0xfff01800), | |
1041 | IRQ(25), | |
1042 | }; | |
1043 | DEFINE_DEV_DATA(macb, 0); | |
1044 | DEV_CLK(hclk, macb0, hsb, 8); | |
1045 | DEV_CLK(pclk, macb0, pbb, 6); | |
1046 | ||
cfcb3a89 HS |
1047 | static struct eth_platform_data macb1_data; |
1048 | static struct resource macb1_resource[] = { | |
1049 | PBMEM(0xfff01c00), | |
1050 | IRQ(26), | |
1051 | }; | |
1052 | DEFINE_DEV_DATA(macb, 1); | |
1053 | DEV_CLK(hclk, macb1, hsb, 9); | |
1054 | DEV_CLK(pclk, macb1, pbb, 7); | |
1055 | ||
5f97f7f9 HS |
1056 | struct platform_device *__init |
1057 | at32_add_device_eth(unsigned int id, struct eth_platform_data *data) | |
1058 | { | |
1059 | struct platform_device *pdev; | |
1060 | ||
1061 | switch (id) { | |
1062 | case 0: | |
1063 | pdev = &macb0_device; | |
1064 | ||
c3e2a79c HS |
1065 | select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */ |
1066 | select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */ | |
1067 | select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */ | |
1068 | select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */ | |
1069 | select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */ | |
1070 | select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */ | |
1071 | select_peripheral(PC(13), PERIPH_A, 0); /* RXER */ | |
1072 | select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */ | |
1073 | select_peripheral(PC(16), PERIPH_A, 0); /* MDC */ | |
1074 | select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */ | |
5f97f7f9 HS |
1075 | |
1076 | if (!data->is_rmii) { | |
c3e2a79c HS |
1077 | select_peripheral(PC(0), PERIPH_A, 0); /* COL */ |
1078 | select_peripheral(PC(1), PERIPH_A, 0); /* CRS */ | |
1079 | select_peripheral(PC(2), PERIPH_A, 0); /* TXER */ | |
1080 | select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */ | |
1081 | select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */ | |
1082 | select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */ | |
1083 | select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */ | |
1084 | select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */ | |
1085 | select_peripheral(PC(18), PERIPH_A, 0); /* SPD */ | |
5f97f7f9 HS |
1086 | } |
1087 | break; | |
1088 | ||
cfcb3a89 HS |
1089 | case 1: |
1090 | pdev = &macb1_device; | |
1091 | ||
1092 | select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */ | |
1093 | select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */ | |
1094 | select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */ | |
1095 | select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */ | |
1096 | select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */ | |
1097 | select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */ | |
1098 | select_peripheral(PD(5), PERIPH_B, 0); /* RXER */ | |
1099 | select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */ | |
1100 | select_peripheral(PD(3), PERIPH_B, 0); /* MDC */ | |
1101 | select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */ | |
1102 | ||
1103 | if (!data->is_rmii) { | |
1104 | select_peripheral(PC(19), PERIPH_B, 0); /* COL */ | |
1105 | select_peripheral(PC(23), PERIPH_B, 0); /* CRS */ | |
1106 | select_peripheral(PC(26), PERIPH_B, 0); /* TXER */ | |
1107 | select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */ | |
1108 | select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */ | |
1109 | select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */ | |
1110 | select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */ | |
1111 | select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */ | |
1112 | select_peripheral(PD(15), PERIPH_B, 0); /* SPD */ | |
1113 | } | |
1114 | break; | |
1115 | ||
5f97f7f9 HS |
1116 | default: |
1117 | return NULL; | |
1118 | } | |
1119 | ||
1120 | memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data)); | |
1121 | platform_device_register(pdev); | |
1122 | ||
1123 | return pdev; | |
1124 | } | |
438ff3f3 | 1125 | #endif |
5f97f7f9 HS |
1126 | |
1127 | /* -------------------------------------------------------------------- | |
1128 | * SPI | |
1129 | * -------------------------------------------------------------------- */ | |
3d60ee1b | 1130 | static struct resource atmel_spi0_resource[] = { |
5f97f7f9 HS |
1131 | PBMEM(0xffe00000), |
1132 | IRQ(3), | |
1133 | }; | |
3d60ee1b HS |
1134 | DEFINE_DEV(atmel_spi, 0); |
1135 | DEV_CLK(spi_clk, atmel_spi0, pba, 0); | |
1136 | ||
1137 | static struct resource atmel_spi1_resource[] = { | |
1138 | PBMEM(0xffe00400), | |
1139 | IRQ(4), | |
1140 | }; | |
1141 | DEFINE_DEV(atmel_spi, 1); | |
1142 | DEV_CLK(spi_clk, atmel_spi1, pba, 1); | |
5f97f7f9 | 1143 | |
9a596a62 | 1144 | static void __init |
41d8ca45 HS |
1145 | at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, |
1146 | unsigned int n, const u8 *pins) | |
5f97f7f9 | 1147 | { |
41d8ca45 HS |
1148 | unsigned int pin, mode; |
1149 | ||
1150 | for (; n; n--, b++) { | |
1151 | b->bus_num = bus_num; | |
1152 | if (b->chip_select >= 4) | |
1153 | continue; | |
1154 | pin = (unsigned)b->controller_data; | |
1155 | if (!pin) { | |
1156 | pin = pins[b->chip_select]; | |
1157 | b->controller_data = (void *)pin; | |
1158 | } | |
1159 | mode = AT32_GPIOF_OUTPUT; | |
1160 | if (!(b->mode & SPI_CS_HIGH)) | |
1161 | mode |= AT32_GPIOF_HIGH; | |
1162 | at32_select_gpio(pin, mode); | |
1163 | } | |
1164 | } | |
1165 | ||
1166 | struct platform_device *__init | |
1167 | at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n) | |
1168 | { | |
1169 | /* | |
1170 | * Manage the chipselects as GPIOs, normally using the same pins | |
1171 | * the SPI controller expects; but boards can use other pins. | |
1172 | */ | |
1173 | static u8 __initdata spi0_pins[] = | |
1174 | { GPIO_PIN_PA(3), GPIO_PIN_PA(4), | |
1175 | GPIO_PIN_PA(5), GPIO_PIN_PA(20), }; | |
1176 | static u8 __initdata spi1_pins[] = | |
1177 | { GPIO_PIN_PB(2), GPIO_PIN_PB(3), | |
1178 | GPIO_PIN_PB(4), GPIO_PIN_PA(27), }; | |
5f97f7f9 HS |
1179 | struct platform_device *pdev; |
1180 | ||
1181 | switch (id) { | |
1182 | case 0: | |
3d60ee1b | 1183 | pdev = &atmel_spi0_device; |
9c2baf78 DB |
1184 | /* pullup MISO so a level is always defined */ |
1185 | select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP); | |
c3e2a79c HS |
1186 | select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */ |
1187 | select_peripheral(PA(2), PERIPH_A, 0); /* SCK */ | |
41d8ca45 | 1188 | at32_spi_setup_slaves(0, b, n, spi0_pins); |
3d60ee1b HS |
1189 | break; |
1190 | ||
1191 | case 1: | |
1192 | pdev = &atmel_spi1_device; | |
9c2baf78 DB |
1193 | /* pullup MISO so a level is always defined */ |
1194 | select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP); | |
3d60ee1b HS |
1195 | select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */ |
1196 | select_peripheral(PB(5), PERIPH_B, 0); /* SCK */ | |
41d8ca45 | 1197 | at32_spi_setup_slaves(1, b, n, spi1_pins); |
5f97f7f9 HS |
1198 | break; |
1199 | ||
1200 | default: | |
1201 | return NULL; | |
1202 | } | |
1203 | ||
41d8ca45 | 1204 | spi_register_board_info(b, n); |
5f97f7f9 HS |
1205 | platform_device_register(pdev); |
1206 | return pdev; | |
1207 | } | |
1208 | ||
2042c1c4 HS |
1209 | /* -------------------------------------------------------------------- |
1210 | * TWI | |
1211 | * -------------------------------------------------------------------- */ | |
1212 | static struct resource atmel_twi0_resource[] __initdata = { | |
1213 | PBMEM(0xffe00800), | |
1214 | IRQ(5), | |
1215 | }; | |
1216 | static struct clk atmel_twi0_pclk = { | |
1217 | .name = "twi_pclk", | |
1218 | .parent = &pba_clk, | |
1219 | .mode = pba_clk_mode, | |
1220 | .get_rate = pba_clk_get_rate, | |
1221 | .index = 2, | |
1222 | }; | |
1223 | ||
040b28fc BN |
1224 | struct platform_device *__init at32_add_device_twi(unsigned int id, |
1225 | struct i2c_board_info *b, | |
1226 | unsigned int n) | |
2042c1c4 HS |
1227 | { |
1228 | struct platform_device *pdev; | |
1229 | ||
1230 | if (id != 0) | |
1231 | return NULL; | |
1232 | ||
1233 | pdev = platform_device_alloc("atmel_twi", id); | |
1234 | if (!pdev) | |
1235 | return NULL; | |
1236 | ||
1237 | if (platform_device_add_resources(pdev, atmel_twi0_resource, | |
1238 | ARRAY_SIZE(atmel_twi0_resource))) | |
1239 | goto err_add_resources; | |
1240 | ||
1241 | select_peripheral(PA(6), PERIPH_A, 0); /* SDA */ | |
1242 | select_peripheral(PA(7), PERIPH_A, 0); /* SDL */ | |
1243 | ||
1244 | atmel_twi0_pclk.dev = &pdev->dev; | |
1245 | ||
040b28fc BN |
1246 | if (b) |
1247 | i2c_register_board_info(id, b, n); | |
1248 | ||
2042c1c4 HS |
1249 | platform_device_add(pdev); |
1250 | return pdev; | |
1251 | ||
1252 | err_add_resources: | |
1253 | platform_device_put(pdev); | |
1254 | return NULL; | |
1255 | } | |
1256 | ||
1257 | /* -------------------------------------------------------------------- | |
1258 | * MMC | |
1259 | * -------------------------------------------------------------------- */ | |
1260 | static struct resource atmel_mci0_resource[] __initdata = { | |
1261 | PBMEM(0xfff02400), | |
1262 | IRQ(28), | |
1263 | }; | |
1264 | static struct clk atmel_mci0_pclk = { | |
1265 | .name = "mci_clk", | |
1266 | .parent = &pbb_clk, | |
1267 | .mode = pbb_clk_mode, | |
1268 | .get_rate = pbb_clk_get_rate, | |
1269 | .index = 9, | |
1270 | }; | |
1271 | ||
1272 | struct platform_device *__init at32_add_device_mci(unsigned int id) | |
1273 | { | |
1274 | struct platform_device *pdev; | |
1275 | ||
1276 | if (id != 0) | |
1277 | return NULL; | |
1278 | ||
1279 | pdev = platform_device_alloc("atmel_mci", id); | |
1280 | if (!pdev) | |
1281 | return NULL; | |
1282 | ||
1283 | if (platform_device_add_resources(pdev, atmel_mci0_resource, | |
1284 | ARRAY_SIZE(atmel_mci0_resource))) | |
1285 | goto err_add_resources; | |
1286 | ||
1287 | select_peripheral(PA(10), PERIPH_A, 0); /* CLK */ | |
1288 | select_peripheral(PA(11), PERIPH_A, 0); /* CMD */ | |
1289 | select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */ | |
1290 | select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */ | |
1291 | select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */ | |
1292 | select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */ | |
1293 | ||
1294 | atmel_mci0_pclk.dev = &pdev->dev; | |
1295 | ||
1296 | platform_device_add(pdev); | |
1297 | return pdev; | |
1298 | ||
1299 | err_add_resources: | |
1300 | platform_device_put(pdev); | |
1301 | return NULL; | |
1302 | } | |
1303 | ||
5f97f7f9 HS |
1304 | /* -------------------------------------------------------------------- |
1305 | * LCDC | |
1306 | * -------------------------------------------------------------------- */ | |
438ff3f3 | 1307 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af HS |
1308 | static struct atmel_lcdfb_info atmel_lcdfb0_data; |
1309 | static struct resource atmel_lcdfb0_resource[] = { | |
5f97f7f9 HS |
1310 | { |
1311 | .start = 0xff000000, | |
1312 | .end = 0xff000fff, | |
1313 | .flags = IORESOURCE_MEM, | |
1314 | }, | |
1315 | IRQ(1), | |
d0a2b7af HS |
1316 | { |
1317 | /* Placeholder for pre-allocated fb memory */ | |
1318 | .start = 0x00000000, | |
1319 | .end = 0x00000000, | |
1320 | .flags = 0, | |
1321 | }, | |
5f97f7f9 | 1322 | }; |
d0a2b7af HS |
1323 | DEFINE_DEV_DATA(atmel_lcdfb, 0); |
1324 | DEV_CLK(hck1, atmel_lcdfb0, hsb, 7); | |
1325 | static struct clk atmel_lcdfb0_pixclk = { | |
1326 | .name = "lcdc_clk", | |
1327 | .dev = &atmel_lcdfb0_device.dev, | |
5f97f7f9 HS |
1328 | .mode = genclk_mode, |
1329 | .get_rate = genclk_get_rate, | |
1330 | .set_rate = genclk_set_rate, | |
1331 | .set_parent = genclk_set_parent, | |
1332 | .index = 7, | |
1333 | }; | |
1334 | ||
1335 | struct platform_device *__init | |
d0a2b7af | 1336 | at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, |
47882cf6 HCE |
1337 | unsigned long fbmem_start, unsigned long fbmem_len, |
1338 | unsigned int pin_config) | |
5f97f7f9 HS |
1339 | { |
1340 | struct platform_device *pdev; | |
d0a2b7af HS |
1341 | struct atmel_lcdfb_info *info; |
1342 | struct fb_monspecs *monspecs; | |
1343 | struct fb_videomode *modedb; | |
1344 | unsigned int modedb_size; | |
1345 | ||
1346 | /* | |
1347 | * Do a deep copy of the fb data, monspecs and modedb. Make | |
1348 | * sure all allocations are done before setting up the | |
1349 | * portmux. | |
1350 | */ | |
1351 | monspecs = kmemdup(data->default_monspecs, | |
1352 | sizeof(struct fb_monspecs), GFP_KERNEL); | |
1353 | if (!monspecs) | |
1354 | return NULL; | |
1355 | ||
1356 | modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len; | |
1357 | modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL); | |
1358 | if (!modedb) | |
1359 | goto err_dup_modedb; | |
1360 | monspecs->modedb = modedb; | |
5f97f7f9 HS |
1361 | |
1362 | switch (id) { | |
1363 | case 0: | |
d0a2b7af | 1364 | pdev = &atmel_lcdfb0_device; |
47882cf6 HCE |
1365 | |
1366 | switch (pin_config) { | |
1367 | case 0: | |
1368 | select_peripheral(PC(19), PERIPH_A, 0); /* CC */ | |
1369 | select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */ | |
1370 | select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */ | |
1371 | select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */ | |
1372 | select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */ | |
1373 | select_peripheral(PC(24), PERIPH_A, 0); /* MODE */ | |
1374 | select_peripheral(PC(25), PERIPH_A, 0); /* PWR */ | |
1375 | select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */ | |
1376 | select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */ | |
1377 | select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */ | |
1378 | select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */ | |
1379 | select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */ | |
1380 | select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */ | |
1381 | select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */ | |
1382 | select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */ | |
1383 | select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */ | |
1384 | select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */ | |
1385 | select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */ | |
1386 | select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */ | |
1387 | select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */ | |
1388 | select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */ | |
1389 | select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */ | |
1390 | select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */ | |
1391 | select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */ | |
1392 | select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */ | |
1393 | select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */ | |
1394 | select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */ | |
1395 | select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */ | |
1396 | select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */ | |
1397 | select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */ | |
1398 | select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */ | |
1399 | break; | |
1400 | case 1: | |
1401 | select_peripheral(PE(0), PERIPH_B, 0); /* CC */ | |
1402 | select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */ | |
1403 | select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */ | |
1404 | select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */ | |
1405 | select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */ | |
1406 | select_peripheral(PE(2), PERIPH_B, 0); /* MODE */ | |
1407 | select_peripheral(PC(25), PERIPH_A, 0); /* PWR */ | |
1408 | select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */ | |
1409 | select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */ | |
1410 | select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */ | |
1411 | select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */ | |
1412 | select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */ | |
1413 | select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */ | |
1414 | select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */ | |
1415 | select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */ | |
1416 | select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */ | |
1417 | select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */ | |
1418 | select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */ | |
1419 | select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */ | |
1420 | select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */ | |
1421 | select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */ | |
1422 | select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */ | |
1423 | select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */ | |
1424 | select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */ | |
1425 | select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */ | |
1426 | select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */ | |
1427 | select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */ | |
1428 | select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */ | |
1429 | select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */ | |
1430 | select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */ | |
1431 | select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */ | |
1432 | break; | |
1433 | default: | |
1434 | goto err_invalid_id; | |
1435 | } | |
5f97f7f9 | 1436 | |
d0a2b7af HS |
1437 | clk_set_parent(&atmel_lcdfb0_pixclk, &pll0); |
1438 | clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0)); | |
5f97f7f9 HS |
1439 | break; |
1440 | ||
1441 | default: | |
d0a2b7af | 1442 | goto err_invalid_id; |
5f97f7f9 HS |
1443 | } |
1444 | ||
d0a2b7af HS |
1445 | if (fbmem_len) { |
1446 | pdev->resource[2].start = fbmem_start; | |
1447 | pdev->resource[2].end = fbmem_start + fbmem_len - 1; | |
1448 | pdev->resource[2].flags = IORESOURCE_MEM; | |
1449 | } | |
1450 | ||
1451 | info = pdev->dev.platform_data; | |
1452 | memcpy(info, data, sizeof(struct atmel_lcdfb_info)); | |
1453 | info->default_monspecs = monspecs; | |
5f97f7f9 HS |
1454 | |
1455 | platform_device_register(pdev); | |
1456 | return pdev; | |
d0a2b7af HS |
1457 | |
1458 | err_invalid_id: | |
1459 | kfree(modedb); | |
1460 | err_dup_modedb: | |
1461 | kfree(monspecs); | |
1462 | return NULL; | |
5f97f7f9 | 1463 | } |
438ff3f3 | 1464 | #endif |
5f97f7f9 | 1465 | |
9a1e8eb1 DB |
1466 | /* -------------------------------------------------------------------- |
1467 | * PWM | |
1468 | * -------------------------------------------------------------------- */ | |
1469 | static struct resource atmel_pwm0_resource[] __initdata = { | |
1470 | PBMEM(0xfff01400), | |
1471 | IRQ(24), | |
1472 | }; | |
1473 | static struct clk atmel_pwm0_mck = { | |
8405996f | 1474 | .name = "pwm_clk", |
9a1e8eb1 DB |
1475 | .parent = &pbb_clk, |
1476 | .mode = pbb_clk_mode, | |
1477 | .get_rate = pbb_clk_get_rate, | |
1478 | .index = 5, | |
1479 | }; | |
1480 | ||
1481 | struct platform_device *__init at32_add_device_pwm(u32 mask) | |
1482 | { | |
1483 | struct platform_device *pdev; | |
1484 | ||
1485 | if (!mask) | |
1486 | return NULL; | |
1487 | ||
1488 | pdev = platform_device_alloc("atmel_pwm", 0); | |
1489 | if (!pdev) | |
1490 | return NULL; | |
1491 | ||
1492 | if (platform_device_add_resources(pdev, atmel_pwm0_resource, | |
1493 | ARRAY_SIZE(atmel_pwm0_resource))) | |
1494 | goto out_free_pdev; | |
1495 | ||
1496 | if (platform_device_add_data(pdev, &mask, sizeof(mask))) | |
1497 | goto out_free_pdev; | |
1498 | ||
1499 | if (mask & (1 << 0)) | |
1500 | select_peripheral(PA(28), PERIPH_A, 0); | |
1501 | if (mask & (1 << 1)) | |
1502 | select_peripheral(PA(29), PERIPH_A, 0); | |
1503 | if (mask & (1 << 2)) | |
1504 | select_peripheral(PA(21), PERIPH_B, 0); | |
1505 | if (mask & (1 << 3)) | |
1506 | select_peripheral(PA(22), PERIPH_B, 0); | |
1507 | ||
1508 | atmel_pwm0_mck.dev = &pdev->dev; | |
1509 | ||
1510 | platform_device_add(pdev); | |
1511 | ||
1512 | return pdev; | |
1513 | ||
1514 | out_free_pdev: | |
1515 | platform_device_put(pdev); | |
1516 | return NULL; | |
1517 | } | |
1518 | ||
9cf6cf58 HCE |
1519 | /* -------------------------------------------------------------------- |
1520 | * SSC | |
1521 | * -------------------------------------------------------------------- */ | |
1522 | static struct resource ssc0_resource[] = { | |
1523 | PBMEM(0xffe01c00), | |
1524 | IRQ(10), | |
1525 | }; | |
1526 | DEFINE_DEV(ssc, 0); | |
1527 | DEV_CLK(pclk, ssc0, pba, 7); | |
1528 | ||
1529 | static struct resource ssc1_resource[] = { | |
1530 | PBMEM(0xffe02000), | |
1531 | IRQ(11), | |
1532 | }; | |
1533 | DEFINE_DEV(ssc, 1); | |
1534 | DEV_CLK(pclk, ssc1, pba, 8); | |
1535 | ||
1536 | static struct resource ssc2_resource[] = { | |
1537 | PBMEM(0xffe02400), | |
1538 | IRQ(12), | |
1539 | }; | |
1540 | DEFINE_DEV(ssc, 2); | |
1541 | DEV_CLK(pclk, ssc2, pba, 9); | |
1542 | ||
1543 | struct platform_device *__init | |
1544 | at32_add_device_ssc(unsigned int id, unsigned int flags) | |
1545 | { | |
1546 | struct platform_device *pdev; | |
1547 | ||
1548 | switch (id) { | |
1549 | case 0: | |
1550 | pdev = &ssc0_device; | |
1551 | if (flags & ATMEL_SSC_RF) | |
1552 | select_peripheral(PA(21), PERIPH_A, 0); /* RF */ | |
1553 | if (flags & ATMEL_SSC_RK) | |
1554 | select_peripheral(PA(22), PERIPH_A, 0); /* RK */ | |
1555 | if (flags & ATMEL_SSC_TK) | |
1556 | select_peripheral(PA(23), PERIPH_A, 0); /* TK */ | |
1557 | if (flags & ATMEL_SSC_TF) | |
1558 | select_peripheral(PA(24), PERIPH_A, 0); /* TF */ | |
1559 | if (flags & ATMEL_SSC_TD) | |
1560 | select_peripheral(PA(25), PERIPH_A, 0); /* TD */ | |
1561 | if (flags & ATMEL_SSC_RD) | |
1562 | select_peripheral(PA(26), PERIPH_A, 0); /* RD */ | |
1563 | break; | |
1564 | case 1: | |
1565 | pdev = &ssc1_device; | |
1566 | if (flags & ATMEL_SSC_RF) | |
1567 | select_peripheral(PA(0), PERIPH_B, 0); /* RF */ | |
1568 | if (flags & ATMEL_SSC_RK) | |
1569 | select_peripheral(PA(1), PERIPH_B, 0); /* RK */ | |
1570 | if (flags & ATMEL_SSC_TK) | |
1571 | select_peripheral(PA(2), PERIPH_B, 0); /* TK */ | |
1572 | if (flags & ATMEL_SSC_TF) | |
1573 | select_peripheral(PA(3), PERIPH_B, 0); /* TF */ | |
1574 | if (flags & ATMEL_SSC_TD) | |
1575 | select_peripheral(PA(4), PERIPH_B, 0); /* TD */ | |
1576 | if (flags & ATMEL_SSC_RD) | |
1577 | select_peripheral(PA(5), PERIPH_B, 0); /* RD */ | |
1578 | break; | |
1579 | case 2: | |
1580 | pdev = &ssc2_device; | |
1581 | if (flags & ATMEL_SSC_TD) | |
1582 | select_peripheral(PB(13), PERIPH_A, 0); /* TD */ | |
1583 | if (flags & ATMEL_SSC_RD) | |
1584 | select_peripheral(PB(14), PERIPH_A, 0); /* RD */ | |
1585 | if (flags & ATMEL_SSC_TK) | |
1586 | select_peripheral(PB(15), PERIPH_A, 0); /* TK */ | |
1587 | if (flags & ATMEL_SSC_TF) | |
1588 | select_peripheral(PB(16), PERIPH_A, 0); /* TF */ | |
1589 | if (flags & ATMEL_SSC_RF) | |
1590 | select_peripheral(PB(17), PERIPH_A, 0); /* RF */ | |
1591 | if (flags & ATMEL_SSC_RK) | |
1592 | select_peripheral(PB(18), PERIPH_A, 0); /* RK */ | |
1593 | break; | |
1594 | default: | |
1595 | return NULL; | |
1596 | } | |
1597 | ||
1598 | platform_device_register(pdev); | |
1599 | return pdev; | |
1600 | } | |
1601 | ||
6fcf0615 HS |
1602 | /* -------------------------------------------------------------------- |
1603 | * USB Device Controller | |
1604 | * -------------------------------------------------------------------- */ | |
1605 | static struct resource usba0_resource[] __initdata = { | |
1606 | { | |
1607 | .start = 0xff300000, | |
1608 | .end = 0xff3fffff, | |
1609 | .flags = IORESOURCE_MEM, | |
1610 | }, { | |
1611 | .start = 0xfff03000, | |
1612 | .end = 0xfff033ff, | |
1613 | .flags = IORESOURCE_MEM, | |
1614 | }, | |
1615 | IRQ(31), | |
1616 | }; | |
1617 | static struct clk usba0_pclk = { | |
1618 | .name = "pclk", | |
1619 | .parent = &pbb_clk, | |
1620 | .mode = pbb_clk_mode, | |
1621 | .get_rate = pbb_clk_get_rate, | |
1622 | .index = 12, | |
1623 | }; | |
1624 | static struct clk usba0_hclk = { | |
1625 | .name = "hclk", | |
1626 | .parent = &hsb_clk, | |
1627 | .mode = hsb_clk_mode, | |
1628 | .get_rate = hsb_clk_get_rate, | |
1629 | .index = 6, | |
1630 | }; | |
1631 | ||
8d855317 SP |
1632 | #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ |
1633 | [idx] = { \ | |
1634 | .name = nam, \ | |
1635 | .index = idx, \ | |
1636 | .fifo_size = maxpkt, \ | |
1637 | .nr_banks = maxbk, \ | |
1638 | .can_dma = dma, \ | |
1639 | .can_isoc = isoc, \ | |
1640 | } | |
1641 | ||
1642 | static struct usba_ep_data at32_usba_ep[] __initdata = { | |
1643 | EP("ep0", 0, 64, 1, 0, 0), | |
1644 | EP("ep1", 1, 512, 2, 1, 1), | |
1645 | EP("ep2", 2, 512, 2, 1, 1), | |
1646 | EP("ep3-int", 3, 64, 3, 1, 0), | |
1647 | EP("ep4-int", 4, 64, 3, 1, 0), | |
1648 | EP("ep5", 5, 1024, 3, 1, 1), | |
1649 | EP("ep6", 6, 1024, 3, 1, 1), | |
1650 | }; | |
1651 | ||
1652 | #undef EP | |
1653 | ||
6fcf0615 HS |
1654 | struct platform_device *__init |
1655 | at32_add_device_usba(unsigned int id, struct usba_platform_data *data) | |
1656 | { | |
8d855317 SP |
1657 | /* |
1658 | * pdata doesn't have room for any endpoints, so we need to | |
1659 | * append room for the ones we need right after it. | |
1660 | */ | |
1661 | struct { | |
1662 | struct usba_platform_data pdata; | |
1663 | struct usba_ep_data ep[7]; | |
1664 | } usba_data; | |
6fcf0615 HS |
1665 | struct platform_device *pdev; |
1666 | ||
1667 | if (id != 0) | |
1668 | return NULL; | |
1669 | ||
1670 | pdev = platform_device_alloc("atmel_usba_udc", 0); | |
1671 | if (!pdev) | |
1672 | return NULL; | |
1673 | ||
1674 | if (platform_device_add_resources(pdev, usba0_resource, | |
1675 | ARRAY_SIZE(usba0_resource))) | |
1676 | goto out_free_pdev; | |
1677 | ||
8d855317 SP |
1678 | if (data) |
1679 | usba_data.pdata.vbus_pin = data->vbus_pin; | |
1680 | else | |
1681 | usba_data.pdata.vbus_pin = -EINVAL; | |
6fcf0615 | 1682 | |
8d855317 SP |
1683 | data = &usba_data.pdata; |
1684 | data->num_ep = ARRAY_SIZE(at32_usba_ep); | |
1685 | memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep)); | |
1686 | ||
1687 | if (platform_device_add_data(pdev, data, sizeof(usba_data))) | |
1688 | goto out_free_pdev; | |
1689 | ||
1690 | if (data->vbus_pin >= 0) | |
1691 | at32_select_gpio(data->vbus_pin, 0); | |
6fcf0615 HS |
1692 | |
1693 | usba0_pclk.dev = &pdev->dev; | |
1694 | usba0_hclk.dev = &pdev->dev; | |
1695 | ||
1696 | platform_device_add(pdev); | |
1697 | ||
1698 | return pdev; | |
1699 | ||
1700 | out_free_pdev: | |
1701 | platform_device_put(pdev); | |
1702 | return NULL; | |
1703 | } | |
1704 | ||
48021bd9 | 1705 | /* -------------------------------------------------------------------- |
eaf5f925 | 1706 | * IDE / CompactFlash |
48021bd9 | 1707 | * -------------------------------------------------------------------- */ |
438ff3f3 | 1708 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001) |
eaf5f925 | 1709 | static struct resource at32_smc_cs4_resource[] __initdata = { |
48021bd9 KNG |
1710 | { |
1711 | .start = 0x04000000, | |
1712 | .end = 0x07ffffff, | |
1713 | .flags = IORESOURCE_MEM, | |
1714 | }, | |
1715 | IRQ(~0UL), /* Magic IRQ will be overridden */ | |
1716 | }; | |
eaf5f925 HS |
1717 | static struct resource at32_smc_cs5_resource[] __initdata = { |
1718 | { | |
1719 | .start = 0x20000000, | |
1720 | .end = 0x23ffffff, | |
1721 | .flags = IORESOURCE_MEM, | |
1722 | }, | |
1723 | IRQ(~0UL), /* Magic IRQ will be overridden */ | |
1724 | }; | |
48021bd9 | 1725 | |
eaf5f925 HS |
1726 | static int __init at32_init_ide_or_cf(struct platform_device *pdev, |
1727 | unsigned int cs, unsigned int extint) | |
48021bd9 | 1728 | { |
eaf5f925 HS |
1729 | static unsigned int extint_pin_map[4] __initdata = { |
1730 | GPIO_PIN_PB(25), | |
1731 | GPIO_PIN_PB(26), | |
1732 | GPIO_PIN_PB(27), | |
1733 | GPIO_PIN_PB(28), | |
1734 | }; | |
1735 | static bool common_pins_initialized __initdata = false; | |
48021bd9 | 1736 | unsigned int extint_pin; |
eaf5f925 | 1737 | int ret; |
48021bd9 | 1738 | |
eaf5f925 HS |
1739 | if (extint >= ARRAY_SIZE(extint_pin_map)) |
1740 | return -EINVAL; | |
1741 | extint_pin = extint_pin_map[extint]; | |
1742 | ||
1743 | switch (cs) { | |
1744 | case 4: | |
1745 | ret = platform_device_add_resources(pdev, | |
1746 | at32_smc_cs4_resource, | |
1747 | ARRAY_SIZE(at32_smc_cs4_resource)); | |
1748 | if (ret) | |
1749 | return ret; | |
1750 | ||
1751 | select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */ | |
1752 | set_ebi_sfr_bits(HMATRIX_BIT(CS4A)); | |
48021bd9 | 1753 | break; |
eaf5f925 HS |
1754 | case 5: |
1755 | ret = platform_device_add_resources(pdev, | |
1756 | at32_smc_cs5_resource, | |
1757 | ARRAY_SIZE(at32_smc_cs5_resource)); | |
1758 | if (ret) | |
1759 | return ret; | |
1760 | ||
1761 | select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */ | |
1762 | set_ebi_sfr_bits(HMATRIX_BIT(CS5A)); | |
48021bd9 KNG |
1763 | break; |
1764 | default: | |
eaf5f925 | 1765 | return -EINVAL; |
48021bd9 KNG |
1766 | } |
1767 | ||
eaf5f925 | 1768 | if (!common_pins_initialized) { |
48021bd9 KNG |
1769 | select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */ |
1770 | select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */ | |
48021bd9 KNG |
1771 | select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */ |
1772 | select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */ | |
eaf5f925 | 1773 | common_pins_initialized = true; |
48021bd9 KNG |
1774 | } |
1775 | ||
1776 | at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH); | |
1777 | ||
1778 | pdev->resource[1].start = EIM_IRQ_BASE + extint; | |
1779 | pdev->resource[1].end = pdev->resource[1].start; | |
1780 | ||
eaf5f925 HS |
1781 | return 0; |
1782 | } | |
48021bd9 | 1783 | |
eaf5f925 HS |
1784 | struct platform_device *__init |
1785 | at32_add_device_ide(unsigned int id, unsigned int extint, | |
1786 | struct ide_platform_data *data) | |
1787 | { | |
1788 | struct platform_device *pdev; | |
1789 | ||
1790 | pdev = platform_device_alloc("at32_ide", id); | |
1791 | if (!pdev) | |
1792 | goto fail; | |
1793 | ||
1794 | if (platform_device_add_data(pdev, data, | |
1795 | sizeof(struct ide_platform_data))) | |
1796 | goto fail; | |
1797 | ||
1798 | if (at32_init_ide_or_cf(pdev, data->cs, extint)) | |
1799 | goto fail; | |
1800 | ||
1801 | platform_device_add(pdev); | |
1802 | return pdev; | |
1803 | ||
1804 | fail: | |
1805 | platform_device_put(pdev); | |
1806 | return NULL; | |
1807 | } | |
1808 | ||
1809 | struct platform_device *__init | |
1810 | at32_add_device_cf(unsigned int id, unsigned int extint, | |
1811 | struct cf_platform_data *data) | |
1812 | { | |
1813 | struct platform_device *pdev; | |
1814 | ||
1815 | pdev = platform_device_alloc("at32_cf", id); | |
1816 | if (!pdev) | |
1817 | goto fail; | |
48021bd9 | 1818 | |
eaf5f925 HS |
1819 | if (platform_device_add_data(pdev, data, |
1820 | sizeof(struct cf_platform_data))) | |
1821 | goto fail; | |
1822 | ||
1823 | if (at32_init_ide_or_cf(pdev, data->cs, extint)) | |
1824 | goto fail; | |
1825 | ||
1826 | if (data->detect_pin != GPIO_PIN_NONE) | |
1827 | at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH); | |
1828 | if (data->reset_pin != GPIO_PIN_NONE) | |
1829 | at32_select_gpio(data->reset_pin, 0); | |
1830 | if (data->vcc_pin != GPIO_PIN_NONE) | |
1831 | at32_select_gpio(data->vcc_pin, 0); | |
1832 | /* READY is used as extint, so we can't select it as gpio */ | |
1833 | ||
1834 | platform_device_add(pdev); | |
48021bd9 | 1835 | return pdev; |
eaf5f925 HS |
1836 | |
1837 | fail: | |
1838 | platform_device_put(pdev); | |
1839 | return NULL; | |
48021bd9 | 1840 | } |
438ff3f3 | 1841 | #endif |
48021bd9 | 1842 | |
2042c1c4 HS |
1843 | /* -------------------------------------------------------------------- |
1844 | * AC97C | |
1845 | * -------------------------------------------------------------------- */ | |
1846 | static struct resource atmel_ac97c0_resource[] __initdata = { | |
1847 | PBMEM(0xfff02800), | |
1848 | IRQ(29), | |
1849 | }; | |
1850 | static struct clk atmel_ac97c0_pclk = { | |
1851 | .name = "pclk", | |
1852 | .parent = &pbb_clk, | |
1853 | .mode = pbb_clk_mode, | |
1854 | .get_rate = pbb_clk_get_rate, | |
1855 | .index = 10, | |
1856 | }; | |
1857 | ||
1858 | struct platform_device *__init at32_add_device_ac97c(unsigned int id) | |
1859 | { | |
1860 | struct platform_device *pdev; | |
1861 | ||
1862 | if (id != 0) | |
1863 | return NULL; | |
1864 | ||
1865 | pdev = platform_device_alloc("atmel_ac97c", id); | |
1866 | if (!pdev) | |
1867 | return NULL; | |
1868 | ||
1869 | if (platform_device_add_resources(pdev, atmel_ac97c0_resource, | |
1870 | ARRAY_SIZE(atmel_ac97c0_resource))) | |
1871 | goto err_add_resources; | |
1872 | ||
1873 | select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */ | |
1874 | select_peripheral(PB(21), PERIPH_B, 0); /* SDO */ | |
1875 | select_peripheral(PB(22), PERIPH_B, 0); /* SDI */ | |
1876 | select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */ | |
1877 | ||
1878 | atmel_ac97c0_pclk.dev = &pdev->dev; | |
1879 | ||
1880 | platform_device_add(pdev); | |
1881 | return pdev; | |
1882 | ||
1883 | err_add_resources: | |
1884 | platform_device_put(pdev); | |
1885 | return NULL; | |
1886 | } | |
1887 | ||
1888 | /* -------------------------------------------------------------------- | |
1889 | * ABDAC | |
1890 | * -------------------------------------------------------------------- */ | |
1891 | static struct resource abdac0_resource[] __initdata = { | |
1892 | PBMEM(0xfff02000), | |
1893 | IRQ(27), | |
1894 | }; | |
1895 | static struct clk abdac0_pclk = { | |
1896 | .name = "pclk", | |
1897 | .parent = &pbb_clk, | |
1898 | .mode = pbb_clk_mode, | |
1899 | .get_rate = pbb_clk_get_rate, | |
1900 | .index = 8, | |
1901 | }; | |
1902 | static struct clk abdac0_sample_clk = { | |
1903 | .name = "sample_clk", | |
1904 | .mode = genclk_mode, | |
1905 | .get_rate = genclk_get_rate, | |
1906 | .set_rate = genclk_set_rate, | |
1907 | .set_parent = genclk_set_parent, | |
1908 | .index = 6, | |
1909 | }; | |
1910 | ||
1911 | struct platform_device *__init at32_add_device_abdac(unsigned int id) | |
1912 | { | |
1913 | struct platform_device *pdev; | |
1914 | ||
1915 | if (id != 0) | |
1916 | return NULL; | |
1917 | ||
1918 | pdev = platform_device_alloc("abdac", id); | |
1919 | if (!pdev) | |
1920 | return NULL; | |
1921 | ||
1922 | if (platform_device_add_resources(pdev, abdac0_resource, | |
1923 | ARRAY_SIZE(abdac0_resource))) | |
1924 | goto err_add_resources; | |
1925 | ||
1926 | select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */ | |
1927 | select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */ | |
1928 | select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */ | |
1929 | select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */ | |
1930 | ||
1931 | abdac0_pclk.dev = &pdev->dev; | |
1932 | abdac0_sample_clk.dev = &pdev->dev; | |
1933 | ||
1934 | platform_device_add(pdev); | |
1935 | return pdev; | |
1936 | ||
1937 | err_add_resources: | |
1938 | platform_device_put(pdev); | |
1939 | return NULL; | |
1940 | } | |
1941 | ||
7a5fe238 HS |
1942 | /* -------------------------------------------------------------------- |
1943 | * GCLK | |
1944 | * -------------------------------------------------------------------- */ | |
1945 | static struct clk gclk0 = { | |
1946 | .name = "gclk0", | |
1947 | .mode = genclk_mode, | |
1948 | .get_rate = genclk_get_rate, | |
1949 | .set_rate = genclk_set_rate, | |
1950 | .set_parent = genclk_set_parent, | |
1951 | .index = 0, | |
1952 | }; | |
1953 | static struct clk gclk1 = { | |
1954 | .name = "gclk1", | |
1955 | .mode = genclk_mode, | |
1956 | .get_rate = genclk_get_rate, | |
1957 | .set_rate = genclk_set_rate, | |
1958 | .set_parent = genclk_set_parent, | |
1959 | .index = 1, | |
1960 | }; | |
1961 | static struct clk gclk2 = { | |
1962 | .name = "gclk2", | |
1963 | .mode = genclk_mode, | |
1964 | .get_rate = genclk_get_rate, | |
1965 | .set_rate = genclk_set_rate, | |
1966 | .set_parent = genclk_set_parent, | |
1967 | .index = 2, | |
1968 | }; | |
1969 | static struct clk gclk3 = { | |
1970 | .name = "gclk3", | |
1971 | .mode = genclk_mode, | |
1972 | .get_rate = genclk_get_rate, | |
1973 | .set_rate = genclk_set_rate, | |
1974 | .set_parent = genclk_set_parent, | |
1975 | .index = 3, | |
1976 | }; | |
1977 | static struct clk gclk4 = { | |
1978 | .name = "gclk4", | |
1979 | .mode = genclk_mode, | |
1980 | .get_rate = genclk_get_rate, | |
1981 | .set_rate = genclk_set_rate, | |
1982 | .set_parent = genclk_set_parent, | |
1983 | .index = 4, | |
1984 | }; | |
1985 | ||
5f97f7f9 HS |
1986 | struct clk *at32_clock_list[] = { |
1987 | &osc32k, | |
1988 | &osc0, | |
1989 | &osc1, | |
1990 | &pll0, | |
1991 | &pll1, | |
1992 | &cpu_clk, | |
1993 | &hsb_clk, | |
1994 | &pba_clk, | |
1995 | &pbb_clk, | |
7a5b8059 | 1996 | &at32_pm_pclk, |
5f97f7f9 | 1997 | &at32_intc0_pclk, |
9c8f8e75 | 1998 | &hmatrix_clk, |
5f97f7f9 HS |
1999 | &ebi_clk, |
2000 | &hramc_clk, | |
bc157b75 HS |
2001 | &smc0_pclk, |
2002 | &smc0_mck, | |
5f97f7f9 HS |
2003 | &pdc_hclk, |
2004 | &pdc_pclk, | |
2042c1c4 | 2005 | &dmaca0_hclk, |
5f97f7f9 HS |
2006 | &pico_clk, |
2007 | &pio0_mck, | |
2008 | &pio1_mck, | |
2009 | &pio2_mck, | |
2010 | &pio3_mck, | |
7f9f4678 | 2011 | &pio4_mck, |
e723ff66 DB |
2012 | &at32_tcb0_t0_clk, |
2013 | &at32_tcb1_t0_clk, | |
d86d314f HCE |
2014 | &atmel_psif0_pclk, |
2015 | &atmel_psif1_pclk, | |
1e8ea802 HS |
2016 | &atmel_usart0_usart, |
2017 | &atmel_usart1_usart, | |
2018 | &atmel_usart2_usart, | |
2019 | &atmel_usart3_usart, | |
9a1e8eb1 | 2020 | &atmel_pwm0_mck, |
438ff3f3 | 2021 | #if defined(CONFIG_CPU_AT32AP7000) |
5f97f7f9 HS |
2022 | &macb0_hclk, |
2023 | &macb0_pclk, | |
cfcb3a89 HS |
2024 | &macb1_hclk, |
2025 | &macb1_pclk, | |
438ff3f3 | 2026 | #endif |
3d60ee1b HS |
2027 | &atmel_spi0_spi_clk, |
2028 | &atmel_spi1_spi_clk, | |
2042c1c4 HS |
2029 | &atmel_twi0_pclk, |
2030 | &atmel_mci0_pclk, | |
438ff3f3 | 2031 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af HS |
2032 | &atmel_lcdfb0_hck1, |
2033 | &atmel_lcdfb0_pixclk, | |
438ff3f3 | 2034 | #endif |
9cf6cf58 HCE |
2035 | &ssc0_pclk, |
2036 | &ssc1_pclk, | |
2037 | &ssc2_pclk, | |
6fcf0615 HS |
2038 | &usba0_hclk, |
2039 | &usba0_pclk, | |
2042c1c4 HS |
2040 | &atmel_ac97c0_pclk, |
2041 | &abdac0_pclk, | |
2042 | &abdac0_sample_clk, | |
7a5fe238 HS |
2043 | &gclk0, |
2044 | &gclk1, | |
2045 | &gclk2, | |
2046 | &gclk3, | |
2047 | &gclk4, | |
5f97f7f9 HS |
2048 | }; |
2049 | unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list); | |
2050 | ||
65033ed7 | 2051 | void __init setup_platform(void) |
5f97f7f9 | 2052 | { |
5f97f7f9 HS |
2053 | u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0; |
2054 | int i; | |
2055 | ||
9e58e185 | 2056 | if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) { |
5f97f7f9 | 2057 | main_clock = &pll0; |
9e58e185 HCE |
2058 | cpu_clk.parent = &pll0; |
2059 | } else { | |
5f97f7f9 | 2060 | main_clock = &osc0; |
9e58e185 HCE |
2061 | cpu_clk.parent = &osc0; |
2062 | } | |
5f97f7f9 | 2063 | |
7a5b8059 | 2064 | if (pm_readl(PLL0) & PM_BIT(PLLOSC)) |
5f97f7f9 | 2065 | pll0.parent = &osc1; |
7a5b8059 | 2066 | if (pm_readl(PLL1) & PM_BIT(PLLOSC)) |
5f97f7f9 HS |
2067 | pll1.parent = &osc1; |
2068 | ||
7a5fe238 HS |
2069 | genclk_init_parent(&gclk0); |
2070 | genclk_init_parent(&gclk1); | |
2071 | genclk_init_parent(&gclk2); | |
2072 | genclk_init_parent(&gclk3); | |
2073 | genclk_init_parent(&gclk4); | |
438ff3f3 | 2074 | #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002) |
d0a2b7af | 2075 | genclk_init_parent(&atmel_lcdfb0_pixclk); |
438ff3f3 | 2076 | #endif |
2042c1c4 | 2077 | genclk_init_parent(&abdac0_sample_clk); |
7a5fe238 | 2078 | |
5f97f7f9 HS |
2079 | /* |
2080 | * Turn on all clocks that have at least one user already, and | |
2081 | * turn off everything else. We only do this for module | |
2082 | * clocks, and even though it isn't particularly pretty to | |
2083 | * check the address of the mode function, it should do the | |
2084 | * trick... | |
2085 | */ | |
2086 | for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) { | |
2087 | struct clk *clk = at32_clock_list[i]; | |
2088 | ||
188ff65d HS |
2089 | if (clk->users == 0) |
2090 | continue; | |
2091 | ||
5f97f7f9 HS |
2092 | if (clk->mode == &cpu_clk_mode) |
2093 | cpu_mask |= 1 << clk->index; | |
2094 | else if (clk->mode == &hsb_clk_mode) | |
2095 | hsb_mask |= 1 << clk->index; | |
2096 | else if (clk->mode == &pba_clk_mode) | |
2097 | pba_mask |= 1 << clk->index; | |
2098 | else if (clk->mode == &pbb_clk_mode) | |
2099 | pbb_mask |= 1 << clk->index; | |
2100 | } | |
2101 | ||
7a5b8059 HS |
2102 | pm_writel(CPU_MASK, cpu_mask); |
2103 | pm_writel(HSB_MASK, hsb_mask); | |
2104 | pm_writel(PBA_MASK, pba_mask); | |
2105 | pm_writel(PBB_MASK, pbb_mask); | |
65033ed7 HS |
2106 | |
2107 | /* Initialize the port muxes */ | |
2108 | at32_init_pio(&pio0_device); | |
2109 | at32_init_pio(&pio1_device); | |
2110 | at32_init_pio(&pio2_device); | |
2111 | at32_init_pio(&pio3_device); | |
2112 | at32_init_pio(&pio4_device); | |
5f97f7f9 | 2113 | } |