[deliverable/linux.git] / arch / avr32 / mach-at32ap / extint.c

/*
 * External interrupt handling for AT32AP CPUs
 *
 * Copyright (C) 2006 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/random.h>

#include <asm/io.h>

#include <asm/arch/sm.h>

#include "sm.h"

static void eim_ack_irq(unsigned int irq)
{
	struct at32_sm *sm = get_irq_chip_data(irq);
	sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
}

static void eim_mask_irq(unsigned int irq)
{
	struct at32_sm *sm = get_irq_chip_data(irq);
	sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
}

static void eim_mask_ack_irq(unsigned int irq)
{
	struct at32_sm *sm = get_irq_chip_data(irq);
	sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
	sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
}

static void eim_unmask_irq(unsigned int irq)
{
	struct at32_sm *sm = get_irq_chip_data(irq);
	sm_writel(sm, EIM_IER, 1 << (irq - sm->eim_first_irq));
}

static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
{
	struct at32_sm *sm = get_irq_chip_data(irq);
	struct irq_desc *desc;
	unsigned int i = irq - sm->eim_first_irq;
	u32 mode, edge, level;
	unsigned long flags;
	int ret = 0;

	if (flow_type == IRQ_TYPE_NONE)
		flow_type = IRQ_TYPE_LEVEL_LOW;

	desc = &irq_desc[irq];
	desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
	desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;

	if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
		desc->status |= IRQ_LEVEL;
		set_irq_handler(irq, handle_level_irq);
	} else {
		set_irq_handler(irq, handle_edge_irq);
	}

	spin_lock_irqsave(&sm->lock, flags);

	mode = sm_readl(sm, EIM_MODE);
	edge = sm_readl(sm, EIM_EDGE);
	level = sm_readl(sm, EIM_LEVEL);

	switch (flow_type) {
	case IRQ_TYPE_LEVEL_LOW:
		mode |= 1 << i;
		level &= ~(1 << i);
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		mode |= 1 << i;
		level |= 1 << i;
		break;
	case IRQ_TYPE_EDGE_RISING:
		mode &= ~(1 << i);
		edge |= 1 << i;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		mode &= ~(1 << i);
		edge &= ~(1 << i);
		break;
	default:
		ret = -EINVAL;
		break;
	}

	sm_writel(sm, EIM_MODE, mode);
	sm_writel(sm, EIM_EDGE, edge);
	sm_writel(sm, EIM_LEVEL, level);

	spin_unlock_irqrestore(&sm->lock, flags);

	return ret;
}

struct irq_chip eim_chip = {
	.name		= "eim",
	.ack		= eim_ack_irq,
	.mask		= eim_mask_irq,
	.mask_ack	= eim_mask_ack_irq,
	.unmask		= eim_unmask_irq,
	.set_type	= eim_set_irq_type,
};

static void demux_eim_irq(unsigned int irq, struct irq_desc *desc)
{
	struct at32_sm *sm = desc->handler_data;
	struct irq_desc *ext_desc;
	unsigned long status, pending;
	unsigned int i, ext_irq;

	spin_lock(&sm->lock);

	status = sm_readl(sm, EIM_ISR);
	pending = status & sm_readl(sm, EIM_IMR);

	while (pending) {
		i = fls(pending) - 1;
		pending &= ~(1 << i);

		ext_irq = i + sm->eim_first_irq;
		ext_desc = irq_desc + ext_irq;
		ext_desc->handle_irq(ext_irq, ext_desc);
	}

	spin_unlock(&sm->lock);
}

static int __init eim_init(void)
{
	struct at32_sm *sm = &system_manager;
	unsigned int i;
	unsigned int nr_irqs;
	unsigned int int_irq;
	u32 pattern;

	/*
	 * The EIM is really the same module as SM, so register
	 * mapping, etc. has been taken care of already.
	 */

	/*
	 * Find out how many interrupt lines that are actually
	 * implemented in hardware.
	 */
	sm_writel(sm, EIM_IDR, ~0UL);
	sm_writel(sm, EIM_MODE, ~0UL);
	pattern = sm_readl(sm, EIM_MODE);
	nr_irqs = fls(pattern);

	/* Trigger on falling edge unless overridden by driver */
	sm_writel(sm, EIM_MODE, 0UL);
	sm_writel(sm, EIM_EDGE, 0UL);

	sm->eim_chip = &eim_chip;

	for (i = 0; i < nr_irqs; i++) {
		set_irq_chip_and_handler(sm->eim_first_irq + i, &eim_chip,
					 handle_edge_irq);
		set_irq_chip_data(sm->eim_first_irq + i, sm);
	}

	int_irq = platform_get_irq_byname(sm->pdev, "eim");

	set_irq_chained_handler(int_irq, demux_eim_irq);
	set_irq_data(int_irq, sm);

	printk("EIM: External Interrupt Module at 0x%p, IRQ %u\n",
	       sm->regs, int_irq);
	printk("EIM: Handling %u external IRQs, starting with IRQ %u\n",
	       nr_irqs, sm->eim_first_irq);

	return 0;
}
arch_initcall(eim_init);
Commit	Line	Data
5f97f7f9 HS	1	/*
	2	* External interrupt handling for AT32AP CPUs
	3	*
	4	* Copyright (C) 2006 Atmel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/errno.h>
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/irq.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/random.h>
	17
	18	#include <asm/io.h>
	19
	20	#include <asm/arch/sm.h>
	21
	22	#include "sm.h"
	23
	24	static void eim_ack_irq(unsigned int irq)
	25	{
	26	struct at32_sm *sm = get_irq_chip_data(irq);
	27	sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
	28	}
	29
	30	static void eim_mask_irq(unsigned int irq)
	31	{
	32	struct at32_sm *sm = get_irq_chip_data(irq);
	33	sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
	34	}
	35
	36	static void eim_mask_ack_irq(unsigned int irq)
	37	{
	38	struct at32_sm *sm = get_irq_chip_data(irq);
	39	sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
	40	sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
	41	}
	42
	43	static void eim_unmask_irq(unsigned int irq)
	44	{
	45	struct at32_sm *sm = get_irq_chip_data(irq);
	46	sm_writel(sm, EIM_IER, 1 << (irq - sm->eim_first_irq));
	47	}
	48
	49	static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
	50	{
	51	struct at32_sm *sm = get_irq_chip_data(irq);
01cb087e	52	struct irq_desc *desc;
5f97f7f9 HS	53	unsigned int i = irq - sm->eim_first_irq;
	54	u32 mode, edge, level;
	55	unsigned long flags;
	56	int ret = 0;
	57
01cb087e HS	58	if (flow_type == IRQ_TYPE_NONE)
	59	flow_type = IRQ_TYPE_LEVEL_LOW;
	60
	61	desc = &irq_desc[irq];
	62	desc->status &= ~(IRQ_TYPE_SENSE_MASK \| IRQ_LEVEL);
	63	desc->status \|= flow_type & IRQ_TYPE_SENSE_MASK;
	64
	65	if (flow_type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH)) {
	66	desc->status \|= IRQ_LEVEL;
	67	set_irq_handler(irq, handle_level_irq);
	68	} else {
	69	set_irq_handler(irq, handle_edge_irq);
	70	}
5f97f7f9 HS	71
	72	spin_lock_irqsave(&sm->lock, flags);
	73
	74	mode = sm_readl(sm, EIM_MODE);
	75	edge = sm_readl(sm, EIM_EDGE);
	76	level = sm_readl(sm, EIM_LEVEL);
	77
	78	switch (flow_type) {
	79	case IRQ_TYPE_LEVEL_LOW:
	80	mode \|= 1 << i;
	81	level &= ~(1 << i);
	82	break;
	83	case IRQ_TYPE_LEVEL_HIGH:
	84	mode \|= 1 << i;
	85	level \|= 1 << i;
	86	break;
	87	case IRQ_TYPE_EDGE_RISING:
	88	mode &= ~(1 << i);
	89	edge \|= 1 << i;
	90	break;
	91	case IRQ_TYPE_EDGE_FALLING:
	92	mode &= ~(1 << i);
	93	edge &= ~(1 << i);
	94	break;
	95	default:
	96	ret = -EINVAL;
	97	break;
	98	}
	99
	100	sm_writel(sm, EIM_MODE, mode);
	101	sm_writel(sm, EIM_EDGE, edge);
	102	sm_writel(sm, EIM_LEVEL, level);
	103
	104	spin_unlock_irqrestore(&sm->lock, flags);
	105
	106	return ret;
	107	}
	108
	109	struct irq_chip eim_chip = {
	110	.name = "eim",
	111	.ack = eim_ack_irq,
	112	.mask = eim_mask_irq,
	113	.mask_ack = eim_mask_ack_irq,
	114	.unmask = eim_unmask_irq,
	115	.set_type = eim_set_irq_type,
	116	};
	117
4e0fadfc	118	static void demux_eim_irq(unsigned int irq, struct irq_desc *desc)
5f97f7f9 HS	119	{
	120	struct at32_sm *sm = desc->handler_data;
	121	struct irq_desc *ext_desc;
	122	unsigned long status, pending;
	123	unsigned int i, ext_irq;
	124
	125	spin_lock(&sm->lock);
	126
	127	status = sm_readl(sm, EIM_ISR);
	128	pending = status & sm_readl(sm, EIM_IMR);
	129
	130	while (pending) {
	131	i = fls(pending) - 1;
	132	pending &= ~(1 << i);
	133
	134	ext_irq = i + sm->eim_first_irq;
	135	ext_desc = irq_desc + ext_irq;
4e0fadfc	136	ext_desc->handle_irq(ext_irq, ext_desc);
5f97f7f9 HS	137	}
	138
	139	spin_unlock(&sm->lock);
	140	}
	141
	142	static int __init eim_init(void)
	143	{
	144	struct at32_sm *sm = &system_manager;
	145	unsigned int i;
	146	unsigned int nr_irqs;
	147	unsigned int int_irq;
	148	u32 pattern;
	149
	150	/*
	151	* The EIM is really the same module as SM, so register
	152	* mapping, etc. has been taken care of already.
	153	*/
	154
	155	/*
	156	* Find out how many interrupt lines that are actually
	157	* implemented in hardware.
	158	*/
	159	sm_writel(sm, EIM_IDR, ~0UL);
	160	sm_writel(sm, EIM_MODE, ~0UL);
	161	pattern = sm_readl(sm, EIM_MODE);
	162	nr_irqs = fls(pattern);
	163
01cb087e HS	164	/* Trigger on falling edge unless overridden by driver */
	165	sm_writel(sm, EIM_MODE, 0UL);
	166	sm_writel(sm, EIM_EDGE, 0UL);
	167
5f97f7f9 HS	168	sm->eim_chip = &eim_chip;
	169
	170	for (i = 0; i < nr_irqs; i++) {
01cb087e HS	171	set_irq_chip_and_handler(sm->eim_first_irq + i, &eim_chip,
01cb087e HS	172	handle_edge_irq);
5f97f7f9 HS	173	set_irq_chip_data(sm->eim_first_irq + i, sm);
	174	}
	175
	176	int_irq = platform_get_irq_byname(sm->pdev, "eim");
	177
	178	set_irq_chained_handler(int_irq, demux_eim_irq);
	179	set_irq_data(int_irq, sm);
	180
	181	printk("EIM: External Interrupt Module at 0x%p, IRQ %u\n",
	182	sm->regs, int_irq);
	183	printk("EIM: Handling %u external IRQs, starting with IRQ %u\n",
	184	nr_irqs, sm->eim_first_irq);
	185
	186	return 0;
	187	}
	188	arch_initcall(eim_init);