[deliverable/linux.git] / arch / avr32 / mach-at32ap / extint.c

/*
 * External interrupt handling for AT32AP CPUs
 *
 * Copyright (C) 2006 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/random.h>
#include <linux/slab.h>

#include <asm/io.h>

/* EIC register offsets */
#define EIC_IER					0x0000
#define EIC_IDR					0x0004
#define EIC_IMR					0x0008
#define EIC_ISR					0x000c
#define EIC_ICR					0x0010
#define EIC_MODE				0x0014
#define EIC_EDGE				0x0018
#define EIC_LEVEL				0x001c
#define EIC_NMIC				0x0024

/* Bitfields in NMIC */
#define EIC_NMIC_ENABLE				(1 << 0)

/* Bit manipulation macros */
#define EIC_BIT(name)					\
	(1 << EIC_##name##_OFFSET)
#define EIC_BF(name,value)				\
	(((value) & ((1 << EIC_##name##_SIZE) - 1))	\
	 << EIC_##name##_OFFSET)
#define EIC_BFEXT(name,value)				\
	(((value) >> EIC_##name##_OFFSET)		\
	 & ((1 << EIC_##name##_SIZE) - 1))
#define EIC_BFINS(name,value,old)			\
	(((old) & ~(((1 << EIC_##name##_SIZE) - 1)	\
		    << EIC_##name##_OFFSET))		\
	 | EIC_BF(name,value))

/* Register access macros */
#define eic_readl(port,reg)				\
	__raw_readl((port)->regs + EIC_##reg)
#define eic_writel(port,reg,value)			\
	__raw_writel((value), (port)->regs + EIC_##reg)

struct eic {
	void __iomem *regs;
	struct irq_chip *chip;
	unsigned int first_irq;
};

static struct eic *nmi_eic;
static bool nmi_enabled;

static void eic_ack_irq(struct irq_chip *d)
{
	struct eic *eic = irq_data_get_irq_chip_data(data);
	eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
}

static void eic_mask_irq(struct irq_chip *d)
{
	struct eic *eic = irq_data_get_irq_chip_data(data);
	eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
}

static void eic_mask_ack_irq(struct irq_chip *d)
{
	struct eic *eic = irq_data_get_irq_chip_data(data);
	eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
	eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
}

static void eic_unmask_irq(struct irq_chip *d)
{
	struct eic *eic = irq_data_get_irq_chip_data(data);
	eic_writel(eic, IER, 1 << (d->irq - eic->first_irq));
}

static int eic_set_irq_type(struct irq_chip *d, unsigned int flow_type)
{
	struct eic *eic = irq_data_get_irq_chip_data(data);
	struct irq_desc *desc;
	unsigned int irq = d->irq;
	unsigned int i = irq - eic->first_irq;
	u32 mode, edge, level;
	int ret = 0;

	flow_type &= IRQ_TYPE_SENSE_MASK;
	if (flow_type == IRQ_TYPE_NONE)
		flow_type = IRQ_TYPE_LEVEL_LOW;

	desc = irq_to_desc(irq);

	mode = eic_readl(eic, MODE);
	edge = eic_readl(eic, EDGE);
	level = eic_readl(eic, LEVEL);

	switch (flow_type) {
	case IRQ_TYPE_LEVEL_LOW:
		mode |= 1 << i;
		level &= ~(1 << i);
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		mode |= 1 << i;
		level |= 1 << i;
		break;
	case IRQ_TYPE_EDGE_RISING:
		mode &= ~(1 << i);
		edge |= 1 << i;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		mode &= ~(1 << i);
		edge &= ~(1 << i);
		break;
	default:
		ret = -EINVAL;
		break;
	}

	if (ret == 0) {
		eic_writel(eic, MODE, mode);
		eic_writel(eic, EDGE, edge);
		eic_writel(eic, LEVEL, level);

		if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
			flow_type |= IRQ_LEVEL;
			__irq_set_handler_locked(irq, handle_level_irq);
		} else
			__irq_set_handler_locked(irq, handle_edge_irq);
		desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
		desc->status |= flow_type;
	}

	return ret;
}

static struct irq_chip eic_chip = {
	.name		= "eic",
	.irq_ack	= eic_ack_irq,
	.irq_mask	= eic_mask_irq,
	.irq_mask_ack	= eic_mask_ack_irq,
	.irq_unmask	= eic_unmask_irq,
	.irq_set_type	= eic_set_irq_type,
};

static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
{
	struct eic *eic = irq_desc_get_handler_data(desc);
	unsigned long status, pending;
	unsigned int i;

	status = eic_readl(eic, ISR);
	pending = status & eic_readl(eic, IMR);

	while (pending) {
		i = fls(pending) - 1;
		pending &= ~(1 << i);

		generic_handle_irq(i + eic->first_irq);
	}
}

int nmi_enable(void)
{
	nmi_enabled = true;

	if (nmi_eic)
		eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);

	return 0;
}

void nmi_disable(void)
{
	if (nmi_eic)
		eic_writel(nmi_eic, NMIC, 0);

	nmi_enabled = false;
}

static int __init eic_probe(struct platform_device *pdev)
{
	struct eic *eic;
	struct resource *regs;
	unsigned int i;
	unsigned int nr_of_irqs;
	unsigned int int_irq;
	int ret;
	u32 pattern;

	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	int_irq = platform_get_irq(pdev, 0);
	if (!regs || !int_irq) {
		dev_dbg(&pdev->dev, "missing regs and/or irq resource\n");
		return -ENXIO;
	}

	ret = -ENOMEM;
	eic = kzalloc(sizeof(struct eic), GFP_KERNEL);
	if (!eic) {
		dev_dbg(&pdev->dev, "no memory for eic structure\n");
		goto err_kzalloc;
	}

	eic->first_irq = EIM_IRQ_BASE + 32 * pdev->id;
	eic->regs = ioremap(regs->start, regs->end - regs->start + 1);
	if (!eic->regs) {
		dev_dbg(&pdev->dev, "failed to map regs\n");
		goto err_ioremap;
	}

	/*
	 * Find out how many interrupt lines that are actually
	 * implemented in hardware.
	 */
	eic_writel(eic, IDR, ~0UL);
	eic_writel(eic, MODE, ~0UL);
	pattern = eic_readl(eic, MODE);
	nr_of_irqs = fls(pattern);

	/* Trigger on low level unless overridden by driver */
	eic_writel(eic, EDGE, 0UL);
	eic_writel(eic, LEVEL, 0UL);

	eic->chip = &eic_chip;

	for (i = 0; i < nr_of_irqs; i++) {
		irq_set_chip_and_handler(eic->first_irq + i, &eic_chip,
					 handle_level_irq);
		irq_set_chip_data(eic->first_irq + i, eic);
	}

	irq_set_chained_handler(int_irq, demux_eic_irq);
	irq_set_handler_data(int_irq, eic);

	if (pdev->id == 0) {
		nmi_eic = eic;
		if (nmi_enabled)
			/*
			 * Someone tried to enable NMI before we were
			 * ready. Do it now.
			 */
			nmi_enable();
	}

	dev_info(&pdev->dev,
		 "External Interrupt Controller at 0x%p, IRQ %u\n",
		 eic->regs, int_irq);
	dev_info(&pdev->dev,
		 "Handling %u external IRQs, starting with IRQ %u\n",
		 nr_of_irqs, eic->first_irq);

	return 0;

err_ioremap:
	kfree(eic);
err_kzalloc:
	return ret;
}

static struct platform_driver eic_driver = {
	.driver = {
		.name = "at32_eic",
	},
};

static int __init eic_init(void)
{
	return platform_driver_probe(&eic_driver, eic_probe);
}
arch_initcall(eic_init);
Commit	Line	Data
5f97f7f9 HS	1	/*
	2	* External interrupt handling for AT32AP CPUs
	3	*
	4	* Copyright (C) 2006 Atmel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/errno.h>
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/irq.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/random.h>
5a0e3ad6	17	#include <linux/slab.h>
5f97f7f9 HS	18
	19	#include <asm/io.h>
	20
7a5b8059 HS	21	/* EIC register offsets */
	22	#define EIC_IER 0x0000
	23	#define EIC_IDR 0x0004
	24	#define EIC_IMR 0x0008
	25	#define EIC_ISR 0x000c
	26	#define EIC_ICR 0x0010
	27	#define EIC_MODE 0x0014
	28	#define EIC_EDGE 0x0018
	29	#define EIC_LEVEL 0x001c
7a5b8059 HS	30	#define EIC_NMIC 0x0024
7a5b8059 HS	31
7a5b8059	32	/* Bitfields in NMIC */
e7ba176b	33	#define EIC_NMIC_ENABLE (1 << 0)
7a5b8059 HS	34
	35	/* Bit manipulation macros */
	36	#define EIC_BIT(name) \
	37	(1 << EIC_##name##_OFFSET)
	38	#define EIC_BF(name,value) \
	39	(((value) & ((1 << EIC_##name##_SIZE) - 1)) \
	40	<< EIC_##name##_OFFSET)
	41	#define EIC_BFEXT(name,value) \
	42	(((value) >> EIC_##name##_OFFSET) \
	43	& ((1 << EIC_##name##_SIZE) - 1))
	44	#define EIC_BFINS(name,value,old) \
	45	(((old) & ~(((1 << EIC_##name##_SIZE) - 1) \
	46	<< EIC_##name##_OFFSET)) \
	47	\| EIC_BF(name,value))
	48
	49	/* Register access macros */
	50	#define eic_readl(port,reg) \
	51	__raw_readl((port)->regs + EIC_##reg)
	52	#define eic_writel(port,reg,value) \
	53	__raw_writel((value), (port)->regs + EIC_##reg)
	54
	55	struct eic {
	56	void __iomem *regs;
	57	struct irq_chip *chip;
	58	unsigned int first_irq;
	59	};
5f97f7f9	60
e7ba176b HS	61	static struct eic *nmi_eic;
	62	static bool nmi_enabled;
	63
7776e233	64	static void eic_ack_irq(struct irq_chip *d)
5f97f7f9	65	{
7776e233 TG	66	struct eic *eic = irq_data_get_irq_chip_data(data);
7776e233 TG	67	eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
5f97f7f9 HS	68	}
5f97f7f9 HS	69
7776e233	70	static void eic_mask_irq(struct irq_chip *d)
5f97f7f9	71	{
7776e233 TG	72	struct eic *eic = irq_data_get_irq_chip_data(data);
7776e233 TG	73	eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
5f97f7f9 HS	74	}
5f97f7f9 HS	75
7776e233	76	static void eic_mask_ack_irq(struct irq_chip *d)
5f97f7f9	77	{
7776e233 TG	78	struct eic *eic = irq_data_get_irq_chip_data(data);
	79	eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
	80	eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
5f97f7f9 HS	81	}
5f97f7f9 HS	82
7776e233	83	static void eic_unmask_irq(struct irq_chip *d)
5f97f7f9	84	{
7776e233 TG	85	struct eic *eic = irq_data_get_irq_chip_data(data);
7776e233 TG	86	eic_writel(eic, IER, 1 << (d->irq - eic->first_irq));
5f97f7f9 HS	87	}
5f97f7f9 HS	88
7776e233	89	static int eic_set_irq_type(struct irq_chip *d, unsigned int flow_type)
5f97f7f9	90	{
7776e233	91	struct eic *eic = irq_data_get_irq_chip_data(data);
01cb087e	92	struct irq_desc *desc;
7776e233	93	unsigned int irq = d->irq;
7a5b8059	94	unsigned int i = irq - eic->first_irq;
5f97f7f9	95	u32 mode, edge, level;
5f97f7f9 HS	96	int ret = 0;
5f97f7f9 HS	97
58febc0b	98	flow_type &= IRQ_TYPE_SENSE_MASK;
01cb087e HS	99	if (flow_type == IRQ_TYPE_NONE)
	100	flow_type = IRQ_TYPE_LEVEL_LOW;
	101
7776e233	102	desc = irq_to_desc(irq);
5f97f7f9	103
7a5b8059 HS	104	mode = eic_readl(eic, MODE);
	105	edge = eic_readl(eic, EDGE);
	106	level = eic_readl(eic, LEVEL);
5f97f7f9 HS	107
	108	switch (flow_type) {
	109	case IRQ_TYPE_LEVEL_LOW:
	110	mode \|= 1 << i;
	111	level &= ~(1 << i);
	112	break;
	113	case IRQ_TYPE_LEVEL_HIGH:
	114	mode \|= 1 << i;
	115	level \|= 1 << i;
	116	break;
	117	case IRQ_TYPE_EDGE_RISING:
	118	mode &= ~(1 << i);
	119	edge \|= 1 << i;
	120	break;
	121	case IRQ_TYPE_EDGE_FALLING:
	122	mode &= ~(1 << i);
	123	edge &= ~(1 << i);
	124	break;
	125	default:
	126	ret = -EINVAL;
	127	break;
	128	}
	129
58febc0b	130	if (ret == 0) {
7a5b8059 HS	131	eic_writel(eic, MODE, mode);
	132	eic_writel(eic, EDGE, edge);
	133	eic_writel(eic, LEVEL, level);
58febc0b	134
e4f586f2	135	if (flow_type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH)) {
58febc0b	136	flow_type \|= IRQ_LEVEL;
d75f1bfd	137	__irq_set_handler_locked(irq, handle_level_irq);
e4f586f2	138	} else
d75f1bfd	139	__irq_set_handler_locked(irq, handle_edge_irq);
58febc0b DB	140	desc->status &= ~(IRQ_TYPE_SENSE_MASK \| IRQ_LEVEL);
	141	desc->status \|= flow_type;
	142	}
5f97f7f9	143
5f97f7f9 HS	144	return ret;
	145	}
	146
86298962	147	static struct irq_chip eic_chip = {
7a5b8059	148	.name = "eic",
7776e233 TG	149	.irq_ack = eic_ack_irq,
	150	.irq_mask = eic_mask_irq,
	151	.irq_mask_ack = eic_mask_ack_irq,
	152	.irq_unmask = eic_unmask_irq,
	153	.irq_set_type = eic_set_irq_type,
5f97f7f9 HS	154	};
5f97f7f9 HS	155
7a5b8059	156	static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
5f97f7f9	157	{
d75f1bfd	158	struct eic *eic = irq_desc_get_handler_data(desc);
5f97f7f9	159	unsigned long status, pending;
e4f586f2	160	unsigned int i;
5f97f7f9	161
7a5b8059 HS	162	status = eic_readl(eic, ISR);
7a5b8059 HS	163	pending = status & eic_readl(eic, IMR);
5f97f7f9 HS	164
	165	while (pending) {
	166	i = fls(pending) - 1;
	167	pending &= ~(1 << i);
	168
e4f586f2	169	generic_handle_irq(i + eic->first_irq);
5f97f7f9	170	}
5f97f7f9 HS	171	}
5f97f7f9 HS	172
e7ba176b HS	173	int nmi_enable(void)
	174	{
	175	nmi_enabled = true;
	176
	177	if (nmi_eic)
	178	eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
	179
	180	return 0;
	181	}
	182
	183	void nmi_disable(void)
	184	{
	185	if (nmi_eic)
	186	eic_writel(nmi_eic, NMIC, 0);
	187
	188	nmi_enabled = false;
	189	}
	190
7a5b8059	191	static int __init eic_probe(struct platform_device *pdev)
5f97f7f9	192	{
7a5b8059 HS	193	struct eic *eic;
7a5b8059 HS	194	struct resource *regs;
5f97f7f9	195	unsigned int i;
4b1135a2	196	unsigned int nr_of_irqs;
5f97f7f9	197	unsigned int int_irq;
7a5b8059	198	int ret;
5f97f7f9 HS	199	u32 pattern;
5f97f7f9 HS	200
7a5b8059 HS	201	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	202	int_irq = platform_get_irq(pdev, 0);
	203	if (!regs \|\| !int_irq) {
	204	dev_dbg(&pdev->dev, "missing regs and/or irq resource\n");
	205	return -ENXIO;
	206	}
	207
	208	ret = -ENOMEM;
	209	eic = kzalloc(sizeof(struct eic), GFP_KERNEL);
	210	if (!eic) {
	211	dev_dbg(&pdev->dev, "no memory for eic structure\n");
	212	goto err_kzalloc;
	213	}
	214
	215	eic->first_irq = EIM_IRQ_BASE + 32 * pdev->id;
	216	eic->regs = ioremap(regs->start, regs->end - regs->start + 1);
	217	if (!eic->regs) {
	218	dev_dbg(&pdev->dev, "failed to map regs\n");
	219	goto err_ioremap;
	220	}
5f97f7f9 HS	221
	222	/*
	223	* Find out how many interrupt lines that are actually
	224	* implemented in hardware.
	225	*/
7a5b8059 HS	226	eic_writel(eic, IDR, ~0UL);
	227	eic_writel(eic, MODE, ~0UL);
	228	pattern = eic_readl(eic, MODE);
4b1135a2	229	nr_of_irqs = fls(pattern);
5f97f7f9	230
d6c49a7a	231	/* Trigger on low level unless overridden by driver */
7a5b8059	232	eic_writel(eic, EDGE, 0UL);
d6c49a7a	233	eic_writel(eic, LEVEL, 0UL);
01cb087e	234
7a5b8059	235	eic->chip = &eic_chip;
5f97f7f9	236
4b1135a2	237	for (i = 0; i < nr_of_irqs; i++) {
d75f1bfd	238	irq_set_chip_and_handler(eic->first_irq + i, &eic_chip,
d6c49a7a	239	handle_level_irq);
d75f1bfd	240	irq_set_chip_data(eic->first_irq + i, eic);
5f97f7f9 HS	241	}
5f97f7f9 HS	242
d75f1bfd TG	243	irq_set_chained_handler(int_irq, demux_eic_irq);
d75f1bfd TG	244	irq_set_handler_data(int_irq, eic);
5f97f7f9	245
e7ba176b HS	246	if (pdev->id == 0) {
	247	nmi_eic = eic;
	248	if (nmi_enabled)
	249	/*
	250	* Someone tried to enable NMI before we were
	251	* ready. Do it now.
	252	*/
	253	nmi_enable();
	254	}
	255
7a5b8059 HS	256	dev_info(&pdev->dev,
	257	"External Interrupt Controller at 0x%p, IRQ %u\n",
	258	eic->regs, int_irq);
	259	dev_info(&pdev->dev,
	260	"Handling %u external IRQs, starting with IRQ %u\n",
4b1135a2	261	nr_of_irqs, eic->first_irq);
5f97f7f9 HS	262
5f97f7f9 HS	263	return 0;
7a5b8059 HS	264
	265	err_ioremap:
	266	kfree(eic);
	267	err_kzalloc:
	268	return ret;
	269	}
	270
	271	static struct platform_driver eic_driver = {
	272	.driver = {
	273	.name = "at32_eic",
	274	},
	275	};
	276
	277	static int __init eic_init(void)
	278	{
	279	return platform_driver_probe(&eic_driver, eic_probe);
5f97f7f9	280	}
7a5b8059	281	arch_initcall(eic_init);