Commit | Line | Data |
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5f97f7f9 HS |
1 | /* |
2 | * Copyright (C) 2004-2006 Atmel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <linux/highmem.h> | |
10 | #include <linux/unistd.h> | |
11 | ||
12 | #include <asm/cacheflush.h> | |
13 | #include <asm/cachectl.h> | |
14 | #include <asm/processor.h> | |
15 | #include <asm/uaccess.h> | |
16 | ||
17 | /* | |
18 | * If you attempt to flush anything more than this, you need superuser | |
19 | * privileges. The value is completely arbitrary. | |
20 | */ | |
21 | #define CACHEFLUSH_MAX_LEN 1024 | |
22 | ||
23 | void invalidate_dcache_region(void *start, size_t size) | |
24 | { | |
212868d3 DB |
25 | unsigned long v, begin, end, linesz, mask; |
26 | int flush = 0; | |
5f97f7f9 HS |
27 | |
28 | linesz = boot_cpu_data.dcache.linesz; | |
212868d3 | 29 | mask = linesz - 1; |
5f97f7f9 | 30 | |
212868d3 DB |
31 | /* when first and/or last cachelines are shared, flush them |
32 | * instead of invalidating ... never discard valid data! | |
33 | */ | |
34 | begin = (unsigned long)start; | |
35 | end = begin + size - 1; | |
5f97f7f9 | 36 | |
212868d3 DB |
37 | if (begin & mask) { |
38 | flush_dcache_line(start); | |
39 | begin += linesz; | |
40 | flush = 1; | |
41 | } | |
42 | if ((end & mask) != mask) { | |
43 | flush_dcache_line((void *)end); | |
44 | end -= linesz; | |
45 | flush = 1; | |
46 | } | |
5f97f7f9 | 47 | |
212868d3 DB |
48 | /* remaining cachelines only need invalidation */ |
49 | for (v = begin; v <= end; v += linesz) | |
5f97f7f9 | 50 | invalidate_dcache_line((void *)v); |
212868d3 DB |
51 | if (flush) |
52 | flush_write_buffer(); | |
5f97f7f9 HS |
53 | } |
54 | ||
55 | void clean_dcache_region(void *start, size_t size) | |
56 | { | |
57 | unsigned long v, begin, end, linesz; | |
58 | ||
59 | linesz = boot_cpu_data.dcache.linesz; | |
60 | begin = (unsigned long)start & ~(linesz - 1); | |
61 | end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); | |
62 | ||
63 | for (v = begin; v < end; v += linesz) | |
64 | clean_dcache_line((void *)v); | |
65 | flush_write_buffer(); | |
66 | } | |
67 | ||
68 | void flush_dcache_region(void *start, size_t size) | |
69 | { | |
70 | unsigned long v, begin, end, linesz; | |
71 | ||
72 | linesz = boot_cpu_data.dcache.linesz; | |
73 | begin = (unsigned long)start & ~(linesz - 1); | |
74 | end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); | |
75 | ||
76 | for (v = begin; v < end; v += linesz) | |
77 | flush_dcache_line((void *)v); | |
78 | flush_write_buffer(); | |
79 | } | |
80 | ||
81 | void invalidate_icache_region(void *start, size_t size) | |
82 | { | |
83 | unsigned long v, begin, end, linesz; | |
84 | ||
85 | linesz = boot_cpu_data.icache.linesz; | |
86 | begin = (unsigned long)start & ~(linesz - 1); | |
87 | end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1); | |
88 | ||
89 | for (v = begin; v < end; v += linesz) | |
90 | invalidate_icache_line((void *)v); | |
91 | } | |
92 | ||
93 | static inline void __flush_icache_range(unsigned long start, unsigned long end) | |
94 | { | |
95 | unsigned long v, linesz; | |
96 | ||
97 | linesz = boot_cpu_data.dcache.linesz; | |
98 | for (v = start; v < end; v += linesz) { | |
99 | clean_dcache_line((void *)v); | |
100 | invalidate_icache_line((void *)v); | |
101 | } | |
102 | ||
103 | flush_write_buffer(); | |
104 | } | |
105 | ||
106 | /* | |
107 | * This one is called after a module has been loaded. | |
108 | */ | |
109 | void flush_icache_range(unsigned long start, unsigned long end) | |
110 | { | |
111 | unsigned long linesz; | |
112 | ||
113 | linesz = boot_cpu_data.dcache.linesz; | |
114 | __flush_icache_range(start & ~(linesz - 1), | |
115 | (end + linesz - 1) & ~(linesz - 1)); | |
116 | } | |
117 | ||
118 | /* | |
119 | * This one is called from do_no_page(), do_swap_page() and install_page(). | |
120 | */ | |
121 | void flush_icache_page(struct vm_area_struct *vma, struct page *page) | |
122 | { | |
123 | if (vma->vm_flags & VM_EXEC) { | |
124 | void *v = kmap(page); | |
125 | __flush_icache_range((unsigned long)v, (unsigned long)v + PAGE_SIZE); | |
126 | kunmap(v); | |
127 | } | |
128 | } | |
129 | ||
130 | /* | |
131 | * This one is used by copy_to_user_page() | |
132 | */ | |
133 | void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, | |
134 | unsigned long addr, int len) | |
135 | { | |
136 | if (vma->vm_flags & VM_EXEC) | |
137 | flush_icache_range(addr, addr + len); | |
138 | } | |
139 | ||
140 | asmlinkage int sys_cacheflush(int operation, void __user *addr, size_t len) | |
141 | { | |
142 | int ret; | |
143 | ||
144 | if (len > CACHEFLUSH_MAX_LEN) { | |
145 | ret = -EPERM; | |
146 | if (!capable(CAP_SYS_ADMIN)) | |
147 | goto out; | |
148 | } | |
149 | ||
150 | ret = -EFAULT; | |
151 | if (!access_ok(VERIFY_WRITE, addr, len)) | |
152 | goto out; | |
153 | ||
154 | switch (operation) { | |
155 | case CACHE_IFLUSH: | |
156 | flush_icache_range((unsigned long)addr, | |
157 | (unsigned long)addr + len); | |
158 | ret = 0; | |
159 | break; | |
160 | default: | |
161 | ret = -EINVAL; | |
162 | } | |
163 | ||
164 | out: | |
165 | return ret; | |
166 | } |