Commit | Line | Data |
---|---|---|
1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
9 | bool | |
10 | default n | |
11 | ||
12 | config FPU | |
13 | bool | |
14 | default n | |
15 | ||
16 | config RWSEM_GENERIC_SPINLOCK | |
17 | bool | |
18 | default y | |
19 | ||
20 | config RWSEM_XCHGADD_ALGORITHM | |
21 | bool | |
22 | default n | |
23 | ||
24 | config BLACKFIN | |
25 | bool | |
26 | default y | |
ec7748b5 | 27 | select HAVE_IDE |
42d4b839 | 28 | select HAVE_OPROFILE |
1394f032 | 29 | |
e3defffe AL |
30 | config ZONE_DMA |
31 | bool | |
32 | default y | |
33 | ||
1394f032 BW |
34 | config SEMAPHORE_SLEEPERS |
35 | bool | |
36 | default y | |
37 | ||
38 | config GENERIC_FIND_NEXT_BIT | |
39 | bool | |
40 | default y | |
41 | ||
42 | config GENERIC_HWEIGHT | |
43 | bool | |
44 | default y | |
45 | ||
46 | config GENERIC_HARDIRQS | |
47 | bool | |
48 | default y | |
49 | ||
50 | config GENERIC_IRQ_PROBE | |
e4e9a7ad | 51 | bool |
1394f032 BW |
52 | default y |
53 | ||
54 | config GENERIC_TIME | |
55 | bool | |
56 | default n | |
57 | ||
b2d1583f | 58 | config GENERIC_GPIO |
1394f032 BW |
59 | bool |
60 | default y | |
61 | ||
62 | config FORCE_MAX_ZONEORDER | |
63 | int | |
64 | default "14" | |
65 | ||
66 | config GENERIC_CALIBRATE_DELAY | |
67 | bool | |
68 | default y | |
69 | ||
7d2284b0 MD |
70 | config HARDWARE_PM |
71 | def_bool y | |
72 | depends on OPROFILE | |
73 | ||
1394f032 BW |
74 | source "init/Kconfig" |
75 | source "kernel/Kconfig.preempt" | |
76 | ||
77 | menu "Blackfin Processor Options" | |
78 | ||
79 | comment "Processor and Board Settings" | |
80 | ||
81 | choice | |
82 | prompt "CPU" | |
83 | default BF533 | |
84 | ||
59003145 MH |
85 | config BF522 |
86 | bool "BF522" | |
87 | help | |
88 | BF522 Processor Support. | |
89 | ||
1545a111 MF |
90 | config BF523 |
91 | bool "BF523" | |
92 | help | |
93 | BF523 Processor Support. | |
94 | ||
95 | config BF524 | |
96 | bool "BF524" | |
97 | help | |
98 | BF524 Processor Support. | |
99 | ||
59003145 MH |
100 | config BF525 |
101 | bool "BF525" | |
102 | help | |
103 | BF525 Processor Support. | |
104 | ||
1545a111 MF |
105 | config BF526 |
106 | bool "BF526" | |
107 | help | |
108 | BF526 Processor Support. | |
109 | ||
59003145 MH |
110 | config BF527 |
111 | bool "BF527" | |
112 | help | |
113 | BF527 Processor Support. | |
114 | ||
1394f032 BW |
115 | config BF531 |
116 | bool "BF531" | |
117 | help | |
118 | BF531 Processor Support. | |
119 | ||
120 | config BF532 | |
121 | bool "BF532" | |
122 | help | |
123 | BF532 Processor Support. | |
124 | ||
125 | config BF533 | |
126 | bool "BF533" | |
127 | help | |
128 | BF533 Processor Support. | |
129 | ||
130 | config BF534 | |
131 | bool "BF534" | |
132 | help | |
133 | BF534 Processor Support. | |
134 | ||
135 | config BF536 | |
136 | bool "BF536" | |
137 | help | |
138 | BF536 Processor Support. | |
139 | ||
140 | config BF537 | |
141 | bool "BF537" | |
142 | help | |
143 | BF537 Processor Support. | |
144 | ||
24a07a12 RH |
145 | config BF542 |
146 | bool "BF542" | |
147 | help | |
148 | BF542 Processor Support. | |
149 | ||
150 | config BF544 | |
151 | bool "BF544" | |
152 | help | |
153 | BF544 Processor Support. | |
154 | ||
7c7fd170 MF |
155 | config BF547 |
156 | bool "BF547" | |
157 | help | |
158 | BF547 Processor Support. | |
159 | ||
24a07a12 RH |
160 | config BF548 |
161 | bool "BF548" | |
162 | help | |
163 | BF548 Processor Support. | |
164 | ||
165 | config BF549 | |
166 | bool "BF549" | |
167 | help | |
168 | BF549 Processor Support. | |
169 | ||
1394f032 BW |
170 | config BF561 |
171 | bool "BF561" | |
172 | help | |
173 | Not Supported Yet - Work in progress - BF561 Processor Support. | |
174 | ||
175 | endchoice | |
176 | ||
177 | choice | |
178 | prompt "Silicon Rev" | |
59003145 | 179 | default BF_REV_0_1 if BF527 |
1394f032 BW |
180 | default BF_REV_0_2 if BF537 |
181 | default BF_REV_0_3 if BF533 | |
24a07a12 RH |
182 | default BF_REV_0_0 if BF549 |
183 | ||
184 | config BF_REV_0_0 | |
185 | bool "0.0" | |
d07f4380 | 186 | depends on (BF52x || BF54x) |
59003145 MH |
187 | |
188 | config BF_REV_0_1 | |
d07f4380 MF |
189 | bool "0.1" |
190 | depends on (BF52x || BF54x) | |
1394f032 BW |
191 | |
192 | config BF_REV_0_2 | |
193 | bool "0.2" | |
194 | depends on (BF537 || BF536 || BF534) | |
195 | ||
196 | config BF_REV_0_3 | |
197 | bool "0.3" | |
198 | depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) | |
199 | ||
200 | config BF_REV_0_4 | |
201 | bool "0.4" | |
202 | depends on (BF561 || BF533 || BF532 || BF531) | |
203 | ||
204 | config BF_REV_0_5 | |
205 | bool "0.5" | |
206 | depends on (BF561 || BF533 || BF532 || BF531) | |
207 | ||
de3025f4 JZ |
208 | config BF_REV_ANY |
209 | bool "any" | |
210 | ||
211 | config BF_REV_NONE | |
212 | bool "none" | |
213 | ||
1394f032 BW |
214 | endchoice |
215 | ||
59003145 MH |
216 | config BF52x |
217 | bool | |
1545a111 | 218 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
219 | default y |
220 | ||
24a07a12 RH |
221 | config BF53x |
222 | bool | |
223 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
224 | default y | |
225 | ||
226 | config BF54x | |
227 | bool | |
7c7fd170 | 228 | depends on (BF542 || BF544 || BF547 || BF548 || BF549) |
24a07a12 RH |
229 | default y |
230 | ||
1394f032 BW |
231 | config BFIN_DUAL_CORE |
232 | bool | |
233 | depends on (BF561) | |
234 | default y | |
235 | ||
236 | config BFIN_SINGLE_CORE | |
237 | bool | |
238 | depends on !BFIN_DUAL_CORE | |
239 | default y | |
240 | ||
1394f032 BW |
241 | config MEM_GENERIC_BOARD |
242 | bool | |
243 | depends on GENERIC_BOARD | |
244 | default y | |
245 | ||
246 | config MEM_MT48LC64M4A2FB_7E | |
247 | bool | |
248 | depends on (BFIN533_STAMP) | |
249 | default y | |
250 | ||
251 | config MEM_MT48LC16M16A2TG_75 | |
252 | bool | |
253 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 JH |
254 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
255 | || H8606_HVSISTEMAS) | |
1394f032 BW |
256 | default y |
257 | ||
258 | config MEM_MT48LC32M8A2_75 | |
259 | bool | |
260 | depends on (BFIN537_STAMP || PNAV10) | |
261 | default y | |
262 | ||
263 | config MEM_MT48LC8M32B2B5_7 | |
264 | bool | |
265 | depends on (BFIN561_BLUETECHNIX_CM) | |
266 | default y | |
267 | ||
59003145 MH |
268 | config MEM_MT48LC32M16A2TG_75 |
269 | bool | |
270 | depends on (BFIN527_EZKIT) | |
271 | default y | |
272 | ||
59003145 | 273 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
274 | source "arch/blackfin/mach-bf533/Kconfig" |
275 | source "arch/blackfin/mach-bf561/Kconfig" | |
276 | source "arch/blackfin/mach-bf537/Kconfig" | |
24a07a12 | 277 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
278 | |
279 | menu "Board customizations" | |
280 | ||
281 | config CMDLINE_BOOL | |
282 | bool "Default bootloader kernel arguments" | |
283 | ||
284 | config CMDLINE | |
285 | string "Initial kernel command string" | |
286 | depends on CMDLINE_BOOL | |
287 | default "console=ttyBF0,57600" | |
288 | help | |
289 | If you don't have a boot loader capable of passing a command line string | |
290 | to the kernel, you may specify one here. As a minimum, you should specify | |
291 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
292 | ||
f16295e7 | 293 | comment "Clock/PLL Setup" |
1394f032 BW |
294 | |
295 | config CLKIN_HZ | |
296 | int "Crystal Frequency in Hz" | |
297 | default "11059200" if BFIN533_STAMP | |
298 | default "27000000" if BFIN533_EZKIT | |
ab472a04 | 299 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS) |
1394f032 BW |
300 | default "30000000" if BFIN561_EZKIT |
301 | default "24576000" if PNAV10 | |
302 | help | |
303 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
304 | ||
f16295e7 RG |
305 | config BFIN_KERNEL_CLOCK |
306 | bool "Re-program Clocks while Kernel boots?" | |
307 | default n | |
308 | help | |
309 | This option decides if kernel clocks are re-programed from the | |
310 | bootloader settings. If the clocks are not set, the SDRAM settings | |
311 | are also not changed, and the Bootloader does 100% of the hardware | |
312 | configuration. | |
313 | ||
314 | config PLL_BYPASS | |
e4e9a7ad MF |
315 | bool "Bypass PLL" |
316 | depends on BFIN_KERNEL_CLOCK | |
317 | default n | |
f16295e7 RG |
318 | |
319 | config CLKIN_HALF | |
320 | bool "Half Clock In" | |
321 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
322 | default n | |
323 | help | |
324 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
325 | ||
326 | config VCO_MULT | |
327 | int "VCO Multiplier" | |
328 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
329 | range 1 64 | |
330 | default "22" if BFIN533_EZKIT | |
331 | default "45" if BFIN533_STAMP | |
971d5bc4 | 332 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT) |
f16295e7 RG |
333 | default "22" if BFIN533_BLUETECHNIX_CM |
334 | default "20" if BFIN537_BLUETECHNIX_CM | |
335 | default "20" if BFIN561_BLUETECHNIX_CM | |
336 | default "20" if BFIN561_EZKIT | |
ab472a04 | 337 | default "16" if H8606_HVSISTEMAS |
f16295e7 RG |
338 | help |
339 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
340 | PLL Frequency = (Crystal Frequency) * (this setting) | |
341 | ||
342 | choice | |
343 | prompt "Core Clock Divider" | |
344 | depends on BFIN_KERNEL_CLOCK | |
345 | default CCLK_DIV_1 | |
346 | help | |
347 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
348 | Core Frequency = (PLL frequency) / (this setting) | |
349 | ||
350 | config CCLK_DIV_1 | |
351 | bool "1" | |
352 | ||
353 | config CCLK_DIV_2 | |
354 | bool "2" | |
355 | ||
356 | config CCLK_DIV_4 | |
357 | bool "4" | |
358 | ||
359 | config CCLK_DIV_8 | |
360 | bool "8" | |
361 | endchoice | |
362 | ||
363 | config SCLK_DIV | |
364 | int "System Clock Divider" | |
365 | depends on BFIN_KERNEL_CLOCK | |
366 | range 1 15 | |
367 | default 5 if BFIN533_EZKIT | |
368 | default 5 if BFIN533_STAMP | |
971d5bc4 | 369 | default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT) |
f16295e7 RG |
370 | default 5 if BFIN533_BLUETECHNIX_CM |
371 | default 4 if BFIN537_BLUETECHNIX_CM | |
372 | default 4 if BFIN561_BLUETECHNIX_CM | |
373 | default 5 if BFIN561_EZKIT | |
ab472a04 | 374 | default 3 if H8606_HVSISTEMAS |
f16295e7 RG |
375 | help |
376 | This sets the frequency of the system clock (including SDRAM or DDR). | |
377 | This can be between 1 and 15 | |
378 | System Clock = (PLL frequency) / (this setting) | |
379 | ||
380 | # | |
381 | # Max & Min Speeds for various Chips | |
382 | # | |
383 | config MAX_VCO_HZ | |
384 | int | |
385 | default 600000000 if BF522 | |
1545a111 MF |
386 | default 400000000 if BF523 |
387 | default 400000000 if BF524 | |
f16295e7 | 388 | default 600000000 if BF525 |
1545a111 | 389 | default 400000000 if BF526 |
f16295e7 RG |
390 | default 600000000 if BF527 |
391 | default 400000000 if BF531 | |
392 | default 400000000 if BF532 | |
393 | default 750000000 if BF533 | |
394 | default 500000000 if BF534 | |
395 | default 400000000 if BF536 | |
396 | default 600000000 if BF537 | |
f72eecb9 RG |
397 | default 533333333 if BF538 |
398 | default 533333333 if BF539 | |
f16295e7 | 399 | default 600000000 if BF542 |
f72eecb9 | 400 | default 533333333 if BF544 |
1545a111 MF |
401 | default 600000000 if BF547 |
402 | default 600000000 if BF548 | |
f72eecb9 | 403 | default 533333333 if BF549 |
f16295e7 RG |
404 | default 600000000 if BF561 |
405 | ||
406 | config MIN_VCO_HZ | |
407 | int | |
408 | default 50000000 | |
409 | ||
410 | config MAX_SCLK_HZ | |
411 | int | |
f72eecb9 | 412 | default 133333333 |
f16295e7 RG |
413 | |
414 | config MIN_SCLK_HZ | |
415 | int | |
416 | default 27000000 | |
417 | ||
418 | comment "Kernel Timer/Scheduler" | |
419 | ||
420 | source kernel/Kconfig.hz | |
421 | ||
422 | comment "Memory Setup" | |
423 | ||
1394f032 BW |
424 | config MEM_SIZE |
425 | int "SDRAM Memory Size in MBytes" | |
426 | default 32 if BFIN533_EZKIT | |
59003145 | 427 | default 64 if BFIN527_EZKIT |
1394f032 | 428 | default 64 if BFIN537_STAMP |
971d5bc4 | 429 | default 64 if BFIN548_EZKIT |
1394f032 BW |
430 | default 64 if BFIN561_EZKIT |
431 | default 128 if BFIN533_STAMP | |
432 | default 64 if PNAV10 | |
ab472a04 | 433 | default 32 if H8606_HVSISTEMAS |
1394f032 BW |
434 | |
435 | config MEM_ADD_WIDTH | |
436 | int "SDRAM Memory Address Width" | |
971d5bc4 | 437 | depends on (!BF54x) |
1394f032 BW |
438 | default 9 if BFIN533_EZKIT |
439 | default 9 if BFIN561_EZKIT | |
ab472a04 | 440 | default 9 if H8606_HVSISTEMAS |
59003145 | 441 | default 10 if BFIN527_EZKIT |
1394f032 BW |
442 | default 10 if BFIN537_STAMP |
443 | default 11 if BFIN533_STAMP | |
444 | default 10 if PNAV10 | |
445 | ||
971d5bc4 SZ |
446 | |
447 | choice | |
448 | prompt "DDR SDRAM Chip Type" | |
449 | depends on BFIN548_EZKIT | |
450 | default MEM_MT46V32M16_5B | |
451 | ||
452 | config MEM_MT46V32M16_6T | |
453 | bool "MT46V32M16_6T" | |
454 | ||
455 | config MEM_MT46V32M16_5B | |
456 | bool "MT46V32M16_5B" | |
457 | endchoice | |
458 | ||
1394f032 BW |
459 | config ENET_FLASH_PIN |
460 | int "PF port/pin used for flash and ethernet sharing" | |
461 | depends on (BFIN533_STAMP) | |
462 | default 0 | |
463 | help | |
464 | PF port/pin used for flash and ethernet sharing to allow other PF | |
465 | pins to be used on other platforms without having to touch common | |
466 | code. | |
467 | For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc. | |
468 | ||
469 | config BOOT_LOAD | |
470 | hex "Kernel load address for booting" | |
471 | default "0x1000" | |
2d8f161f | 472 | range 0x1000 0x20000000 |
1394f032 BW |
473 | help |
474 | This option allows you to set the load address of the kernel. | |
475 | This can be useful if you are on a board which has a small amount | |
476 | of memory or you wish to reserve some memory at the beginning of | |
477 | the address space. | |
478 | ||
2d8f161f MF |
479 | Note that you need to keep this value above 4k (0x1000) as this |
480 | memory region is used to capture NULL pointer references as well | |
481 | as some core kernel functions. | |
1394f032 | 482 | |
f0b5d12f MF |
483 | choice |
484 | prompt "Blackfin Exception Scratch Register" | |
485 | default BFIN_SCRATCH_REG_RETN | |
486 | help | |
487 | Select the resource to reserve for the Exception handler: | |
488 | - RETN: Non-Maskable Interrupt (NMI) | |
489 | - RETE: Exception Return (JTAG/ICE) | |
490 | - CYCLES: Performance counter | |
491 | ||
492 | If you are unsure, please select "RETN". | |
493 | ||
494 | config BFIN_SCRATCH_REG_RETN | |
495 | bool "RETN" | |
496 | help | |
497 | Use the RETN register in the Blackfin exception handler | |
498 | as a stack scratch register. This means you cannot | |
499 | safely use NMI on the Blackfin while running Linux, but | |
500 | you can debug the system with a JTAG ICE and use the | |
501 | CYCLES performance registers. | |
502 | ||
503 | If you are unsure, please select "RETN". | |
504 | ||
505 | config BFIN_SCRATCH_REG_RETE | |
506 | bool "RETE" | |
507 | help | |
508 | Use the RETE register in the Blackfin exception handler | |
509 | as a stack scratch register. This means you cannot | |
510 | safely use a JTAG ICE while debugging a Blackfin board, | |
511 | but you can safely use the CYCLES performance registers | |
512 | and the NMI. | |
513 | ||
514 | If you are unsure, please select "RETN". | |
515 | ||
516 | config BFIN_SCRATCH_REG_CYCLES | |
517 | bool "CYCLES" | |
518 | help | |
519 | Use the CYCLES register in the Blackfin exception handler | |
520 | as a stack scratch register. This means you cannot | |
521 | safely use the CYCLES performance registers on a Blackfin | |
522 | board at anytime, but you can debug the system with a JTAG | |
523 | ICE and use the NMI. | |
524 | ||
525 | If you are unsure, please select "RETN". | |
526 | ||
527 | endchoice | |
528 | ||
1394f032 BW |
529 | endmenu |
530 | ||
531 | ||
532 | menu "Blackfin Kernel Optimizations" | |
533 | ||
1394f032 BW |
534 | comment "Memory Optimizations" |
535 | ||
536 | config I_ENTRY_L1 | |
537 | bool "Locate interrupt entry code in L1 Memory" | |
538 | default y | |
539 | help | |
01dd2fbf ML |
540 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
541 | into L1 instruction memory. (less latency) | |
1394f032 BW |
542 | |
543 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 544 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
545 | default y |
546 | help | |
01dd2fbf | 547 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 548 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 549 | (less latency) |
1394f032 BW |
550 | |
551 | config DO_IRQ_L1 | |
552 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
553 | default y | |
554 | help | |
01dd2fbf ML |
555 | If enabled, the frequently called do_irq dispatcher function is linked |
556 | into L1 instruction memory. (less latency) | |
1394f032 BW |
557 | |
558 | config CORE_TIMER_IRQ_L1 | |
559 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
560 | default y | |
561 | help | |
01dd2fbf ML |
562 | If enabled, the frequently called timer_interrupt() function is linked |
563 | into L1 instruction memory. (less latency) | |
1394f032 BW |
564 | |
565 | config IDLE_L1 | |
566 | bool "Locate frequently idle function in L1 Memory" | |
567 | default y | |
568 | help | |
01dd2fbf ML |
569 | If enabled, the frequently called idle function is linked |
570 | into L1 instruction memory. (less latency) | |
1394f032 BW |
571 | |
572 | config SCHEDULE_L1 | |
573 | bool "Locate kernel schedule function in L1 Memory" | |
574 | default y | |
575 | help | |
01dd2fbf ML |
576 | If enabled, the frequently called kernel schedule is linked |
577 | into L1 instruction memory. (less latency) | |
1394f032 BW |
578 | |
579 | config ARITHMETIC_OPS_L1 | |
580 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
581 | default y | |
582 | help | |
01dd2fbf ML |
583 | If enabled, arithmetic functions are linked |
584 | into L1 instruction memory. (less latency) | |
1394f032 BW |
585 | |
586 | config ACCESS_OK_L1 | |
587 | bool "Locate access_ok function in L1 Memory" | |
588 | default y | |
589 | help | |
01dd2fbf ML |
590 | If enabled, the access_ok function is linked |
591 | into L1 instruction memory. (less latency) | |
1394f032 BW |
592 | |
593 | config MEMSET_L1 | |
594 | bool "Locate memset function in L1 Memory" | |
595 | default y | |
596 | help | |
01dd2fbf ML |
597 | If enabled, the memset function is linked |
598 | into L1 instruction memory. (less latency) | |
1394f032 BW |
599 | |
600 | config MEMCPY_L1 | |
601 | bool "Locate memcpy function in L1 Memory" | |
602 | default y | |
603 | help | |
01dd2fbf ML |
604 | If enabled, the memcpy function is linked |
605 | into L1 instruction memory. (less latency) | |
1394f032 BW |
606 | |
607 | config SYS_BFIN_SPINLOCK_L1 | |
608 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
609 | default y | |
610 | help | |
01dd2fbf ML |
611 | If enabled, sys_bfin_spinlock function is linked |
612 | into L1 instruction memory. (less latency) | |
1394f032 BW |
613 | |
614 | config IP_CHECKSUM_L1 | |
615 | bool "Locate IP Checksum function in L1 Memory" | |
616 | default n | |
617 | help | |
01dd2fbf ML |
618 | If enabled, the IP Checksum function is linked |
619 | into L1 instruction memory. (less latency) | |
1394f032 BW |
620 | |
621 | config CACHELINE_ALIGNED_L1 | |
622 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
623 | default y if !BF54x |
624 | default n if BF54x | |
1394f032 BW |
625 | depends on !BF531 |
626 | help | |
01dd2fbf ML |
627 | If enabled, cacheline_anligned data is linked |
628 | into L1 data memory. (less latency) | |
1394f032 BW |
629 | |
630 | config SYSCALL_TAB_L1 | |
631 | bool "Locate Syscall Table L1 Data Memory" | |
632 | default n | |
633 | depends on !BF531 | |
634 | help | |
01dd2fbf ML |
635 | If enabled, the Syscall LUT is linked |
636 | into L1 data memory. (less latency) | |
1394f032 BW |
637 | |
638 | config CPLB_SWITCH_TAB_L1 | |
639 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
640 | default n | |
641 | depends on !BF531 | |
642 | help | |
01dd2fbf ML |
643 | If enabled, the CPLB Switch Tables are linked |
644 | into L1 data memory. (less latency) | |
1394f032 BW |
645 | |
646 | endmenu | |
647 | ||
648 | ||
649 | choice | |
650 | prompt "Kernel executes from" | |
651 | help | |
652 | Choose the memory type that the kernel will be running in. | |
653 | ||
654 | config RAMKERNEL | |
655 | bool "RAM" | |
656 | help | |
657 | The kernel will be resident in RAM when running. | |
658 | ||
659 | config ROMKERNEL | |
660 | bool "ROM" | |
661 | help | |
662 | The kernel will be resident in FLASH/ROM when running. | |
663 | ||
664 | endchoice | |
665 | ||
666 | source "mm/Kconfig" | |
667 | ||
db0fa206 BW |
668 | config LARGE_ALLOCS |
669 | bool "Allow allocating large blocks (> 1MB) of memory" | |
670 | help | |
671 | Allow the slab memory allocator to keep chains for very large | |
672 | memory sizes - upto 32MB. You may need this if your system has | |
673 | a lot of RAM, and you need to able to allocate very large | |
674 | contiguous chunks. If unsure, say N. | |
675 | ||
780431e3 MF |
676 | config BFIN_GPTIMERS |
677 | tristate "Enable Blackfin General Purpose Timers API" | |
678 | default n | |
679 | help | |
680 | Enable support for the General Purpose Timers API. If you | |
681 | are unsure, say N. | |
682 | ||
683 | To compile this driver as a module, choose M here: the module | |
684 | will be called gptimers.ko. | |
685 | ||
1394f032 BW |
686 | config BFIN_DMA_5XX |
687 | bool "Enable DMA Support" | |
59003145 | 688 | depends on (BF52x || BF53x || BF561 || BF54x) |
1394f032 BW |
689 | default y |
690 | help | |
691 | DMA driver for BF5xx. | |
692 | ||
693 | choice | |
694 | prompt "Uncached SDRAM region" | |
695 | default DMA_UNCACHED_1M | |
247537b9 | 696 | depends on BFIN_DMA_5XX |
1394f032 BW |
697 | config DMA_UNCACHED_2M |
698 | bool "Enable 2M DMA region" | |
699 | config DMA_UNCACHED_1M | |
700 | bool "Enable 1M DMA region" | |
701 | config DMA_UNCACHED_NONE | |
702 | bool "Disable DMA region" | |
703 | endchoice | |
704 | ||
705 | ||
706 | comment "Cache Support" | |
3bebca2d | 707 | config BFIN_ICACHE |
1394f032 | 708 | bool "Enable ICACHE" |
3bebca2d | 709 | config BFIN_DCACHE |
1394f032 | 710 | bool "Enable DCACHE" |
3bebca2d | 711 | config BFIN_DCACHE_BANKA |
1394f032 | 712 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 713 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 714 | default n |
3bebca2d RG |
715 | config BFIN_ICACHE_LOCK |
716 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
717 | |
718 | choice | |
719 | prompt "Policy" | |
3bebca2d RG |
720 | depends on BFIN_DCACHE |
721 | default BFIN_WB | |
722 | config BFIN_WB | |
1394f032 BW |
723 | bool "Write back" |
724 | help | |
725 | Write Back Policy: | |
726 | Cached data will be written back to SDRAM only when needed. | |
727 | This can give a nice increase in performance, but beware of | |
728 | broken drivers that do not properly invalidate/flush their | |
729 | cache. | |
730 | ||
731 | Write Through Policy: | |
732 | Cached data will always be written back to SDRAM when the | |
733 | cache is updated. This is a completely safe setting, but | |
734 | performance is worse than Write Back. | |
735 | ||
736 | If you are unsure of the options and you want to be safe, | |
737 | then go with Write Through. | |
738 | ||
3bebca2d | 739 | config BFIN_WT |
1394f032 BW |
740 | bool "Write through" |
741 | help | |
742 | Write Back Policy: | |
743 | Cached data will be written back to SDRAM only when needed. | |
744 | This can give a nice increase in performance, but beware of | |
745 | broken drivers that do not properly invalidate/flush their | |
746 | cache. | |
747 | ||
748 | Write Through Policy: | |
749 | Cached data will always be written back to SDRAM when the | |
750 | cache is updated. This is a completely safe setting, but | |
751 | performance is worse than Write Back. | |
752 | ||
753 | If you are unsure of the options and you want to be safe, | |
754 | then go with Write Through. | |
755 | ||
756 | endchoice | |
757 | ||
758 | config L1_MAX_PIECE | |
759 | int "Set the max L1 SRAM pieces" | |
760 | default 16 | |
761 | help | |
762 | Set the max memory pieces for the L1 SRAM allocation algorithm. | |
763 | Min value is 16. Max value is 1024. | |
764 | ||
b97b8a99 BS |
765 | |
766 | config MPU | |
767 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
768 | default n | |
769 | help | |
770 | Use the processor's MPU to protect applications from accessing | |
771 | memory they do not own. This comes at a performance penalty | |
772 | and is recommended only for debugging. | |
773 | ||
1394f032 BW |
774 | comment "Asynchonous Memory Configuration" |
775 | ||
ddf416b2 | 776 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
777 | config C_AMCKEN |
778 | bool "Enable CLKOUT" | |
779 | default y | |
780 | ||
781 | config C_CDPRIO | |
782 | bool "DMA has priority over core for ext. accesses" | |
783 | default n | |
784 | ||
785 | config C_B0PEN | |
786 | depends on BF561 | |
787 | bool "Bank 0 16 bit packing enable" | |
788 | default y | |
789 | ||
790 | config C_B1PEN | |
791 | depends on BF561 | |
792 | bool "Bank 1 16 bit packing enable" | |
793 | default y | |
794 | ||
795 | config C_B2PEN | |
796 | depends on BF561 | |
797 | bool "Bank 2 16 bit packing enable" | |
798 | default y | |
799 | ||
800 | config C_B3PEN | |
801 | depends on BF561 | |
802 | bool "Bank 3 16 bit packing enable" | |
803 | default n | |
804 | ||
805 | choice | |
806 | prompt"Enable Asynchonous Memory Banks" | |
807 | default C_AMBEN_ALL | |
808 | ||
809 | config C_AMBEN | |
810 | bool "Disable All Banks" | |
811 | ||
812 | config C_AMBEN_B0 | |
813 | bool "Enable Bank 0" | |
814 | ||
815 | config C_AMBEN_B0_B1 | |
816 | bool "Enable Bank 0 & 1" | |
817 | ||
818 | config C_AMBEN_B0_B1_B2 | |
819 | bool "Enable Bank 0 & 1 & 2" | |
820 | ||
821 | config C_AMBEN_ALL | |
822 | bool "Enable All Banks" | |
823 | endchoice | |
824 | endmenu | |
825 | ||
826 | menu "EBIU_AMBCTL Control" | |
827 | config BANK_0 | |
828 | hex "Bank 0" | |
829 | default 0x7BB0 | |
830 | ||
831 | config BANK_1 | |
832 | hex "Bank 1" | |
833 | default 0x7BB0 | |
834 | ||
835 | config BANK_2 | |
836 | hex "Bank 2" | |
837 | default 0x7BB0 | |
838 | ||
839 | config BANK_3 | |
840 | hex "Bank 3" | |
841 | default 0x99B3 | |
842 | endmenu | |
843 | ||
e40540b3 SZ |
844 | config EBIU_MBSCTLVAL |
845 | hex "EBIU Bank Select Control Register" | |
846 | depends on BF54x | |
847 | default 0 | |
848 | ||
849 | config EBIU_MODEVAL | |
850 | hex "Flash Memory Mode Control Register" | |
851 | depends on BF54x | |
852 | default 1 | |
853 | ||
854 | config EBIU_FCTLVAL | |
855 | hex "Flash Memory Bank Control Register" | |
856 | depends on BF54x | |
857 | default 6 | |
1394f032 BW |
858 | endmenu |
859 | ||
860 | ############################################################################# | |
861 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
862 | ||
863 | config PCI | |
864 | bool "PCI support" | |
865 | help | |
866 | Support for PCI bus. | |
867 | ||
868 | source "drivers/pci/Kconfig" | |
869 | ||
870 | config HOTPLUG | |
871 | bool "Support for hot-pluggable device" | |
872 | help | |
873 | Say Y here if you want to plug devices into your computer while | |
874 | the system is running, and be able to use them quickly. In many | |
875 | cases, the devices can likewise be unplugged at any time too. | |
876 | ||
877 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
878 | size devices such as network cards, modems or hard drives which are | |
879 | plugged into slots found on all modern laptop computers. Another | |
880 | example, used on modern desktops as well as laptops, is USB. | |
881 | ||
882 | Enable HOTPLUG and KMOD, and build a modular kernel. Get agent | |
883 | software (at <http://linux-hotplug.sourceforge.net/>) and install it. | |
884 | Then your kernel will automatically call out to a user mode "policy | |
885 | agent" (/sbin/hotplug) to load modules and set up software needed | |
886 | to use devices as you hotplug them. | |
887 | ||
888 | source "drivers/pcmcia/Kconfig" | |
889 | ||
890 | source "drivers/pci/hotplug/Kconfig" | |
891 | ||
892 | endmenu | |
893 | ||
894 | menu "Executable file formats" | |
895 | ||
896 | source "fs/Kconfig.binfmt" | |
897 | ||
898 | endmenu | |
899 | ||
900 | menu "Power management options" | |
901 | source "kernel/power/Kconfig" | |
902 | ||
f4cb5700 JB |
903 | config ARCH_SUSPEND_POSSIBLE |
904 | def_bool y | |
905 | depends on !SMP | |
906 | ||
1394f032 | 907 | choice |
cfefe3c6 | 908 | prompt "Default Power Saving Mode" |
1394f032 | 909 | depends on PM |
cfefe3c6 MH |
910 | default PM_BFIN_SLEEP_DEEPER |
911 | config PM_BFIN_SLEEP_DEEPER | |
912 | bool "Sleep Deeper" | |
913 | help | |
914 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
915 | power dissipation by disabling the clock to the processor core (CCLK). | |
916 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
917 | to 0.85 V to provide the greatest power savings, while preserving the | |
918 | processor state. | |
919 | The PLL and system clock (SCLK) continue to operate at a very low | |
920 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
921 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
922 | such as GPIO interrupt or RTC activity wakes up the processor. | |
923 | Various Peripherals such as UART, SPORT, PPI may not function as | |
924 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
925 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
926 | ||
927 | config PM_BFIN_SLEEP | |
928 | bool "Sleep" | |
929 | help | |
930 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
931 | dissipation by disabling the clock to the processor core (CCLK). | |
932 | The PLL and system clock (SCLK), however, continue to operate in | |
933 | this mode. Typically an external event or RTC activity will wake | |
934 | up the processor. When in the sleep mode, | |
935 | system DMA access to L1 memory is not supported. | |
936 | endchoice | |
1394f032 | 937 | |
1394f032 BW |
938 | config PM_WAKEUP_BY_GPIO |
939 | bool "Cause Wakeup Event by GPIO" | |
1394f032 BW |
940 | |
941 | config PM_WAKEUP_GPIO_NUMBER | |
942 | int "Wakeup GPIO number" | |
943 | range 0 47 | |
944 | depends on PM_WAKEUP_BY_GPIO | |
945 | default 2 if BFIN537_STAMP | |
946 | ||
947 | choice | |
948 | prompt "GPIO Polarity" | |
949 | depends on PM_WAKEUP_BY_GPIO | |
950 | default PM_WAKEUP_GPIO_POLAR_H | |
951 | config PM_WAKEUP_GPIO_POLAR_H | |
952 | bool "Active High" | |
953 | config PM_WAKEUP_GPIO_POLAR_L | |
954 | bool "Active Low" | |
955 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
956 | bool "Falling EDGE" | |
957 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
958 | bool "Rising EDGE" | |
959 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
960 | bool "Both EDGE" | |
961 | endchoice | |
962 | ||
963 | endmenu | |
964 | ||
24a07a12 | 965 | if (BF537 || BF533 || BF54x) |
1394f032 BW |
966 | |
967 | menu "CPU Frequency scaling" | |
968 | ||
969 | source "drivers/cpufreq/Kconfig" | |
970 | ||
971 | config CPU_FREQ | |
972 | bool | |
973 | default n | |
974 | help | |
975 | If you want to enable this option, you should select the | |
976 | DPMC driver from Character Devices. | |
977 | endmenu | |
978 | ||
979 | endif | |
980 | ||
981 | source "net/Kconfig" | |
982 | ||
983 | source "drivers/Kconfig" | |
984 | ||
985 | source "fs/Kconfig" | |
986 | ||
74ce8322 | 987 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
988 | |
989 | source "security/Kconfig" | |
990 | ||
991 | source "crypto/Kconfig" | |
992 | ||
993 | source "lib/Kconfig" |