Commit | Line | Data |
---|---|---|
1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
9 | bool | |
10 | default n | |
11 | ||
12 | config FPU | |
13 | bool | |
14 | default n | |
15 | ||
16 | config RWSEM_GENERIC_SPINLOCK | |
17 | bool | |
18 | default y | |
19 | ||
20 | config RWSEM_XCHGADD_ALGORITHM | |
21 | bool | |
22 | default n | |
23 | ||
24 | config BLACKFIN | |
25 | bool | |
26 | default y | |
ec7748b5 | 27 | select HAVE_IDE |
42d4b839 | 28 | select HAVE_OPROFILE |
1394f032 | 29 | |
e3defffe AL |
30 | config ZONE_DMA |
31 | bool | |
32 | default y | |
33 | ||
1394f032 BW |
34 | config GENERIC_FIND_NEXT_BIT |
35 | bool | |
36 | default y | |
37 | ||
38 | config GENERIC_HWEIGHT | |
39 | bool | |
40 | default y | |
41 | ||
42 | config GENERIC_HARDIRQS | |
43 | bool | |
44 | default y | |
45 | ||
46 | config GENERIC_IRQ_PROBE | |
e4e9a7ad | 47 | bool |
1394f032 BW |
48 | default y |
49 | ||
b2d1583f | 50 | config GENERIC_GPIO |
1394f032 BW |
51 | bool |
52 | default y | |
53 | ||
54 | config FORCE_MAX_ZONEORDER | |
55 | int | |
56 | default "14" | |
57 | ||
58 | config GENERIC_CALIBRATE_DELAY | |
59 | bool | |
60 | default y | |
61 | ||
7d2284b0 MD |
62 | config HARDWARE_PM |
63 | def_bool y | |
64 | depends on OPROFILE | |
65 | ||
1394f032 BW |
66 | source "init/Kconfig" |
67 | source "kernel/Kconfig.preempt" | |
68 | ||
69 | menu "Blackfin Processor Options" | |
70 | ||
71 | comment "Processor and Board Settings" | |
72 | ||
73 | choice | |
74 | prompt "CPU" | |
75 | default BF533 | |
76 | ||
59003145 MH |
77 | config BF522 |
78 | bool "BF522" | |
79 | help | |
80 | BF522 Processor Support. | |
81 | ||
1545a111 MF |
82 | config BF523 |
83 | bool "BF523" | |
84 | help | |
85 | BF523 Processor Support. | |
86 | ||
87 | config BF524 | |
88 | bool "BF524" | |
89 | help | |
90 | BF524 Processor Support. | |
91 | ||
59003145 MH |
92 | config BF525 |
93 | bool "BF525" | |
94 | help | |
95 | BF525 Processor Support. | |
96 | ||
1545a111 MF |
97 | config BF526 |
98 | bool "BF526" | |
99 | help | |
100 | BF526 Processor Support. | |
101 | ||
59003145 MH |
102 | config BF527 |
103 | bool "BF527" | |
104 | help | |
105 | BF527 Processor Support. | |
106 | ||
1394f032 BW |
107 | config BF531 |
108 | bool "BF531" | |
109 | help | |
110 | BF531 Processor Support. | |
111 | ||
112 | config BF532 | |
113 | bool "BF532" | |
114 | help | |
115 | BF532 Processor Support. | |
116 | ||
117 | config BF533 | |
118 | bool "BF533" | |
119 | help | |
120 | BF533 Processor Support. | |
121 | ||
122 | config BF534 | |
123 | bool "BF534" | |
124 | help | |
125 | BF534 Processor Support. | |
126 | ||
127 | config BF536 | |
128 | bool "BF536" | |
129 | help | |
130 | BF536 Processor Support. | |
131 | ||
132 | config BF537 | |
133 | bool "BF537" | |
134 | help | |
135 | BF537 Processor Support. | |
136 | ||
24a07a12 RH |
137 | config BF542 |
138 | bool "BF542" | |
139 | help | |
140 | BF542 Processor Support. | |
141 | ||
142 | config BF544 | |
143 | bool "BF544" | |
144 | help | |
145 | BF544 Processor Support. | |
146 | ||
7c7fd170 MF |
147 | config BF547 |
148 | bool "BF547" | |
149 | help | |
150 | BF547 Processor Support. | |
151 | ||
24a07a12 RH |
152 | config BF548 |
153 | bool "BF548" | |
154 | help | |
155 | BF548 Processor Support. | |
156 | ||
157 | config BF549 | |
158 | bool "BF549" | |
159 | help | |
160 | BF549 Processor Support. | |
161 | ||
1394f032 BW |
162 | config BF561 |
163 | bool "BF561" | |
164 | help | |
165 | Not Supported Yet - Work in progress - BF561 Processor Support. | |
166 | ||
167 | endchoice | |
168 | ||
169 | choice | |
170 | prompt "Silicon Rev" | |
59003145 | 171 | default BF_REV_0_1 if BF527 |
1394f032 BW |
172 | default BF_REV_0_2 if BF537 |
173 | default BF_REV_0_3 if BF533 | |
24a07a12 RH |
174 | default BF_REV_0_0 if BF549 |
175 | ||
176 | config BF_REV_0_0 | |
177 | bool "0.0" | |
d07f4380 | 178 | depends on (BF52x || BF54x) |
59003145 MH |
179 | |
180 | config BF_REV_0_1 | |
d07f4380 MF |
181 | bool "0.1" |
182 | depends on (BF52x || BF54x) | |
1394f032 BW |
183 | |
184 | config BF_REV_0_2 | |
185 | bool "0.2" | |
186 | depends on (BF537 || BF536 || BF534) | |
187 | ||
188 | config BF_REV_0_3 | |
189 | bool "0.3" | |
190 | depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) | |
191 | ||
192 | config BF_REV_0_4 | |
193 | bool "0.4" | |
194 | depends on (BF561 || BF533 || BF532 || BF531) | |
195 | ||
196 | config BF_REV_0_5 | |
197 | bool "0.5" | |
198 | depends on (BF561 || BF533 || BF532 || BF531) | |
199 | ||
de3025f4 JZ |
200 | config BF_REV_ANY |
201 | bool "any" | |
202 | ||
203 | config BF_REV_NONE | |
204 | bool "none" | |
205 | ||
1394f032 BW |
206 | endchoice |
207 | ||
59003145 MH |
208 | config BF52x |
209 | bool | |
1545a111 | 210 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
211 | default y |
212 | ||
24a07a12 RH |
213 | config BF53x |
214 | bool | |
215 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
216 | default y | |
217 | ||
218 | config BF54x | |
219 | bool | |
7c7fd170 | 220 | depends on (BF542 || BF544 || BF547 || BF548 || BF549) |
24a07a12 RH |
221 | default y |
222 | ||
1394f032 BW |
223 | config MEM_GENERIC_BOARD |
224 | bool | |
225 | depends on GENERIC_BOARD | |
226 | default y | |
227 | ||
228 | config MEM_MT48LC64M4A2FB_7E | |
229 | bool | |
230 | depends on (BFIN533_STAMP) | |
231 | default y | |
232 | ||
233 | config MEM_MT48LC16M16A2TG_75 | |
234 | bool | |
235 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 | 236 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
9db144fe | 237 | || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) |
1394f032 BW |
238 | default y |
239 | ||
240 | config MEM_MT48LC32M8A2_75 | |
241 | bool | |
242 | depends on (BFIN537_STAMP || PNAV10) | |
243 | default y | |
244 | ||
245 | config MEM_MT48LC8M32B2B5_7 | |
246 | bool | |
247 | depends on (BFIN561_BLUETECHNIX_CM) | |
248 | default y | |
249 | ||
59003145 MH |
250 | config MEM_MT48LC32M16A2TG_75 |
251 | bool | |
8cc7117e | 252 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) |
59003145 MH |
253 | default y |
254 | ||
59003145 | 255 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
256 | source "arch/blackfin/mach-bf533/Kconfig" |
257 | source "arch/blackfin/mach-bf561/Kconfig" | |
258 | source "arch/blackfin/mach-bf537/Kconfig" | |
24a07a12 | 259 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
260 | |
261 | menu "Board customizations" | |
262 | ||
263 | config CMDLINE_BOOL | |
264 | bool "Default bootloader kernel arguments" | |
265 | ||
266 | config CMDLINE | |
267 | string "Initial kernel command string" | |
268 | depends on CMDLINE_BOOL | |
269 | default "console=ttyBF0,57600" | |
270 | help | |
271 | If you don't have a boot loader capable of passing a command line string | |
272 | to the kernel, you may specify one here. As a minimum, you should specify | |
273 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
274 | ||
5f004c20 MF |
275 | config BOOT_LOAD |
276 | hex "Kernel load address for booting" | |
277 | default "0x1000" | |
278 | range 0x1000 0x20000000 | |
279 | help | |
280 | This option allows you to set the load address of the kernel. | |
281 | This can be useful if you are on a board which has a small amount | |
282 | of memory or you wish to reserve some memory at the beginning of | |
283 | the address space. | |
284 | ||
285 | Note that you need to keep this value above 4k (0x1000) as this | |
286 | memory region is used to capture NULL pointer references as well | |
287 | as some core kernel functions. | |
288 | ||
8cc7117e MH |
289 | config ROM_BASE |
290 | hex "Kernel ROM Base" | |
291 | default "0x20040000" | |
292 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
293 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
294 | help | |
295 | ||
f16295e7 | 296 | comment "Clock/PLL Setup" |
1394f032 BW |
297 | |
298 | config CLKIN_HZ | |
2fb6cb41 | 299 | int "Frequency of the crystal on the board in Hz" |
1394f032 BW |
300 | default "11059200" if BFIN533_STAMP |
301 | default "27000000" if BFIN533_EZKIT | |
8cc7117e | 302 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) |
1394f032 BW |
303 | default "30000000" if BFIN561_EZKIT |
304 | default "24576000" if PNAV10 | |
5d1617b2 | 305 | default "10000000" if BFIN532_IP0X |
1394f032 BW |
306 | help |
307 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
308 | Warning: This value should match the crystal on the board. Otherwise, |
309 | peripherals won't work properly. | |
1394f032 | 310 | |
f16295e7 RG |
311 | config BFIN_KERNEL_CLOCK |
312 | bool "Re-program Clocks while Kernel boots?" | |
313 | default n | |
314 | help | |
315 | This option decides if kernel clocks are re-programed from the | |
316 | bootloader settings. If the clocks are not set, the SDRAM settings | |
317 | are also not changed, and the Bootloader does 100% of the hardware | |
318 | configuration. | |
319 | ||
320 | config PLL_BYPASS | |
e4e9a7ad MF |
321 | bool "Bypass PLL" |
322 | depends on BFIN_KERNEL_CLOCK | |
323 | default n | |
f16295e7 RG |
324 | |
325 | config CLKIN_HALF | |
326 | bool "Half Clock In" | |
327 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
328 | default n | |
329 | help | |
330 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
331 | ||
332 | config VCO_MULT | |
333 | int "VCO Multiplier" | |
334 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
335 | range 1 64 | |
336 | default "22" if BFIN533_EZKIT | |
337 | default "45" if BFIN533_STAMP | |
db68254f | 338 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM) |
f16295e7 | 339 | default "22" if BFIN533_BLUETECHNIX_CM |
9db144fe | 340 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 341 | default "20" if BFIN561_EZKIT |
8cc7117e | 342 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD) |
f16295e7 RG |
343 | help |
344 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
345 | PLL Frequency = (Crystal Frequency) * (this setting) | |
346 | ||
347 | choice | |
348 | prompt "Core Clock Divider" | |
349 | depends on BFIN_KERNEL_CLOCK | |
350 | default CCLK_DIV_1 | |
351 | help | |
352 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
353 | Core Frequency = (PLL frequency) / (this setting) | |
354 | ||
355 | config CCLK_DIV_1 | |
356 | bool "1" | |
357 | ||
358 | config CCLK_DIV_2 | |
359 | bool "2" | |
360 | ||
361 | config CCLK_DIV_4 | |
362 | bool "4" | |
363 | ||
364 | config CCLK_DIV_8 | |
365 | bool "8" | |
366 | endchoice | |
367 | ||
368 | config SCLK_DIV | |
369 | int "System Clock Divider" | |
370 | depends on BFIN_KERNEL_CLOCK | |
371 | range 1 15 | |
5f004c20 | 372 | default 5 |
f16295e7 RG |
373 | help |
374 | This sets the frequency of the system clock (including SDRAM or DDR). | |
375 | This can be between 1 and 15 | |
376 | System Clock = (PLL frequency) / (this setting) | |
377 | ||
5f004c20 MF |
378 | choice |
379 | prompt "DDR SDRAM Chip Type" | |
380 | depends on BFIN_KERNEL_CLOCK | |
381 | depends on BF54x | |
382 | default MEM_MT46V32M16_5B | |
383 | ||
384 | config MEM_MT46V32M16_6T | |
385 | bool "MT46V32M16_6T" | |
386 | ||
387 | config MEM_MT46V32M16_5B | |
388 | bool "MT46V32M16_5B" | |
389 | endchoice | |
390 | ||
7eb2c23f MF |
391 | config MAX_MEM_SIZE |
392 | int "Max SDRAM Memory Size in MBytes" | |
393 | depends on !MPU | |
394 | default 512 | |
395 | help | |
396 | This is the max memory size that the kernel will create CPLB | |
397 | tables for. Your system will not be able to handle any more. | |
398 | ||
f16295e7 RG |
399 | # |
400 | # Max & Min Speeds for various Chips | |
401 | # | |
402 | config MAX_VCO_HZ | |
403 | int | |
404 | default 600000000 if BF522 | |
1545a111 MF |
405 | default 400000000 if BF523 |
406 | default 400000000 if BF524 | |
f16295e7 | 407 | default 600000000 if BF525 |
1545a111 | 408 | default 400000000 if BF526 |
f16295e7 RG |
409 | default 600000000 if BF527 |
410 | default 400000000 if BF531 | |
411 | default 400000000 if BF532 | |
412 | default 750000000 if BF533 | |
413 | default 500000000 if BF534 | |
414 | default 400000000 if BF536 | |
415 | default 600000000 if BF537 | |
f72eecb9 RG |
416 | default 533333333 if BF538 |
417 | default 533333333 if BF539 | |
f16295e7 | 418 | default 600000000 if BF542 |
f72eecb9 | 419 | default 533333333 if BF544 |
1545a111 MF |
420 | default 600000000 if BF547 |
421 | default 600000000 if BF548 | |
f72eecb9 | 422 | default 533333333 if BF549 |
f16295e7 RG |
423 | default 600000000 if BF561 |
424 | ||
425 | config MIN_VCO_HZ | |
426 | int | |
427 | default 50000000 | |
428 | ||
429 | config MAX_SCLK_HZ | |
430 | int | |
f72eecb9 | 431 | default 133333333 |
f16295e7 RG |
432 | |
433 | config MIN_SCLK_HZ | |
434 | int | |
435 | default 27000000 | |
436 | ||
437 | comment "Kernel Timer/Scheduler" | |
438 | ||
439 | source kernel/Kconfig.hz | |
440 | ||
8b5f79f9 VM |
441 | config GENERIC_TIME |
442 | bool "Generic time" | |
443 | default y | |
444 | ||
445 | config GENERIC_CLOCKEVENTS | |
446 | bool "Generic clock events" | |
447 | depends on GENERIC_TIME | |
448 | default y | |
449 | ||
450 | config CYCLES_CLOCKSOURCE | |
451 | bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)" | |
452 | depends on EXPERIMENTAL | |
453 | depends on GENERIC_CLOCKEVENTS | |
454 | depends on !BFIN_SCRATCH_REG_CYCLES | |
455 | default n | |
456 | help | |
457 | If you say Y here, you will enable support for using the 'cycles' | |
458 | registers as a clock source. Doing so means you will be unable to | |
459 | safely write to the 'cycles' register during runtime. You will | |
460 | still be able to read it (such as for performance monitoring), but | |
461 | writing the registers will most likely crash the kernel. | |
462 | ||
463 | source kernel/time/Kconfig | |
464 | ||
5f004c20 | 465 | comment "Misc" |
971d5bc4 | 466 | |
f0b5d12f MF |
467 | choice |
468 | prompt "Blackfin Exception Scratch Register" | |
469 | default BFIN_SCRATCH_REG_RETN | |
470 | help | |
471 | Select the resource to reserve for the Exception handler: | |
472 | - RETN: Non-Maskable Interrupt (NMI) | |
473 | - RETE: Exception Return (JTAG/ICE) | |
474 | - CYCLES: Performance counter | |
475 | ||
476 | If you are unsure, please select "RETN". | |
477 | ||
478 | config BFIN_SCRATCH_REG_RETN | |
479 | bool "RETN" | |
480 | help | |
481 | Use the RETN register in the Blackfin exception handler | |
482 | as a stack scratch register. This means you cannot | |
483 | safely use NMI on the Blackfin while running Linux, but | |
484 | you can debug the system with a JTAG ICE and use the | |
485 | CYCLES performance registers. | |
486 | ||
487 | If you are unsure, please select "RETN". | |
488 | ||
489 | config BFIN_SCRATCH_REG_RETE | |
490 | bool "RETE" | |
491 | help | |
492 | Use the RETE register in the Blackfin exception handler | |
493 | as a stack scratch register. This means you cannot | |
494 | safely use a JTAG ICE while debugging a Blackfin board, | |
495 | but you can safely use the CYCLES performance registers | |
496 | and the NMI. | |
497 | ||
498 | If you are unsure, please select "RETN". | |
499 | ||
500 | config BFIN_SCRATCH_REG_CYCLES | |
501 | bool "CYCLES" | |
502 | help | |
503 | Use the CYCLES register in the Blackfin exception handler | |
504 | as a stack scratch register. This means you cannot | |
505 | safely use the CYCLES performance registers on a Blackfin | |
506 | board at anytime, but you can debug the system with a JTAG | |
507 | ICE and use the NMI. | |
508 | ||
509 | If you are unsure, please select "RETN". | |
510 | ||
511 | endchoice | |
512 | ||
1394f032 BW |
513 | endmenu |
514 | ||
515 | ||
516 | menu "Blackfin Kernel Optimizations" | |
517 | ||
1394f032 BW |
518 | comment "Memory Optimizations" |
519 | ||
520 | config I_ENTRY_L1 | |
521 | bool "Locate interrupt entry code in L1 Memory" | |
522 | default y | |
523 | help | |
01dd2fbf ML |
524 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
525 | into L1 instruction memory. (less latency) | |
1394f032 BW |
526 | |
527 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 528 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
529 | default y |
530 | help | |
01dd2fbf | 531 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 532 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 533 | (less latency) |
1394f032 BW |
534 | |
535 | config DO_IRQ_L1 | |
536 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
537 | default y | |
538 | help | |
01dd2fbf ML |
539 | If enabled, the frequently called do_irq dispatcher function is linked |
540 | into L1 instruction memory. (less latency) | |
1394f032 BW |
541 | |
542 | config CORE_TIMER_IRQ_L1 | |
543 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
544 | default y | |
545 | help | |
01dd2fbf ML |
546 | If enabled, the frequently called timer_interrupt() function is linked |
547 | into L1 instruction memory. (less latency) | |
1394f032 BW |
548 | |
549 | config IDLE_L1 | |
550 | bool "Locate frequently idle function in L1 Memory" | |
551 | default y | |
552 | help | |
01dd2fbf ML |
553 | If enabled, the frequently called idle function is linked |
554 | into L1 instruction memory. (less latency) | |
1394f032 BW |
555 | |
556 | config SCHEDULE_L1 | |
557 | bool "Locate kernel schedule function in L1 Memory" | |
558 | default y | |
559 | help | |
01dd2fbf ML |
560 | If enabled, the frequently called kernel schedule is linked |
561 | into L1 instruction memory. (less latency) | |
1394f032 BW |
562 | |
563 | config ARITHMETIC_OPS_L1 | |
564 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
565 | default y | |
566 | help | |
01dd2fbf ML |
567 | If enabled, arithmetic functions are linked |
568 | into L1 instruction memory. (less latency) | |
1394f032 BW |
569 | |
570 | config ACCESS_OK_L1 | |
571 | bool "Locate access_ok function in L1 Memory" | |
572 | default y | |
573 | help | |
01dd2fbf ML |
574 | If enabled, the access_ok function is linked |
575 | into L1 instruction memory. (less latency) | |
1394f032 BW |
576 | |
577 | config MEMSET_L1 | |
578 | bool "Locate memset function in L1 Memory" | |
579 | default y | |
580 | help | |
01dd2fbf ML |
581 | If enabled, the memset function is linked |
582 | into L1 instruction memory. (less latency) | |
1394f032 BW |
583 | |
584 | config MEMCPY_L1 | |
585 | bool "Locate memcpy function in L1 Memory" | |
586 | default y | |
587 | help | |
01dd2fbf ML |
588 | If enabled, the memcpy function is linked |
589 | into L1 instruction memory. (less latency) | |
1394f032 BW |
590 | |
591 | config SYS_BFIN_SPINLOCK_L1 | |
592 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
593 | default y | |
594 | help | |
01dd2fbf ML |
595 | If enabled, sys_bfin_spinlock function is linked |
596 | into L1 instruction memory. (less latency) | |
1394f032 BW |
597 | |
598 | config IP_CHECKSUM_L1 | |
599 | bool "Locate IP Checksum function in L1 Memory" | |
600 | default n | |
601 | help | |
01dd2fbf ML |
602 | If enabled, the IP Checksum function is linked |
603 | into L1 instruction memory. (less latency) | |
1394f032 BW |
604 | |
605 | config CACHELINE_ALIGNED_L1 | |
606 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
607 | default y if !BF54x |
608 | default n if BF54x | |
1394f032 BW |
609 | depends on !BF531 |
610 | help | |
01dd2fbf ML |
611 | If enabled, cacheline_anligned data is linked |
612 | into L1 data memory. (less latency) | |
1394f032 BW |
613 | |
614 | config SYSCALL_TAB_L1 | |
615 | bool "Locate Syscall Table L1 Data Memory" | |
616 | default n | |
617 | depends on !BF531 | |
618 | help | |
01dd2fbf ML |
619 | If enabled, the Syscall LUT is linked |
620 | into L1 data memory. (less latency) | |
1394f032 BW |
621 | |
622 | config CPLB_SWITCH_TAB_L1 | |
623 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
624 | default n | |
625 | depends on !BF531 | |
626 | help | |
01dd2fbf ML |
627 | If enabled, the CPLB Switch Tables are linked |
628 | into L1 data memory. (less latency) | |
1394f032 | 629 | |
ca87b7ad GY |
630 | config APP_STACK_L1 |
631 | bool "Support locating application stack in L1 Scratch Memory" | |
632 | default y | |
633 | help | |
634 | If enabled the application stack can be located in L1 | |
635 | scratch memory (less latency). | |
636 | ||
637 | Currently only works with FLAT binaries. | |
638 | ||
251383c7 RG |
639 | comment "Speed Optimizations" |
640 | config BFIN_INS_LOWOVERHEAD | |
641 | bool "ins[bwl] low overhead, higher interrupt latency" | |
642 | default y | |
643 | help | |
644 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
645 | they can be interrupted at any time (even after they have been issued | |
646 | on to the external bus), and re-issued after the interrupt occurs. | |
647 | For memory - this is not a big deal, since memory does not change if | |
648 | it sees a read. | |
649 | ||
650 | If a FIFO is sitting on the end of the read, it will see two reads, | |
651 | when the core only sees one since the FIFO receives both the read | |
652 | which is cancelled (and not delivered to the core) and the one which | |
653 | is re-issued (which is delivered to the core). | |
654 | ||
655 | To solve this, interrupts are turned off before reads occur to | |
656 | I/O space. This option controls which the overhead/latency of | |
657 | controlling interrupts during this time | |
658 | "n" turns interrupts off every read | |
659 | (higher overhead, but lower interrupt latency) | |
660 | "y" turns interrupts off every loop | |
661 | (low overhead, but longer interrupt latency) | |
662 | ||
663 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
664 | interrupt latency issues, it is safe and OK to turn this off. | |
665 | ||
1394f032 BW |
666 | endmenu |
667 | ||
668 | ||
669 | choice | |
670 | prompt "Kernel executes from" | |
671 | help | |
672 | Choose the memory type that the kernel will be running in. | |
673 | ||
674 | config RAMKERNEL | |
675 | bool "RAM" | |
676 | help | |
677 | The kernel will be resident in RAM when running. | |
678 | ||
679 | config ROMKERNEL | |
680 | bool "ROM" | |
681 | help | |
682 | The kernel will be resident in FLASH/ROM when running. | |
683 | ||
684 | endchoice | |
685 | ||
686 | source "mm/Kconfig" | |
687 | ||
780431e3 MF |
688 | config BFIN_GPTIMERS |
689 | tristate "Enable Blackfin General Purpose Timers API" | |
690 | default n | |
691 | help | |
692 | Enable support for the General Purpose Timers API. If you | |
693 | are unsure, say N. | |
694 | ||
695 | To compile this driver as a module, choose M here: the module | |
696 | will be called gptimers.ko. | |
697 | ||
1394f032 BW |
698 | config BFIN_DMA_5XX |
699 | bool "Enable DMA Support" | |
59003145 | 700 | depends on (BF52x || BF53x || BF561 || BF54x) |
1394f032 BW |
701 | default y |
702 | help | |
703 | DMA driver for BF5xx. | |
704 | ||
705 | choice | |
706 | prompt "Uncached SDRAM region" | |
707 | default DMA_UNCACHED_1M | |
247537b9 | 708 | depends on BFIN_DMA_5XX |
86ad7932 CC |
709 | config DMA_UNCACHED_4M |
710 | bool "Enable 4M DMA region" | |
1394f032 BW |
711 | config DMA_UNCACHED_2M |
712 | bool "Enable 2M DMA region" | |
713 | config DMA_UNCACHED_1M | |
714 | bool "Enable 1M DMA region" | |
715 | config DMA_UNCACHED_NONE | |
716 | bool "Disable DMA region" | |
717 | endchoice | |
718 | ||
719 | ||
720 | comment "Cache Support" | |
3bebca2d | 721 | config BFIN_ICACHE |
1394f032 | 722 | bool "Enable ICACHE" |
3bebca2d | 723 | config BFIN_DCACHE |
1394f032 | 724 | bool "Enable DCACHE" |
3bebca2d | 725 | config BFIN_DCACHE_BANKA |
1394f032 | 726 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 727 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 728 | default n |
3bebca2d RG |
729 | config BFIN_ICACHE_LOCK |
730 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
731 | |
732 | choice | |
733 | prompt "Policy" | |
3bebca2d RG |
734 | depends on BFIN_DCACHE |
735 | default BFIN_WB | |
736 | config BFIN_WB | |
1394f032 BW |
737 | bool "Write back" |
738 | help | |
739 | Write Back Policy: | |
740 | Cached data will be written back to SDRAM only when needed. | |
741 | This can give a nice increase in performance, but beware of | |
742 | broken drivers that do not properly invalidate/flush their | |
743 | cache. | |
744 | ||
745 | Write Through Policy: | |
746 | Cached data will always be written back to SDRAM when the | |
747 | cache is updated. This is a completely safe setting, but | |
748 | performance is worse than Write Back. | |
749 | ||
750 | If you are unsure of the options and you want to be safe, | |
751 | then go with Write Through. | |
752 | ||
3bebca2d | 753 | config BFIN_WT |
1394f032 BW |
754 | bool "Write through" |
755 | help | |
756 | Write Back Policy: | |
757 | Cached data will be written back to SDRAM only when needed. | |
758 | This can give a nice increase in performance, but beware of | |
759 | broken drivers that do not properly invalidate/flush their | |
760 | cache. | |
761 | ||
762 | Write Through Policy: | |
763 | Cached data will always be written back to SDRAM when the | |
764 | cache is updated. This is a completely safe setting, but | |
765 | performance is worse than Write Back. | |
766 | ||
767 | If you are unsure of the options and you want to be safe, | |
768 | then go with Write Through. | |
769 | ||
770 | endchoice | |
771 | ||
b97b8a99 BS |
772 | config MPU |
773 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
774 | default n | |
775 | help | |
776 | Use the processor's MPU to protect applications from accessing | |
777 | memory they do not own. This comes at a performance penalty | |
778 | and is recommended only for debugging. | |
779 | ||
1394f032 BW |
780 | comment "Asynchonous Memory Configuration" |
781 | ||
ddf416b2 | 782 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
783 | config C_AMCKEN |
784 | bool "Enable CLKOUT" | |
785 | default y | |
786 | ||
787 | config C_CDPRIO | |
788 | bool "DMA has priority over core for ext. accesses" | |
789 | default n | |
790 | ||
791 | config C_B0PEN | |
792 | depends on BF561 | |
793 | bool "Bank 0 16 bit packing enable" | |
794 | default y | |
795 | ||
796 | config C_B1PEN | |
797 | depends on BF561 | |
798 | bool "Bank 1 16 bit packing enable" | |
799 | default y | |
800 | ||
801 | config C_B2PEN | |
802 | depends on BF561 | |
803 | bool "Bank 2 16 bit packing enable" | |
804 | default y | |
805 | ||
806 | config C_B3PEN | |
807 | depends on BF561 | |
808 | bool "Bank 3 16 bit packing enable" | |
809 | default n | |
810 | ||
811 | choice | |
812 | prompt"Enable Asynchonous Memory Banks" | |
813 | default C_AMBEN_ALL | |
814 | ||
815 | config C_AMBEN | |
816 | bool "Disable All Banks" | |
817 | ||
818 | config C_AMBEN_B0 | |
819 | bool "Enable Bank 0" | |
820 | ||
821 | config C_AMBEN_B0_B1 | |
822 | bool "Enable Bank 0 & 1" | |
823 | ||
824 | config C_AMBEN_B0_B1_B2 | |
825 | bool "Enable Bank 0 & 1 & 2" | |
826 | ||
827 | config C_AMBEN_ALL | |
828 | bool "Enable All Banks" | |
829 | endchoice | |
830 | endmenu | |
831 | ||
832 | menu "EBIU_AMBCTL Control" | |
833 | config BANK_0 | |
834 | hex "Bank 0" | |
835 | default 0x7BB0 | |
836 | ||
837 | config BANK_1 | |
838 | hex "Bank 1" | |
839 | default 0x7BB0 | |
197fba56 | 840 | default 0x5558 if BF54x |
1394f032 BW |
841 | |
842 | config BANK_2 | |
843 | hex "Bank 2" | |
844 | default 0x7BB0 | |
845 | ||
846 | config BANK_3 | |
847 | hex "Bank 3" | |
848 | default 0x99B3 | |
849 | endmenu | |
850 | ||
e40540b3 SZ |
851 | config EBIU_MBSCTLVAL |
852 | hex "EBIU Bank Select Control Register" | |
853 | depends on BF54x | |
854 | default 0 | |
855 | ||
856 | config EBIU_MODEVAL | |
857 | hex "Flash Memory Mode Control Register" | |
858 | depends on BF54x | |
859 | default 1 | |
860 | ||
861 | config EBIU_FCTLVAL | |
862 | hex "Flash Memory Bank Control Register" | |
863 | depends on BF54x | |
864 | default 6 | |
1394f032 BW |
865 | endmenu |
866 | ||
867 | ############################################################################# | |
868 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
869 | ||
870 | config PCI | |
871 | bool "PCI support" | |
a95ca3b2 | 872 | depends on BROKEN |
1394f032 BW |
873 | help |
874 | Support for PCI bus. | |
875 | ||
876 | source "drivers/pci/Kconfig" | |
877 | ||
878 | config HOTPLUG | |
879 | bool "Support for hot-pluggable device" | |
880 | help | |
881 | Say Y here if you want to plug devices into your computer while | |
882 | the system is running, and be able to use them quickly. In many | |
883 | cases, the devices can likewise be unplugged at any time too. | |
884 | ||
885 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
886 | size devices such as network cards, modems or hard drives which are | |
887 | plugged into slots found on all modern laptop computers. Another | |
888 | example, used on modern desktops as well as laptops, is USB. | |
889 | ||
a81792f6 JB |
890 | Enable HOTPLUG and build a modular kernel. Get agent software |
891 | (from <http://linux-hotplug.sourceforge.net/>) and install it. | |
1394f032 BW |
892 | Then your kernel will automatically call out to a user mode "policy |
893 | agent" (/sbin/hotplug) to load modules and set up software needed | |
894 | to use devices as you hotplug them. | |
895 | ||
896 | source "drivers/pcmcia/Kconfig" | |
897 | ||
898 | source "drivers/pci/hotplug/Kconfig" | |
899 | ||
900 | endmenu | |
901 | ||
902 | menu "Executable file formats" | |
903 | ||
904 | source "fs/Kconfig.binfmt" | |
905 | ||
906 | endmenu | |
907 | ||
908 | menu "Power management options" | |
909 | source "kernel/power/Kconfig" | |
910 | ||
f4cb5700 JB |
911 | config ARCH_SUSPEND_POSSIBLE |
912 | def_bool y | |
913 | depends on !SMP | |
914 | ||
1394f032 | 915 | choice |
1efc80b5 | 916 | prompt "Standby Power Saving Mode" |
1394f032 | 917 | depends on PM |
cfefe3c6 MH |
918 | default PM_BFIN_SLEEP_DEEPER |
919 | config PM_BFIN_SLEEP_DEEPER | |
920 | bool "Sleep Deeper" | |
921 | help | |
922 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
923 | power dissipation by disabling the clock to the processor core (CCLK). | |
924 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
925 | to 0.85 V to provide the greatest power savings, while preserving the | |
926 | processor state. | |
927 | The PLL and system clock (SCLK) continue to operate at a very low | |
928 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
929 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
930 | such as GPIO interrupt or RTC activity wakes up the processor. | |
931 | Various Peripherals such as UART, SPORT, PPI may not function as | |
932 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
933 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
934 | ||
1efc80b5 MH |
935 | If unsure, select "Sleep Deeper". |
936 | ||
cfefe3c6 MH |
937 | config PM_BFIN_SLEEP |
938 | bool "Sleep" | |
939 | help | |
940 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
941 | dissipation by disabling the clock to the processor core (CCLK). | |
942 | The PLL and system clock (SCLK), however, continue to operate in | |
943 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
944 | up the processor. When in the sleep mode, system DMA access to L1 |
945 | memory is not supported. | |
946 | ||
947 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 948 | endchoice |
1394f032 | 949 | |
1394f032 | 950 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 951 | bool "Allow Wakeup from Standby by GPIO" |
1394f032 BW |
952 | |
953 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 954 | int "GPIO number" |
1394f032 BW |
955 | range 0 47 |
956 | depends on PM_WAKEUP_BY_GPIO | |
957 | default 2 if BFIN537_STAMP | |
958 | ||
959 | choice | |
960 | prompt "GPIO Polarity" | |
961 | depends on PM_WAKEUP_BY_GPIO | |
962 | default PM_WAKEUP_GPIO_POLAR_H | |
963 | config PM_WAKEUP_GPIO_POLAR_H | |
964 | bool "Active High" | |
965 | config PM_WAKEUP_GPIO_POLAR_L | |
966 | bool "Active Low" | |
967 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
968 | bool "Falling EDGE" | |
969 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
970 | bool "Rising EDGE" | |
971 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
972 | bool "Both EDGE" | |
973 | endchoice | |
974 | ||
1efc80b5 MH |
975 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
976 | depends on PM | |
977 | ||
1efc80b5 MH |
978 | config PM_BFIN_WAKE_PH6 |
979 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
980 | depends on PM && (BF52x || BF534 || BF536 || BF537) | |
981 | default n | |
982 | help | |
983 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
984 | ||
1efc80b5 MH |
985 | config PM_BFIN_WAKE_GP |
986 | bool "Allow Wake-Up from GPIOs" | |
987 | depends on PM && BF54x | |
988 | default n | |
989 | help | |
990 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
1394f032 BW |
991 | endmenu |
992 | ||
1394f032 BW |
993 | menu "CPU Frequency scaling" |
994 | ||
995 | source "drivers/cpufreq/Kconfig" | |
996 | ||
14b03204 MH |
997 | config CPU_VOLTAGE |
998 | bool "CPU Voltage scaling" | |
999 | depends on EXPERIMENTAL | |
1000 | depends on CPU_FREQ | |
1001 | default n | |
1002 | help | |
1003 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1004 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
1005 | manuals. There is a theoretical risk that during VDDINT transitions | |
1006 | the PLL may unlock. | |
1007 | ||
1394f032 BW |
1008 | endmenu |
1009 | ||
1394f032 BW |
1010 | source "net/Kconfig" |
1011 | ||
1012 | source "drivers/Kconfig" | |
1013 | ||
1014 | source "fs/Kconfig" | |
1015 | ||
74ce8322 | 1016 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1017 | |
1018 | source "security/Kconfig" | |
1019 | ||
1020 | source "crypto/Kconfig" | |
1021 | ||
1022 | source "lib/Kconfig" |