Commit | Line | Data |
---|---|---|
9e1b9b80 AJ |
1 | config SYMBOL_PREFIX |
2 | string | |
3 | default "_" | |
4 | ||
1394f032 | 5 | config MMU |
bac7d89e | 6 | def_bool n |
1394f032 BW |
7 | |
8 | config FPU | |
bac7d89e | 9 | def_bool n |
1394f032 BW |
10 | |
11 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 12 | def_bool y |
1394f032 BW |
13 | |
14 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 15 | def_bool n |
1394f032 BW |
16 | |
17 | config BLACKFIN | |
bac7d89e | 18 | def_bool y |
652afdc3 | 19 | select HAVE_ARCH_KGDB |
e8f263df | 20 | select HAVE_ARCH_TRACEHOOK |
f5074429 MF |
21 | select HAVE_DYNAMIC_FTRACE |
22 | select HAVE_FTRACE_MCOUNT_RECORD | |
1ee76d7e | 23 | select HAVE_FUNCTION_GRAPH_TRACER |
1c873be7 | 24 | select HAVE_FUNCTION_TRACER |
aebfef03 | 25 | select HAVE_FUNCTION_TRACE_MCOUNT_TEST |
ec7748b5 | 26 | select HAVE_IDE |
7db79172 | 27 | select HAVE_IRQ_WORK |
d86bfb16 BS |
28 | select HAVE_KERNEL_GZIP if RAMKERNEL |
29 | select HAVE_KERNEL_BZIP2 if RAMKERNEL | |
30 | select HAVE_KERNEL_LZMA if RAMKERNEL | |
67df6cc6 | 31 | select HAVE_KERNEL_LZO if RAMKERNEL |
42d4b839 | 32 | select HAVE_OPROFILE |
7db79172 | 33 | select HAVE_PERF_EVENTS |
7563bbf8 | 34 | select ARCH_HAVE_CUSTOM_GPIO_H |
a4f0b32c | 35 | select ARCH_WANT_OPTIONAL_GPIOLIB |
af1839eb | 36 | select HAVE_UID16 |
c1d7e01d | 37 | select ARCH_WANT_IPC_PARSE_VERSION |
7b028863 | 38 | select HAVE_GENERIC_HARDIRQS |
bee18beb | 39 | select GENERIC_ATOMIC64 |
7b028863 TG |
40 | select GENERIC_IRQ_PROBE |
41 | select IRQ_PER_CPU if SMP | |
50888469 | 42 | select USE_GENERIC_SMP_HELPERS if SMP |
d314d74c | 43 | select HAVE_NMI_WATCHDOG if NMI_WATCHDOG |
6bba2682 | 44 | select GENERIC_SMP_IDLE_THREAD |
dfbaec06 | 45 | select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS |
1394f032 | 46 | |
ddf9ddac MF |
47 | config GENERIC_CSUM |
48 | def_bool y | |
49 | ||
70f12567 MF |
50 | config GENERIC_BUG |
51 | def_bool y | |
52 | depends on BUG | |
53 | ||
e3defffe | 54 | config ZONE_DMA |
bac7d89e | 55 | def_bool y |
e3defffe | 56 | |
b2d1583f | 57 | config GENERIC_GPIO |
bac7d89e | 58 | def_bool y |
1394f032 BW |
59 | |
60 | config FORCE_MAX_ZONEORDER | |
61 | int | |
62 | default "14" | |
63 | ||
64 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 65 | def_bool y |
1394f032 | 66 | |
6fa68e7a MF |
67 | config LOCKDEP_SUPPORT |
68 | def_bool y | |
69 | ||
c7b412f4 MF |
70 | config STACKTRACE_SUPPORT |
71 | def_bool y | |
72 | ||
8f86001f MF |
73 | config TRACE_IRQFLAGS_SUPPORT |
74 | def_bool y | |
1394f032 | 75 | |
1394f032 | 76 | source "init/Kconfig" |
dc52ddc0 | 77 | |
1394f032 BW |
78 | source "kernel/Kconfig.preempt" |
79 | ||
dc52ddc0 MH |
80 | source "kernel/Kconfig.freezer" |
81 | ||
1394f032 BW |
82 | menu "Blackfin Processor Options" |
83 | ||
84 | comment "Processor and Board Settings" | |
85 | ||
86 | choice | |
87 | prompt "CPU" | |
88 | default BF533 | |
89 | ||
2f6f4bcd BW |
90 | config BF512 |
91 | bool "BF512" | |
92 | help | |
93 | BF512 Processor Support. | |
94 | ||
95 | config BF514 | |
96 | bool "BF514" | |
97 | help | |
98 | BF514 Processor Support. | |
99 | ||
100 | config BF516 | |
101 | bool "BF516" | |
102 | help | |
103 | BF516 Processor Support. | |
104 | ||
105 | config BF518 | |
106 | bool "BF518" | |
107 | help | |
108 | BF518 Processor Support. | |
109 | ||
59003145 MH |
110 | config BF522 |
111 | bool "BF522" | |
112 | help | |
113 | BF522 Processor Support. | |
114 | ||
1545a111 MF |
115 | config BF523 |
116 | bool "BF523" | |
117 | help | |
118 | BF523 Processor Support. | |
119 | ||
120 | config BF524 | |
121 | bool "BF524" | |
122 | help | |
123 | BF524 Processor Support. | |
124 | ||
59003145 MH |
125 | config BF525 |
126 | bool "BF525" | |
127 | help | |
128 | BF525 Processor Support. | |
129 | ||
1545a111 MF |
130 | config BF526 |
131 | bool "BF526" | |
132 | help | |
133 | BF526 Processor Support. | |
134 | ||
59003145 MH |
135 | config BF527 |
136 | bool "BF527" | |
137 | help | |
138 | BF527 Processor Support. | |
139 | ||
1394f032 BW |
140 | config BF531 |
141 | bool "BF531" | |
142 | help | |
143 | BF531 Processor Support. | |
144 | ||
145 | config BF532 | |
146 | bool "BF532" | |
147 | help | |
148 | BF532 Processor Support. | |
149 | ||
150 | config BF533 | |
151 | bool "BF533" | |
152 | help | |
153 | BF533 Processor Support. | |
154 | ||
155 | config BF534 | |
156 | bool "BF534" | |
157 | help | |
158 | BF534 Processor Support. | |
159 | ||
160 | config BF536 | |
161 | bool "BF536" | |
162 | help | |
163 | BF536 Processor Support. | |
164 | ||
165 | config BF537 | |
166 | bool "BF537" | |
167 | help | |
168 | BF537 Processor Support. | |
169 | ||
dc26aec2 MH |
170 | config BF538 |
171 | bool "BF538" | |
172 | help | |
173 | BF538 Processor Support. | |
174 | ||
175 | config BF539 | |
176 | bool "BF539" | |
177 | help | |
178 | BF539 Processor Support. | |
179 | ||
5df326ac | 180 | config BF542_std |
24a07a12 RH |
181 | bool "BF542" |
182 | help | |
183 | BF542 Processor Support. | |
184 | ||
2f89c063 MF |
185 | config BF542M |
186 | bool "BF542m" | |
187 | help | |
188 | BF542 Processor Support. | |
189 | ||
5df326ac | 190 | config BF544_std |
24a07a12 RH |
191 | bool "BF544" |
192 | help | |
193 | BF544 Processor Support. | |
194 | ||
2f89c063 MF |
195 | config BF544M |
196 | bool "BF544m" | |
197 | help | |
198 | BF544 Processor Support. | |
199 | ||
5df326ac | 200 | config BF547_std |
7c7fd170 MF |
201 | bool "BF547" |
202 | help | |
203 | BF547 Processor Support. | |
204 | ||
2f89c063 MF |
205 | config BF547M |
206 | bool "BF547m" | |
207 | help | |
208 | BF547 Processor Support. | |
209 | ||
5df326ac | 210 | config BF548_std |
24a07a12 RH |
211 | bool "BF548" |
212 | help | |
213 | BF548 Processor Support. | |
214 | ||
2f89c063 MF |
215 | config BF548M |
216 | bool "BF548m" | |
217 | help | |
218 | BF548 Processor Support. | |
219 | ||
5df326ac | 220 | config BF549_std |
24a07a12 RH |
221 | bool "BF549" |
222 | help | |
223 | BF549 Processor Support. | |
224 | ||
2f89c063 MF |
225 | config BF549M |
226 | bool "BF549m" | |
227 | help | |
228 | BF549 Processor Support. | |
229 | ||
1394f032 BW |
230 | config BF561 |
231 | bool "BF561" | |
232 | help | |
cd88b4dc | 233 | BF561 Processor Support. |
1394f032 | 234 | |
b5affb01 BL |
235 | config BF609 |
236 | bool "BF609" | |
237 | select CLKDEV_LOOKUP | |
238 | help | |
239 | BF609 Processor Support. | |
240 | ||
1394f032 BW |
241 | endchoice |
242 | ||
46fa5eec GY |
243 | config SMP |
244 | depends on BF561 | |
0d152c27 | 245 | select TICKSOURCE_CORETMR |
46fa5eec GY |
246 | bool "Symmetric multi-processing support" |
247 | ---help--- | |
248 | This enables support for systems with more than one CPU, | |
249 | like the dual core BF561. If you have a system with only one | |
250 | CPU, say N. If you have a system with more than one CPU, say Y. | |
251 | ||
252 | If you don't know what to do here, say N. | |
253 | ||
254 | config NR_CPUS | |
255 | int | |
256 | depends on SMP | |
257 | default 2 if BF561 | |
258 | ||
0b39db28 GY |
259 | config HOTPLUG_CPU |
260 | bool "Support for hot-pluggable CPUs" | |
261 | depends on SMP && HOTPLUG | |
262 | default y | |
263 | ||
0c0497c2 MF |
264 | config BF_REV_MIN |
265 | int | |
b5affb01 | 266 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x |
0c0497c2 | 267 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 268 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 269 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
270 | |
271 | config BF_REV_MAX | |
272 | int | |
b5affb01 | 273 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x |
2f89c063 | 274 | default 3 if (BF537 || BF536 || BF534 || BF54xM) |
2f6f4bcd | 275 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
276 | default 6 if (BF533 || BF532 || BF531) |
277 | ||
1394f032 BW |
278 | choice |
279 | prompt "Silicon Rev" | |
b5affb01 | 280 | default BF_REV_0_0 if (BF51x || BF52x || BF60x) |
f8b55651 | 281 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) |
2f89c063 | 282 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
283 | |
284 | config BF_REV_0_0 | |
285 | bool "0.0" | |
b5affb01 | 286 | depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x) |
59003145 MH |
287 | |
288 | config BF_REV_0_1 | |
d07f4380 | 289 | bool "0.1" |
3d15f302 | 290 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
291 | |
292 | config BF_REV_0_2 | |
293 | bool "0.2" | |
8060bb6f | 294 | depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
295 | |
296 | config BF_REV_0_3 | |
297 | bool "0.3" | |
2f89c063 | 298 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
299 | |
300 | config BF_REV_0_4 | |
301 | bool "0.4" | |
ee5124e3 | 302 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x) |
1394f032 BW |
303 | |
304 | config BF_REV_0_5 | |
305 | bool "0.5" | |
dc26aec2 | 306 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 307 | |
49f7253c MF |
308 | config BF_REV_0_6 |
309 | bool "0.6" | |
310 | depends on (BF533 || BF532 || BF531) | |
311 | ||
de3025f4 JZ |
312 | config BF_REV_ANY |
313 | bool "any" | |
314 | ||
315 | config BF_REV_NONE | |
316 | bool "none" | |
317 | ||
1394f032 BW |
318 | endchoice |
319 | ||
24a07a12 RH |
320 | config BF53x |
321 | bool | |
322 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
323 | default y | |
324 | ||
1394f032 BW |
325 | config MEM_MT48LC64M4A2FB_7E |
326 | bool | |
327 | depends on (BFIN533_STAMP) | |
328 | default y | |
329 | ||
330 | config MEM_MT48LC16M16A2TG_75 | |
331 | bool | |
332 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
60584344 HK |
333 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
334 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ | |
335 | || BFIN527_BLUETECHNIX_CM) | |
1394f032 BW |
336 | default y |
337 | ||
338 | config MEM_MT48LC32M8A2_75 | |
339 | bool | |
084f9ebf | 340 | depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
341 | default y |
342 | ||
343 | config MEM_MT48LC8M32B2B5_7 | |
344 | bool | |
345 | depends on (BFIN561_BLUETECHNIX_CM) | |
346 | default y | |
347 | ||
59003145 MH |
348 | config MEM_MT48LC32M16A2TG_75 |
349 | bool | |
8effc4a6 | 350 | depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) |
59003145 MH |
351 | default y |
352 | ||
ee48efb5 GY |
353 | config MEM_MT48H32M16LFCJ_75 |
354 | bool | |
355 | depends on (BFIN526_EZBRD) | |
356 | default y | |
357 | ||
f82f16d2 BL |
358 | config MEM_MT47H64M16 |
359 | bool | |
360 | depends on (BFIN609_EZKIT) | |
361 | default y | |
362 | ||
2f6f4bcd | 363 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 364 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
365 | source "arch/blackfin/mach-bf533/Kconfig" |
366 | source "arch/blackfin/mach-bf561/Kconfig" | |
367 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 368 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 369 | source "arch/blackfin/mach-bf548/Kconfig" |
b5affb01 | 370 | source "arch/blackfin/mach-bf609/Kconfig" |
1394f032 BW |
371 | |
372 | menu "Board customizations" | |
373 | ||
374 | config CMDLINE_BOOL | |
375 | bool "Default bootloader kernel arguments" | |
376 | ||
377 | config CMDLINE | |
378 | string "Initial kernel command string" | |
379 | depends on CMDLINE_BOOL | |
380 | default "console=ttyBF0,57600" | |
381 | help | |
382 | If you don't have a boot loader capable of passing a command line string | |
383 | to the kernel, you may specify one here. As a minimum, you should specify | |
384 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
385 | ||
5f004c20 MF |
386 | config BOOT_LOAD |
387 | hex "Kernel load address for booting" | |
388 | default "0x1000" | |
389 | range 0x1000 0x20000000 | |
390 | help | |
391 | This option allows you to set the load address of the kernel. | |
392 | This can be useful if you are on a board which has a small amount | |
393 | of memory or you wish to reserve some memory at the beginning of | |
394 | the address space. | |
395 | ||
396 | Note that you need to keep this value above 4k (0x1000) as this | |
397 | memory region is used to capture NULL pointer references as well | |
398 | as some core kernel functions. | |
399 | ||
b5affb01 BL |
400 | config PHY_RAM_BASE_ADDRESS |
401 | hex "Physical RAM Base" | |
402 | default 0x0 | |
403 | help | |
404 | set BF609 FPGA physical SRAM base address | |
405 | ||
8cc7117e MH |
406 | config ROM_BASE |
407 | hex "Kernel ROM Base" | |
86249911 | 408 | depends on ROMKERNEL |
d86bfb16 | 409 | default "0x20040040" |
3003668c | 410 | range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x) |
8cc7117e | 411 | range 0x20000000 0x30000000 if (BF54x || BF561) |
3003668c | 412 | range 0xB0000000 0xC0000000 if (BF60x) |
8cc7117e | 413 | help |
d86bfb16 BS |
414 | Make sure your ROM base does not include any file-header |
415 | information that is prepended to the kernel. | |
416 | ||
417 | For example, the bootable U-Boot format (created with | |
418 | mkimage) has a 64 byte header (0x40). So while the image | |
419 | you write to flash might start at say 0x20080000, you have | |
420 | to add 0x40 to get the kernel's ROM base as it will come | |
421 | after the header. | |
8cc7117e | 422 | |
f16295e7 | 423 | comment "Clock/PLL Setup" |
1394f032 BW |
424 | |
425 | config CLKIN_HZ | |
2fb6cb41 | 426 | int "Frequency of the crystal on the board in Hz" |
d0cb9b4e | 427 | default "10000000" if BFIN532_IP0X |
1394f032 | 428 | default "11059200" if BFIN533_STAMP |
d0cb9b4e MF |
429 | default "24576000" if PNAV10 |
430 | default "25000000" # most people use this | |
1394f032 | 431 | default "27000000" if BFIN533_EZKIT |
1394f032 | 432 | default "30000000" if BFIN561_EZKIT |
8effc4a6 | 433 | default "24000000" if BFIN527_AD7160EVAL |
1394f032 BW |
434 | help |
435 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
436 | Warning: This value should match the crystal on the board. Otherwise, |
437 | peripherals won't work properly. | |
1394f032 | 438 | |
f16295e7 RG |
439 | config BFIN_KERNEL_CLOCK |
440 | bool "Re-program Clocks while Kernel boots?" | |
441 | default n | |
442 | help | |
443 | This option decides if kernel clocks are re-programed from the | |
444 | bootloader settings. If the clocks are not set, the SDRAM settings | |
445 | are also not changed, and the Bootloader does 100% of the hardware | |
446 | configuration. | |
447 | ||
448 | config PLL_BYPASS | |
e4e9a7ad | 449 | bool "Bypass PLL" |
7c141c1c | 450 | depends on BFIN_KERNEL_CLOCK && (!BF60x) |
e4e9a7ad | 451 | default n |
f16295e7 RG |
452 | |
453 | config CLKIN_HALF | |
454 | bool "Half Clock In" | |
455 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
456 | default n | |
457 | help | |
458 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
459 | ||
460 | config VCO_MULT | |
461 | int "VCO Multiplier" | |
462 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
463 | range 1 64 | |
464 | default "22" if BFIN533_EZKIT | |
465 | default "45" if BFIN533_STAMP | |
6924dfb0 | 466 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 467 | default "22" if BFIN533_BLUETECHNIX_CM |
60584344 | 468 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
7c141c1c | 469 | default "20" if (BFIN561_EZKIT || BF609) |
2f6f4bcd | 470 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
8effc4a6 | 471 | default "25" if BFIN527_AD7160EVAL |
f16295e7 RG |
472 | help |
473 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
474 | PLL Frequency = (Crystal Frequency) * (this setting) | |
475 | ||
476 | choice | |
477 | prompt "Core Clock Divider" | |
478 | depends on BFIN_KERNEL_CLOCK | |
479 | default CCLK_DIV_1 | |
480 | help | |
481 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
482 | Core Frequency = (PLL frequency) / (this setting) | |
483 | ||
484 | config CCLK_DIV_1 | |
485 | bool "1" | |
486 | ||
487 | config CCLK_DIV_2 | |
488 | bool "2" | |
489 | ||
490 | config CCLK_DIV_4 | |
491 | bool "4" | |
492 | ||
493 | config CCLK_DIV_8 | |
494 | bool "8" | |
495 | endchoice | |
496 | ||
497 | config SCLK_DIV | |
498 | int "System Clock Divider" | |
499 | depends on BFIN_KERNEL_CLOCK | |
500 | range 1 15 | |
7c141c1c | 501 | default 4 |
f16295e7 | 502 | help |
7c141c1c BL |
503 | This sets the frequency of the system clock (including SDRAM or DDR) on |
504 | !BF60x else it set the clock for system buses and provides the | |
505 | source from which SCLK0 and SCLK1 are derived. | |
f16295e7 RG |
506 | This can be between 1 and 15 |
507 | System Clock = (PLL frequency) / (this setting) | |
508 | ||
7c141c1c BL |
509 | config SCLK0_DIV |
510 | int "System Clock0 Divider" | |
511 | depends on BFIN_KERNEL_CLOCK && BF60x | |
512 | range 1 15 | |
513 | default 1 | |
514 | help | |
515 | This sets the frequency of the system clock0 for PVP and all other | |
516 | peripherals not clocked by SCLK1. | |
517 | This can be between 1 and 15 | |
518 | System Clock0 = (System Clock) / (this setting) | |
519 | ||
520 | config SCLK1_DIV | |
521 | int "System Clock1 Divider" | |
522 | depends on BFIN_KERNEL_CLOCK && BF60x | |
523 | range 1 15 | |
524 | default 1 | |
525 | help | |
526 | This sets the frequency of the system clock1 (including SPORT, SPI and ACM). | |
527 | This can be between 1 and 15 | |
528 | System Clock1 = (System Clock) / (this setting) | |
529 | ||
530 | config DCLK_DIV | |
531 | int "DDR Clock Divider" | |
532 | depends on BFIN_KERNEL_CLOCK && BF60x | |
533 | range 1 15 | |
534 | default 2 | |
535 | help | |
536 | This sets the frequency of the DDR memory. | |
537 | This can be between 1 and 15 | |
538 | DDR Clock = (PLL frequency) / (this setting) | |
539 | ||
5f004c20 MF |
540 | choice |
541 | prompt "DDR SDRAM Chip Type" | |
542 | depends on BFIN_KERNEL_CLOCK | |
543 | depends on BF54x | |
544 | default MEM_MT46V32M16_5B | |
545 | ||
546 | config MEM_MT46V32M16_6T | |
547 | bool "MT46V32M16_6T" | |
548 | ||
549 | config MEM_MT46V32M16_5B | |
550 | bool "MT46V32M16_5B" | |
551 | endchoice | |
552 | ||
73feb5c0 MH |
553 | choice |
554 | prompt "DDR/SDRAM Timing" | |
7c141c1c | 555 | depends on BFIN_KERNEL_CLOCK && !BF60x |
73feb5c0 MH |
556 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC |
557 | help | |
558 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
559 | The calculated SDRAM timing parameters may not be 100% | |
560 | accurate - This option is therefore marked experimental. | |
561 | ||
562 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
563 | bool "Calculate Timings (EXPERIMENTAL)" | |
564 | depends on EXPERIMENTAL | |
565 | ||
566 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
567 | bool "Provide accurate Timings based on target SCLK" | |
568 | help | |
569 | Please consult the Blackfin Hardware Reference Manuals as well | |
570 | as the memory device datasheet. | |
571 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
572 | endchoice | |
573 | ||
574 | menu "Memory Init Control" | |
575 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
576 | ||
577 | config MEM_DDRCTL0 | |
578 | depends on BF54x | |
579 | hex "DDRCTL0" | |
580 | default 0x0 | |
581 | ||
582 | config MEM_DDRCTL1 | |
583 | depends on BF54x | |
584 | hex "DDRCTL1" | |
585 | default 0x0 | |
586 | ||
587 | config MEM_DDRCTL2 | |
588 | depends on BF54x | |
589 | hex "DDRCTL2" | |
590 | default 0x0 | |
591 | ||
592 | config MEM_EBIU_DDRQUE | |
593 | depends on BF54x | |
594 | hex "DDRQUE" | |
595 | default 0x0 | |
596 | ||
597 | config MEM_SDRRC | |
598 | depends on !BF54x | |
599 | hex "SDRRC" | |
600 | default 0x0 | |
601 | ||
602 | config MEM_SDGCTL | |
603 | depends on !BF54x | |
604 | hex "SDGCTL" | |
605 | default 0x0 | |
606 | endmenu | |
607 | ||
f16295e7 RG |
608 | # |
609 | # Max & Min Speeds for various Chips | |
610 | # | |
611 | config MAX_VCO_HZ | |
612 | int | |
2f6f4bcd BW |
613 | default 400000000 if BF512 |
614 | default 400000000 if BF514 | |
615 | default 400000000 if BF516 | |
616 | default 400000000 if BF518 | |
7b06263b MF |
617 | default 400000000 if BF522 |
618 | default 600000000 if BF523 | |
1545a111 | 619 | default 400000000 if BF524 |
f16295e7 | 620 | default 600000000 if BF525 |
1545a111 | 621 | default 400000000 if BF526 |
f16295e7 RG |
622 | default 600000000 if BF527 |
623 | default 400000000 if BF531 | |
624 | default 400000000 if BF532 | |
625 | default 750000000 if BF533 | |
626 | default 500000000 if BF534 | |
627 | default 400000000 if BF536 | |
628 | default 600000000 if BF537 | |
f72eecb9 RG |
629 | default 533333333 if BF538 |
630 | default 533333333 if BF539 | |
f16295e7 | 631 | default 600000000 if BF542 |
f72eecb9 | 632 | default 533333333 if BF544 |
1545a111 MF |
633 | default 600000000 if BF547 |
634 | default 600000000 if BF548 | |
f72eecb9 | 635 | default 533333333 if BF549 |
f16295e7 | 636 | default 600000000 if BF561 |
7c141c1c | 637 | default 800000000 if BF609 |
f16295e7 RG |
638 | |
639 | config MIN_VCO_HZ | |
640 | int | |
641 | default 50000000 | |
642 | ||
643 | config MAX_SCLK_HZ | |
644 | int | |
7c141c1c | 645 | default 200000000 if BF609 |
f72eecb9 | 646 | default 133333333 |
f16295e7 RG |
647 | |
648 | config MIN_SCLK_HZ | |
649 | int | |
650 | default 27000000 | |
651 | ||
652 | comment "Kernel Timer/Scheduler" | |
653 | ||
654 | source kernel/Kconfig.hz | |
655 | ||
dfbaec06 | 656 | config SET_GENERIC_CLOCKEVENTS |
8b5f79f9 | 657 | bool "Generic clock events" |
8b5f79f9 | 658 | default y |
dfbaec06 | 659 | select GENERIC_CLOCKEVENTS |
8b5f79f9 | 660 | |
0d152c27 | 661 | menu "Clock event device" |
1fa9be72 | 662 | depends on GENERIC_CLOCKEVENTS |
1fa9be72 | 663 | config TICKSOURCE_GPTMR0 |
0d152c27 YL |
664 | bool "GPTimer0" |
665 | depends on !SMP | |
1fa9be72 | 666 | select BFIN_GPTIMERS |
1fa9be72 GY |
667 | |
668 | config TICKSOURCE_CORETMR | |
0d152c27 YL |
669 | bool "Core timer" |
670 | default y | |
671 | endmenu | |
1fa9be72 | 672 | |
0d152c27 | 673 | menu "Clock souce" |
8b5f79f9 | 674 | depends on GENERIC_CLOCKEVENTS |
0d152c27 YL |
675 | config CYCLES_CLOCKSOURCE |
676 | bool "CYCLES" | |
677 | default y | |
8b5f79f9 | 678 | depends on !BFIN_SCRATCH_REG_CYCLES |
1fa9be72 | 679 | depends on !SMP |
8b5f79f9 VM |
680 | help |
681 | If you say Y here, you will enable support for using the 'cycles' | |
682 | registers as a clock source. Doing so means you will be unable to | |
683 | safely write to the 'cycles' register during runtime. You will | |
684 | still be able to read it (such as for performance monitoring), but | |
685 | writing the registers will most likely crash the kernel. | |
686 | ||
1fa9be72 | 687 | config GPTMR0_CLOCKSOURCE |
0d152c27 | 688 | bool "GPTimer0" |
3aca47c0 | 689 | select BFIN_GPTIMERS |
1fa9be72 | 690 | depends on !TICKSOURCE_GPTMR0 |
0d152c27 | 691 | endmenu |
1fa9be72 | 692 | |
5f004c20 | 693 | comment "Misc" |
971d5bc4 | 694 | |
f0b5d12f MF |
695 | choice |
696 | prompt "Blackfin Exception Scratch Register" | |
697 | default BFIN_SCRATCH_REG_RETN | |
698 | help | |
699 | Select the resource to reserve for the Exception handler: | |
700 | - RETN: Non-Maskable Interrupt (NMI) | |
701 | - RETE: Exception Return (JTAG/ICE) | |
702 | - CYCLES: Performance counter | |
703 | ||
704 | If you are unsure, please select "RETN". | |
705 | ||
706 | config BFIN_SCRATCH_REG_RETN | |
707 | bool "RETN" | |
708 | help | |
709 | Use the RETN register in the Blackfin exception handler | |
710 | as a stack scratch register. This means you cannot | |
711 | safely use NMI on the Blackfin while running Linux, but | |
712 | you can debug the system with a JTAG ICE and use the | |
713 | CYCLES performance registers. | |
714 | ||
715 | If you are unsure, please select "RETN". | |
716 | ||
717 | config BFIN_SCRATCH_REG_RETE | |
718 | bool "RETE" | |
719 | help | |
720 | Use the RETE register in the Blackfin exception handler | |
721 | as a stack scratch register. This means you cannot | |
722 | safely use a JTAG ICE while debugging a Blackfin board, | |
723 | but you can safely use the CYCLES performance registers | |
724 | and the NMI. | |
725 | ||
726 | If you are unsure, please select "RETN". | |
727 | ||
728 | config BFIN_SCRATCH_REG_CYCLES | |
729 | bool "CYCLES" | |
730 | help | |
731 | Use the CYCLES register in the Blackfin exception handler | |
732 | as a stack scratch register. This means you cannot | |
733 | safely use the CYCLES performance registers on a Blackfin | |
734 | board at anytime, but you can debug the system with a JTAG | |
735 | ICE and use the NMI. | |
736 | ||
737 | If you are unsure, please select "RETN". | |
738 | ||
739 | endchoice | |
740 | ||
1394f032 BW |
741 | endmenu |
742 | ||
743 | ||
744 | menu "Blackfin Kernel Optimizations" | |
745 | ||
1394f032 BW |
746 | comment "Memory Optimizations" |
747 | ||
748 | config I_ENTRY_L1 | |
749 | bool "Locate interrupt entry code in L1 Memory" | |
750 | default y | |
820b127d | 751 | depends on !SMP |
1394f032 | 752 | help |
01dd2fbf ML |
753 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
754 | into L1 instruction memory. (less latency) | |
1394f032 BW |
755 | |
756 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 757 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 | 758 | default y |
820b127d | 759 | depends on !SMP |
1394f032 | 760 | help |
01dd2fbf | 761 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 762 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 763 | (less latency) |
1394f032 BW |
764 | |
765 | config DO_IRQ_L1 | |
766 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
767 | default y | |
820b127d | 768 | depends on !SMP |
1394f032 | 769 | help |
01dd2fbf ML |
770 | If enabled, the frequently called do_irq dispatcher function is linked |
771 | into L1 instruction memory. (less latency) | |
1394f032 BW |
772 | |
773 | config CORE_TIMER_IRQ_L1 | |
774 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
775 | default y | |
820b127d | 776 | depends on !SMP |
1394f032 | 777 | help |
01dd2fbf ML |
778 | If enabled, the frequently called timer_interrupt() function is linked |
779 | into L1 instruction memory. (less latency) | |
1394f032 BW |
780 | |
781 | config IDLE_L1 | |
782 | bool "Locate frequently idle function in L1 Memory" | |
783 | default y | |
820b127d | 784 | depends on !SMP |
1394f032 | 785 | help |
01dd2fbf ML |
786 | If enabled, the frequently called idle function is linked |
787 | into L1 instruction memory. (less latency) | |
1394f032 BW |
788 | |
789 | config SCHEDULE_L1 | |
790 | bool "Locate kernel schedule function in L1 Memory" | |
791 | default y | |
820b127d | 792 | depends on !SMP |
1394f032 | 793 | help |
01dd2fbf ML |
794 | If enabled, the frequently called kernel schedule is linked |
795 | into L1 instruction memory. (less latency) | |
1394f032 BW |
796 | |
797 | config ARITHMETIC_OPS_L1 | |
798 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
799 | default y | |
820b127d | 800 | depends on !SMP |
1394f032 | 801 | help |
01dd2fbf ML |
802 | If enabled, arithmetic functions are linked |
803 | into L1 instruction memory. (less latency) | |
1394f032 BW |
804 | |
805 | config ACCESS_OK_L1 | |
806 | bool "Locate access_ok function in L1 Memory" | |
807 | default y | |
820b127d | 808 | depends on !SMP |
1394f032 | 809 | help |
01dd2fbf ML |
810 | If enabled, the access_ok function is linked |
811 | into L1 instruction memory. (less latency) | |
1394f032 BW |
812 | |
813 | config MEMSET_L1 | |
814 | bool "Locate memset function in L1 Memory" | |
815 | default y | |
820b127d | 816 | depends on !SMP |
1394f032 | 817 | help |
01dd2fbf ML |
818 | If enabled, the memset function is linked |
819 | into L1 instruction memory. (less latency) | |
1394f032 BW |
820 | |
821 | config MEMCPY_L1 | |
822 | bool "Locate memcpy function in L1 Memory" | |
823 | default y | |
820b127d | 824 | depends on !SMP |
1394f032 | 825 | help |
01dd2fbf ML |
826 | If enabled, the memcpy function is linked |
827 | into L1 instruction memory. (less latency) | |
1394f032 | 828 | |
479ba603 RG |
829 | config STRCMP_L1 |
830 | bool "locate strcmp function in L1 Memory" | |
831 | default y | |
820b127d | 832 | depends on !SMP |
479ba603 RG |
833 | help |
834 | If enabled, the strcmp function is linked | |
835 | into L1 instruction memory (less latency). | |
836 | ||
837 | config STRNCMP_L1 | |
838 | bool "locate strncmp function in L1 Memory" | |
839 | default y | |
820b127d | 840 | depends on !SMP |
479ba603 RG |
841 | help |
842 | If enabled, the strncmp function is linked | |
843 | into L1 instruction memory (less latency). | |
844 | ||
845 | config STRCPY_L1 | |
846 | bool "locate strcpy function in L1 Memory" | |
847 | default y | |
820b127d | 848 | depends on !SMP |
479ba603 RG |
849 | help |
850 | If enabled, the strcpy function is linked | |
851 | into L1 instruction memory (less latency). | |
852 | ||
853 | config STRNCPY_L1 | |
854 | bool "locate strncpy function in L1 Memory" | |
855 | default y | |
820b127d | 856 | depends on !SMP |
479ba603 RG |
857 | help |
858 | If enabled, the strncpy function is linked | |
859 | into L1 instruction memory (less latency). | |
860 | ||
1394f032 BW |
861 | config SYS_BFIN_SPINLOCK_L1 |
862 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
863 | default y | |
820b127d | 864 | depends on !SMP |
1394f032 | 865 | help |
01dd2fbf ML |
866 | If enabled, sys_bfin_spinlock function is linked |
867 | into L1 instruction memory. (less latency) | |
1394f032 BW |
868 | |
869 | config IP_CHECKSUM_L1 | |
870 | bool "Locate IP Checksum function in L1 Memory" | |
871 | default n | |
820b127d | 872 | depends on !SMP |
1394f032 | 873 | help |
01dd2fbf ML |
874 | If enabled, the IP Checksum function is linked |
875 | into L1 instruction memory. (less latency) | |
1394f032 BW |
876 | |
877 | config CACHELINE_ALIGNED_L1 | |
878 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
879 | default y if !BF54x |
880 | default n if BF54x | |
95fc2d8f | 881 | depends on !SMP && !BF531 && !CRC32 |
1394f032 | 882 | help |
692105b8 | 883 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 884 | into L1 data memory. (less latency) |
1394f032 BW |
885 | |
886 | config SYSCALL_TAB_L1 | |
887 | bool "Locate Syscall Table L1 Data Memory" | |
888 | default n | |
820b127d | 889 | depends on !SMP && !BF531 |
1394f032 | 890 | help |
01dd2fbf ML |
891 | If enabled, the Syscall LUT is linked |
892 | into L1 data memory. (less latency) | |
1394f032 BW |
893 | |
894 | config CPLB_SWITCH_TAB_L1 | |
895 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
896 | default n | |
820b127d | 897 | depends on !SMP && !BF531 |
1394f032 | 898 | help |
01dd2fbf ML |
899 | If enabled, the CPLB Switch Tables are linked |
900 | into L1 data memory. (less latency) | |
1394f032 | 901 | |
820b127d MF |
902 | config ICACHE_FLUSH_L1 |
903 | bool "Locate icache flush funcs in L1 Inst Memory" | |
74181295 MF |
904 | default y |
905 | help | |
820b127d | 906 | If enabled, the Blackfin icache flushing functions are linked |
74181295 MF |
907 | into L1 instruction memory. |
908 | ||
909 | Note that this might be required to address anomalies, but | |
910 | these functions are pretty small, so it shouldn't be too bad. | |
911 | If you are using a processor affected by an anomaly, the build | |
912 | system will double check for you and prevent it. | |
913 | ||
820b127d MF |
914 | config DCACHE_FLUSH_L1 |
915 | bool "Locate dcache flush funcs in L1 Inst Memory" | |
916 | default y | |
917 | depends on !SMP | |
918 | help | |
919 | If enabled, the Blackfin dcache flushing functions are linked | |
920 | into L1 instruction memory. | |
921 | ||
ca87b7ad GY |
922 | config APP_STACK_L1 |
923 | bool "Support locating application stack in L1 Scratch Memory" | |
924 | default y | |
820b127d | 925 | depends on !SMP |
ca87b7ad GY |
926 | help |
927 | If enabled the application stack can be located in L1 | |
928 | scratch memory (less latency). | |
929 | ||
930 | Currently only works with FLAT binaries. | |
931 | ||
6ad2b84c MF |
932 | config EXCEPTION_L1_SCRATCH |
933 | bool "Locate exception stack in L1 Scratch Memory" | |
934 | default n | |
820b127d | 935 | depends on !SMP && !APP_STACK_L1 |
6ad2b84c MF |
936 | help |
937 | Whenever an exception occurs, use the L1 Scratch memory for | |
938 | stack storage. You cannot place the stacks of FLAT binaries | |
939 | in L1 when using this option. | |
940 | ||
941 | If you don't use L1 Scratch, then you should say Y here. | |
942 | ||
251383c7 RG |
943 | comment "Speed Optimizations" |
944 | config BFIN_INS_LOWOVERHEAD | |
945 | bool "ins[bwl] low overhead, higher interrupt latency" | |
946 | default y | |
820b127d | 947 | depends on !SMP |
251383c7 RG |
948 | help |
949 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
950 | they can be interrupted at any time (even after they have been issued | |
951 | on to the external bus), and re-issued after the interrupt occurs. | |
952 | For memory - this is not a big deal, since memory does not change if | |
953 | it sees a read. | |
954 | ||
955 | If a FIFO is sitting on the end of the read, it will see two reads, | |
956 | when the core only sees one since the FIFO receives both the read | |
957 | which is cancelled (and not delivered to the core) and the one which | |
958 | is re-issued (which is delivered to the core). | |
959 | ||
960 | To solve this, interrupts are turned off before reads occur to | |
961 | I/O space. This option controls which the overhead/latency of | |
962 | controlling interrupts during this time | |
963 | "n" turns interrupts off every read | |
964 | (higher overhead, but lower interrupt latency) | |
965 | "y" turns interrupts off every loop | |
966 | (low overhead, but longer interrupt latency) | |
967 | ||
968 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
969 | interrupt latency issues, it is safe and OK to turn this off. | |
970 | ||
1394f032 BW |
971 | endmenu |
972 | ||
1394f032 BW |
973 | choice |
974 | prompt "Kernel executes from" | |
975 | help | |
976 | Choose the memory type that the kernel will be running in. | |
977 | ||
978 | config RAMKERNEL | |
979 | bool "RAM" | |
980 | help | |
981 | The kernel will be resident in RAM when running. | |
982 | ||
983 | config ROMKERNEL | |
984 | bool "ROM" | |
985 | help | |
986 | The kernel will be resident in FLASH/ROM when running. | |
987 | ||
988 | endchoice | |
989 | ||
56b4f07a MF |
990 | # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both |
991 | config XIP_KERNEL | |
992 | bool | |
993 | default y | |
994 | depends on ROMKERNEL | |
995 | ||
1394f032 BW |
996 | source "mm/Kconfig" |
997 | ||
780431e3 MF |
998 | config BFIN_GPTIMERS |
999 | tristate "Enable Blackfin General Purpose Timers API" | |
1000 | default n | |
1001 | help | |
1002 | Enable support for the General Purpose Timers API. If you | |
1003 | are unsure, say N. | |
1004 | ||
1005 | To compile this driver as a module, choose M here: the module | |
4737f097 | 1006 | will be called gptimers. |
780431e3 | 1007 | |
1394f032 | 1008 | choice |
d292b000 | 1009 | prompt "Uncached DMA region" |
1394f032 | 1010 | default DMA_UNCACHED_1M |
c8d11a06 SJ |
1011 | config DMA_UNCACHED_32M |
1012 | bool "Enable 32M DMA region" | |
1013 | config DMA_UNCACHED_16M | |
1014 | bool "Enable 16M DMA region" | |
1015 | config DMA_UNCACHED_8M | |
1016 | bool "Enable 8M DMA region" | |
86ad7932 CC |
1017 | config DMA_UNCACHED_4M |
1018 | bool "Enable 4M DMA region" | |
1394f032 BW |
1019 | config DMA_UNCACHED_2M |
1020 | bool "Enable 2M DMA region" | |
1021 | config DMA_UNCACHED_1M | |
1022 | bool "Enable 1M DMA region" | |
c45c0659 BS |
1023 | config DMA_UNCACHED_512K |
1024 | bool "Enable 512K DMA region" | |
1025 | config DMA_UNCACHED_256K | |
1026 | bool "Enable 256K DMA region" | |
1027 | config DMA_UNCACHED_128K | |
1028 | bool "Enable 128K DMA region" | |
1394f032 BW |
1029 | config DMA_UNCACHED_NONE |
1030 | bool "Disable DMA region" | |
1031 | endchoice | |
1032 | ||
1033 | ||
1034 | comment "Cache Support" | |
41ba653f | 1035 | |
3bebca2d | 1036 | config BFIN_ICACHE |
1394f032 | 1037 | bool "Enable ICACHE" |
41ba653f | 1038 | default y |
41ba653f JZ |
1039 | config BFIN_EXTMEM_ICACHEABLE |
1040 | bool "Enable ICACHE for external memory" | |
1041 | depends on BFIN_ICACHE | |
1042 | default y | |
1043 | config BFIN_L2_ICACHEABLE | |
1044 | bool "Enable ICACHE for L2 SRAM" | |
1045 | depends on BFIN_ICACHE | |
b0ce61d5 | 1046 | depends on (BF54x || BF561 || BF60x) && !SMP |
41ba653f JZ |
1047 | default n |
1048 | ||
3bebca2d | 1049 | config BFIN_DCACHE |
1394f032 | 1050 | bool "Enable DCACHE" |
41ba653f | 1051 | default y |
3bebca2d | 1052 | config BFIN_DCACHE_BANKA |
1394f032 | 1053 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 1054 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 1055 | default n |
41ba653f JZ |
1056 | config BFIN_EXTMEM_DCACHEABLE |
1057 | bool "Enable DCACHE for external memory" | |
3bebca2d | 1058 | depends on BFIN_DCACHE |
41ba653f JZ |
1059 | default y |
1060 | choice | |
1061 | prompt "External memory DCACHE policy" | |
1062 | depends on BFIN_EXTMEM_DCACHEABLE | |
1063 | default BFIN_EXTMEM_WRITEBACK if !SMP | |
1064 | default BFIN_EXTMEM_WRITETHROUGH if SMP | |
1065 | config BFIN_EXTMEM_WRITEBACK | |
1394f032 | 1066 | bool "Write back" |
46fa5eec | 1067 | depends on !SMP |
1394f032 BW |
1068 | help |
1069 | Write Back Policy: | |
1070 | Cached data will be written back to SDRAM only when needed. | |
1071 | This can give a nice increase in performance, but beware of | |
1072 | broken drivers that do not properly invalidate/flush their | |
1073 | cache. | |
1074 | ||
1075 | Write Through Policy: | |
1076 | Cached data will always be written back to SDRAM when the | |
1077 | cache is updated. This is a completely safe setting, but | |
1078 | performance is worse than Write Back. | |
1079 | ||
1080 | If you are unsure of the options and you want to be safe, | |
1081 | then go with Write Through. | |
1082 | ||
41ba653f | 1083 | config BFIN_EXTMEM_WRITETHROUGH |
1394f032 BW |
1084 | bool "Write through" |
1085 | help | |
1086 | Write Back Policy: | |
1087 | Cached data will be written back to SDRAM only when needed. | |
1088 | This can give a nice increase in performance, but beware of | |
1089 | broken drivers that do not properly invalidate/flush their | |
1090 | cache. | |
1091 | ||
1092 | Write Through Policy: | |
1093 | Cached data will always be written back to SDRAM when the | |
1094 | cache is updated. This is a completely safe setting, but | |
1095 | performance is worse than Write Back. | |
1096 | ||
1097 | If you are unsure of the options and you want to be safe, | |
1098 | then go with Write Through. | |
1099 | ||
1100 | endchoice | |
1101 | ||
41ba653f JZ |
1102 | config BFIN_L2_DCACHEABLE |
1103 | bool "Enable DCACHE for L2 SRAM" | |
1104 | depends on BFIN_DCACHE | |
b5affb01 | 1105 | depends on (BF54x || BF561 || BF60x) && !SMP |
41ba653f | 1106 | default n |
5ba76675 | 1107 | choice |
41ba653f JZ |
1108 | prompt "L2 SRAM DCACHE policy" |
1109 | depends on BFIN_L2_DCACHEABLE | |
1110 | default BFIN_L2_WRITEBACK | |
1111 | config BFIN_L2_WRITEBACK | |
5ba76675 | 1112 | bool "Write back" |
5ba76675 | 1113 | |
41ba653f | 1114 | config BFIN_L2_WRITETHROUGH |
5ba76675 | 1115 | bool "Write through" |
5ba76675 | 1116 | endchoice |
f099f39a | 1117 | |
41ba653f JZ |
1118 | |
1119 | comment "Memory Protection Unit" | |
b97b8a99 BS |
1120 | config MPU |
1121 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
1122 | default n | |
1123 | help | |
1124 | Use the processor's MPU to protect applications from accessing | |
1125 | memory they do not own. This comes at a performance penalty | |
1126 | and is recommended only for debugging. | |
1127 | ||
692105b8 | 1128 | comment "Asynchronous Memory Configuration" |
1394f032 | 1129 | |
ddf416b2 | 1130 | menu "EBIU_AMGCTL Global Control" |
b5affb01 | 1131 | depends on !BF60x |
1394f032 BW |
1132 | config C_AMCKEN |
1133 | bool "Enable CLKOUT" | |
1134 | default y | |
1135 | ||
1136 | config C_CDPRIO | |
1137 | bool "DMA has priority over core for ext. accesses" | |
1138 | default n | |
1139 | ||
1140 | config C_B0PEN | |
1141 | depends on BF561 | |
1142 | bool "Bank 0 16 bit packing enable" | |
1143 | default y | |
1144 | ||
1145 | config C_B1PEN | |
1146 | depends on BF561 | |
1147 | bool "Bank 1 16 bit packing enable" | |
1148 | default y | |
1149 | ||
1150 | config C_B2PEN | |
1151 | depends on BF561 | |
1152 | bool "Bank 2 16 bit packing enable" | |
1153 | default y | |
1154 | ||
1155 | config C_B3PEN | |
1156 | depends on BF561 | |
1157 | bool "Bank 3 16 bit packing enable" | |
1158 | default n | |
1159 | ||
1160 | choice | |
692105b8 | 1161 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1162 | default C_AMBEN_ALL |
1163 | ||
1164 | config C_AMBEN | |
1165 | bool "Disable All Banks" | |
1166 | ||
1167 | config C_AMBEN_B0 | |
1168 | bool "Enable Bank 0" | |
1169 | ||
1170 | config C_AMBEN_B0_B1 | |
1171 | bool "Enable Bank 0 & 1" | |
1172 | ||
1173 | config C_AMBEN_B0_B1_B2 | |
1174 | bool "Enable Bank 0 & 1 & 2" | |
1175 | ||
1176 | config C_AMBEN_ALL | |
1177 | bool "Enable All Banks" | |
1178 | endchoice | |
1179 | endmenu | |
1180 | ||
1181 | menu "EBIU_AMBCTL Control" | |
b5affb01 | 1182 | depends on !BF60x |
1394f032 | 1183 | config BANK_0 |
c8342f87 | 1184 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1185 | default 0x7BB0 |
c8342f87 MF |
1186 | help |
1187 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1188 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1189 | |
1190 | config BANK_1 | |
c8342f87 | 1191 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1192 | default 0x7BB0 |
197fba56 | 1193 | default 0x5558 if BF54x |
c8342f87 MF |
1194 | help |
1195 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1196 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1197 | |
1198 | config BANK_2 | |
c8342f87 | 1199 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1200 | default 0x7BB0 |
c8342f87 MF |
1201 | help |
1202 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1203 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1204 | |
1205 | config BANK_3 | |
c8342f87 | 1206 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1207 | default 0x99B3 |
c8342f87 MF |
1208 | help |
1209 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1210 | used to control the Asynchronous Memory Bank 3 settings. | |
1211 | ||
1394f032 BW |
1212 | endmenu |
1213 | ||
e40540b3 SZ |
1214 | config EBIU_MBSCTLVAL |
1215 | hex "EBIU Bank Select Control Register" | |
1216 | depends on BF54x | |
1217 | default 0 | |
1218 | ||
1219 | config EBIU_MODEVAL | |
1220 | hex "Flash Memory Mode Control Register" | |
1221 | depends on BF54x | |
1222 | default 1 | |
1223 | ||
1224 | config EBIU_FCTLVAL | |
1225 | hex "Flash Memory Bank Control Register" | |
1226 | depends on BF54x | |
1227 | default 6 | |
1394f032 BW |
1228 | endmenu |
1229 | ||
1230 | ############################################################################# | |
1231 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1232 | ||
1233 | config PCI | |
1234 | bool "PCI support" | |
a95ca3b2 | 1235 | depends on BROKEN |
1394f032 BW |
1236 | help |
1237 | Support for PCI bus. | |
1238 | ||
1239 | source "drivers/pci/Kconfig" | |
1240 | ||
1394f032 BW |
1241 | source "drivers/pcmcia/Kconfig" |
1242 | ||
1243 | source "drivers/pci/hotplug/Kconfig" | |
1244 | ||
1245 | endmenu | |
1246 | ||
1247 | menu "Executable file formats" | |
1248 | ||
1249 | source "fs/Kconfig.binfmt" | |
1250 | ||
1251 | endmenu | |
1252 | ||
1253 | menu "Power management options" | |
ad46163a | 1254 | |
1394f032 BW |
1255 | source "kernel/power/Kconfig" |
1256 | ||
f4cb5700 JB |
1257 | config ARCH_SUSPEND_POSSIBLE |
1258 | def_bool y | |
f4cb5700 | 1259 | |
1394f032 | 1260 | choice |
1efc80b5 | 1261 | prompt "Standby Power Saving Mode" |
0fbd88ca | 1262 | depends on PM && !BF60x |
cfefe3c6 MH |
1263 | default PM_BFIN_SLEEP_DEEPER |
1264 | config PM_BFIN_SLEEP_DEEPER | |
1265 | bool "Sleep Deeper" | |
1266 | help | |
1267 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1268 | power dissipation by disabling the clock to the processor core (CCLK). | |
1269 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1270 | to 0.85 V to provide the greatest power savings, while preserving the | |
1271 | processor state. | |
1272 | The PLL and system clock (SCLK) continue to operate at a very low | |
1273 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1274 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1275 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1276 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1277 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1278 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1279 | ||
1efc80b5 MH |
1280 | If unsure, select "Sleep Deeper". |
1281 | ||
cfefe3c6 MH |
1282 | config PM_BFIN_SLEEP |
1283 | bool "Sleep" | |
1284 | help | |
1285 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1286 | dissipation by disabling the clock to the processor core (CCLK). | |
1287 | The PLL and system clock (SCLK), however, continue to operate in | |
1288 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1289 | up the processor. When in the sleep mode, system DMA access to L1 |
1290 | memory is not supported. | |
1291 | ||
1292 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1293 | endchoice |
1394f032 | 1294 | |
1efc80b5 MH |
1295 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1296 | depends on PM | |
1297 | ||
1efc80b5 MH |
1298 | config PM_BFIN_WAKE_PH6 |
1299 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1300 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1301 | default n |
1302 | help | |
1303 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1304 | ||
1efc80b5 MH |
1305 | config PM_BFIN_WAKE_GP |
1306 | bool "Allow Wake-Up from GPIOs" | |
1307 | depends on PM && BF54x | |
1308 | default n | |
1309 | help | |
1310 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1311 | (all processors, except ADSP-BF549). This option sets |
1312 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1313 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
59bf8964 | 1314 | On ADSP-BF549 this option enables the same functionality on the |
19986289 MH |
1315 | /MRXON pin also PH7. |
1316 | ||
0fbd88ca SM |
1317 | config PM_BFIN_WAKE_PA15 |
1318 | bool "Allow Wake-Up from PA15" | |
1319 | depends on PM && BF60x | |
1320 | default n | |
1321 | help | |
1322 | Enable PA15 Wake-Up | |
1323 | ||
1324 | config PM_BFIN_WAKE_PA15_POL | |
1325 | int "Wake-up priority" | |
1326 | depends on PM_BFIN_WAKE_PA15 | |
1327 | default 0 | |
1328 | help | |
1329 | Wake-Up priority 0(low) 1(high) | |
1330 | ||
1331 | config PM_BFIN_WAKE_PB15 | |
1332 | bool "Allow Wake-Up from PB15" | |
1333 | depends on PM && BF60x | |
1334 | default n | |
1335 | help | |
1336 | Enable PB15 Wake-Up | |
1337 | ||
1338 | config PM_BFIN_WAKE_PB15_POL | |
1339 | int "Wake-up priority" | |
1340 | depends on PM_BFIN_WAKE_PB15 | |
1341 | default 0 | |
1342 | help | |
1343 | Wake-Up priority 0(low) 1(high) | |
1344 | ||
1345 | config PM_BFIN_WAKE_PC15 | |
1346 | bool "Allow Wake-Up from PC15" | |
1347 | depends on PM && BF60x | |
1348 | default n | |
1349 | help | |
1350 | Enable PC15 Wake-Up | |
1351 | ||
1352 | config PM_BFIN_WAKE_PC15_POL | |
1353 | int "Wake-up priority" | |
1354 | depends on PM_BFIN_WAKE_PC15 | |
1355 | default 0 | |
1356 | help | |
1357 | Wake-Up priority 0(low) 1(high) | |
1358 | ||
1359 | config PM_BFIN_WAKE_PD06 | |
1360 | bool "Allow Wake-Up from PD06(ETH0_PHYINT)" | |
1361 | depends on PM && BF60x | |
1362 | default n | |
1363 | help | |
1364 | Enable PD06(ETH0_PHYINT) Wake-up | |
1365 | ||
1366 | config PM_BFIN_WAKE_PD06_POL | |
1367 | int "Wake-up priority" | |
1368 | depends on PM_BFIN_WAKE_PD06 | |
1369 | default 0 | |
1370 | help | |
1371 | Wake-Up priority 0(low) 1(high) | |
1372 | ||
1373 | config PM_BFIN_WAKE_PE12 | |
1374 | bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)" | |
1375 | depends on PM && BF60x | |
1376 | default n | |
1377 | help | |
1378 | Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up | |
1379 | ||
1380 | config PM_BFIN_WAKE_PE12_POL | |
1381 | int "Wake-up priority" | |
1382 | depends on PM_BFIN_WAKE_PE12 | |
1383 | default 0 | |
1384 | help | |
1385 | Wake-Up priority 0(low) 1(high) | |
1386 | ||
1387 | config PM_BFIN_WAKE_PG04 | |
1388 | bool "Allow Wake-Up from PG04(CAN0_RX)" | |
1389 | depends on PM && BF60x | |
1390 | default n | |
1391 | help | |
1392 | Enable PG04(CAN0_RX) Wake-up | |
1393 | ||
1394 | config PM_BFIN_WAKE_PG04_POL | |
1395 | int "Wake-up priority" | |
1396 | depends on PM_BFIN_WAKE_PG04 | |
1397 | default 0 | |
1398 | help | |
1399 | Wake-Up priority 0(low) 1(high) | |
1400 | ||
1401 | config PM_BFIN_WAKE_PG13 | |
1402 | bool "Allow Wake-Up from PG13" | |
1403 | depends on PM && BF60x | |
1404 | default n | |
1405 | help | |
1406 | Enable PG13 Wake-Up | |
1407 | ||
1408 | config PM_BFIN_WAKE_PG13_POL | |
1409 | int "Wake-up priority" | |
1410 | depends on PM_BFIN_WAKE_PG13 | |
1411 | default 0 | |
1412 | help | |
1413 | Wake-Up priority 0(low) 1(high) | |
1414 | ||
1415 | config PM_BFIN_WAKE_USB | |
1416 | bool "Allow Wake-Up from (USB)" | |
1417 | depends on PM && BF60x | |
1418 | default n | |
1419 | help | |
1420 | Enable (USB) Wake-up | |
1421 | ||
1422 | config PM_BFIN_WAKE_USB_POL | |
1423 | int "Wake-up priority" | |
1424 | depends on PM_BFIN_WAKE_USB | |
1425 | default 0 | |
1426 | help | |
1427 | Wake-Up priority 0(low) 1(high) | |
1428 | ||
1394f032 BW |
1429 | endmenu |
1430 | ||
1394f032 BW |
1431 | menu "CPU Frequency scaling" |
1432 | ||
1433 | source "drivers/cpufreq/Kconfig" | |
1434 | ||
5ad2ca5f MH |
1435 | config BFIN_CPU_FREQ |
1436 | bool | |
1437 | depends on CPU_FREQ | |
1438 | select CPU_FREQ_TABLE | |
1439 | default y | |
1440 | ||
14b03204 MH |
1441 | config CPU_VOLTAGE |
1442 | bool "CPU Voltage scaling" | |
73feb5c0 | 1443 | depends on EXPERIMENTAL |
14b03204 MH |
1444 | depends on CPU_FREQ |
1445 | default n | |
1446 | help | |
1447 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1448 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1449 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1450 | the PLL may unlock. |
1451 | ||
1394f032 BW |
1452 | endmenu |
1453 | ||
1394f032 BW |
1454 | source "net/Kconfig" |
1455 | ||
1456 | source "drivers/Kconfig" | |
1457 | ||
872d024b MF |
1458 | source "drivers/firmware/Kconfig" |
1459 | ||
1394f032 BW |
1460 | source "fs/Kconfig" |
1461 | ||
74ce8322 | 1462 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1463 | |
1464 | source "security/Kconfig" | |
1465 | ||
1466 | source "crypto/Kconfig" | |
1467 | ||
1468 | source "lib/Kconfig" |