Commit | Line | Data |
---|---|---|
1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
bac7d89e | 9 | def_bool n |
1394f032 BW |
10 | |
11 | config FPU | |
bac7d89e | 12 | def_bool n |
1394f032 BW |
13 | |
14 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 15 | def_bool y |
1394f032 BW |
16 | |
17 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 18 | def_bool n |
1394f032 BW |
19 | |
20 | config BLACKFIN | |
bac7d89e | 21 | def_bool y |
1ee76d7e | 22 | select HAVE_FUNCTION_GRAPH_TRACER |
1c873be7 | 23 | select HAVE_FUNCTION_TRACER |
ec7748b5 | 24 | select HAVE_IDE |
538067c8 MF |
25 | select HAVE_KERNEL_GZIP |
26 | select HAVE_KERNEL_BZIP2 | |
27 | select HAVE_KERNEL_LZMA | |
42d4b839 | 28 | select HAVE_OPROFILE |
a4f0b32c | 29 | select ARCH_WANT_OPTIONAL_GPIOLIB |
1394f032 | 30 | |
ddf9ddac MF |
31 | config GENERIC_CSUM |
32 | def_bool y | |
33 | ||
70f12567 MF |
34 | config GENERIC_BUG |
35 | def_bool y | |
36 | depends on BUG | |
37 | ||
e3defffe | 38 | config ZONE_DMA |
bac7d89e | 39 | def_bool y |
e3defffe | 40 | |
1394f032 | 41 | config GENERIC_FIND_NEXT_BIT |
bac7d89e | 42 | def_bool y |
1394f032 BW |
43 | |
44 | config GENERIC_HWEIGHT | |
bac7d89e | 45 | def_bool y |
1394f032 BW |
46 | |
47 | config GENERIC_HARDIRQS | |
bac7d89e | 48 | def_bool y |
1394f032 BW |
49 | |
50 | config GENERIC_IRQ_PROBE | |
bac7d89e | 51 | def_bool y |
1394f032 | 52 | |
796dada9 MH |
53 | config GENERIC_HARDIRQS_NO__DO_IRQ |
54 | def_bool y | |
55 | ||
b2d1583f | 56 | config GENERIC_GPIO |
bac7d89e | 57 | def_bool y |
1394f032 BW |
58 | |
59 | config FORCE_MAX_ZONEORDER | |
60 | int | |
61 | default "14" | |
62 | ||
63 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 64 | def_bool y |
1394f032 | 65 | |
6fa68e7a MF |
66 | config LOCKDEP_SUPPORT |
67 | def_bool y | |
68 | ||
c7b412f4 MF |
69 | config STACKTRACE_SUPPORT |
70 | def_bool y | |
71 | ||
8f86001f MF |
72 | config TRACE_IRQFLAGS_SUPPORT |
73 | def_bool y | |
1394f032 | 74 | |
1394f032 | 75 | source "init/Kconfig" |
dc52ddc0 | 76 | |
1394f032 BW |
77 | source "kernel/Kconfig.preempt" |
78 | ||
dc52ddc0 MH |
79 | source "kernel/Kconfig.freezer" |
80 | ||
1394f032 BW |
81 | menu "Blackfin Processor Options" |
82 | ||
83 | comment "Processor and Board Settings" | |
84 | ||
85 | choice | |
86 | prompt "CPU" | |
87 | default BF533 | |
88 | ||
2f6f4bcd BW |
89 | config BF512 |
90 | bool "BF512" | |
91 | help | |
92 | BF512 Processor Support. | |
93 | ||
94 | config BF514 | |
95 | bool "BF514" | |
96 | help | |
97 | BF514 Processor Support. | |
98 | ||
99 | config BF516 | |
100 | bool "BF516" | |
101 | help | |
102 | BF516 Processor Support. | |
103 | ||
104 | config BF518 | |
105 | bool "BF518" | |
106 | help | |
107 | BF518 Processor Support. | |
108 | ||
59003145 MH |
109 | config BF522 |
110 | bool "BF522" | |
111 | help | |
112 | BF522 Processor Support. | |
113 | ||
1545a111 MF |
114 | config BF523 |
115 | bool "BF523" | |
116 | help | |
117 | BF523 Processor Support. | |
118 | ||
119 | config BF524 | |
120 | bool "BF524" | |
121 | help | |
122 | BF524 Processor Support. | |
123 | ||
59003145 MH |
124 | config BF525 |
125 | bool "BF525" | |
126 | help | |
127 | BF525 Processor Support. | |
128 | ||
1545a111 MF |
129 | config BF526 |
130 | bool "BF526" | |
131 | help | |
132 | BF526 Processor Support. | |
133 | ||
59003145 MH |
134 | config BF527 |
135 | bool "BF527" | |
136 | help | |
137 | BF527 Processor Support. | |
138 | ||
1394f032 BW |
139 | config BF531 |
140 | bool "BF531" | |
141 | help | |
142 | BF531 Processor Support. | |
143 | ||
144 | config BF532 | |
145 | bool "BF532" | |
146 | help | |
147 | BF532 Processor Support. | |
148 | ||
149 | config BF533 | |
150 | bool "BF533" | |
151 | help | |
152 | BF533 Processor Support. | |
153 | ||
154 | config BF534 | |
155 | bool "BF534" | |
156 | help | |
157 | BF534 Processor Support. | |
158 | ||
159 | config BF536 | |
160 | bool "BF536" | |
161 | help | |
162 | BF536 Processor Support. | |
163 | ||
164 | config BF537 | |
165 | bool "BF537" | |
166 | help | |
167 | BF537 Processor Support. | |
168 | ||
dc26aec2 MH |
169 | config BF538 |
170 | bool "BF538" | |
171 | help | |
172 | BF538 Processor Support. | |
173 | ||
174 | config BF539 | |
175 | bool "BF539" | |
176 | help | |
177 | BF539 Processor Support. | |
178 | ||
5df326ac | 179 | config BF542_std |
24a07a12 RH |
180 | bool "BF542" |
181 | help | |
182 | BF542 Processor Support. | |
183 | ||
2f89c063 MF |
184 | config BF542M |
185 | bool "BF542m" | |
186 | help | |
187 | BF542 Processor Support. | |
188 | ||
5df326ac | 189 | config BF544_std |
24a07a12 RH |
190 | bool "BF544" |
191 | help | |
192 | BF544 Processor Support. | |
193 | ||
2f89c063 MF |
194 | config BF544M |
195 | bool "BF544m" | |
196 | help | |
197 | BF544 Processor Support. | |
198 | ||
5df326ac | 199 | config BF547_std |
7c7fd170 MF |
200 | bool "BF547" |
201 | help | |
202 | BF547 Processor Support. | |
203 | ||
2f89c063 MF |
204 | config BF547M |
205 | bool "BF547m" | |
206 | help | |
207 | BF547 Processor Support. | |
208 | ||
5df326ac | 209 | config BF548_std |
24a07a12 RH |
210 | bool "BF548" |
211 | help | |
212 | BF548 Processor Support. | |
213 | ||
2f89c063 MF |
214 | config BF548M |
215 | bool "BF548m" | |
216 | help | |
217 | BF548 Processor Support. | |
218 | ||
5df326ac | 219 | config BF549_std |
24a07a12 RH |
220 | bool "BF549" |
221 | help | |
222 | BF549 Processor Support. | |
223 | ||
2f89c063 MF |
224 | config BF549M |
225 | bool "BF549m" | |
226 | help | |
227 | BF549 Processor Support. | |
228 | ||
1394f032 BW |
229 | config BF561 |
230 | bool "BF561" | |
231 | help | |
cd88b4dc | 232 | BF561 Processor Support. |
1394f032 BW |
233 | |
234 | endchoice | |
235 | ||
46fa5eec GY |
236 | config SMP |
237 | depends on BF561 | |
10f03f1a | 238 | select GENERIC_CLOCKEVENTS |
46fa5eec GY |
239 | bool "Symmetric multi-processing support" |
240 | ---help--- | |
241 | This enables support for systems with more than one CPU, | |
242 | like the dual core BF561. If you have a system with only one | |
243 | CPU, say N. If you have a system with more than one CPU, say Y. | |
244 | ||
245 | If you don't know what to do here, say N. | |
246 | ||
247 | config NR_CPUS | |
248 | int | |
249 | depends on SMP | |
250 | default 2 if BF561 | |
251 | ||
252 | config IRQ_PER_CPU | |
253 | bool | |
254 | depends on SMP | |
255 | default y | |
256 | ||
0c0497c2 MF |
257 | config BF_REV_MIN |
258 | int | |
2f89c063 | 259 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
0c0497c2 | 260 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 261 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 262 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
263 | |
264 | config BF_REV_MAX | |
265 | int | |
2f89c063 MF |
266 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
267 | default 3 if (BF537 || BF536 || BF534 || BF54xM) | |
2f6f4bcd | 268 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
269 | default 6 if (BF533 || BF532 || BF531) |
270 | ||
1394f032 BW |
271 | choice |
272 | prompt "Silicon Rev" | |
f8b55651 MF |
273 | default BF_REV_0_0 if (BF51x || BF52x) |
274 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) | |
2f89c063 | 275 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
276 | |
277 | config BF_REV_0_0 | |
278 | bool "0.0" | |
2f89c063 | 279 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
59003145 MH |
280 | |
281 | config BF_REV_0_1 | |
d07f4380 | 282 | bool "0.1" |
3d15f302 | 283 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
284 | |
285 | config BF_REV_0_2 | |
286 | bool "0.2" | |
2f89c063 | 287 | depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
288 | |
289 | config BF_REV_0_3 | |
290 | bool "0.3" | |
2f89c063 | 291 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
292 | |
293 | config BF_REV_0_4 | |
294 | bool "0.4" | |
dc26aec2 | 295 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
296 | |
297 | config BF_REV_0_5 | |
298 | bool "0.5" | |
dc26aec2 | 299 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 300 | |
49f7253c MF |
301 | config BF_REV_0_6 |
302 | bool "0.6" | |
303 | depends on (BF533 || BF532 || BF531) | |
304 | ||
de3025f4 JZ |
305 | config BF_REV_ANY |
306 | bool "any" | |
307 | ||
308 | config BF_REV_NONE | |
309 | bool "none" | |
310 | ||
1394f032 BW |
311 | endchoice |
312 | ||
24a07a12 RH |
313 | config BF53x |
314 | bool | |
315 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
316 | default y | |
317 | ||
1394f032 BW |
318 | config MEM_GENERIC_BOARD |
319 | bool | |
320 | depends on GENERIC_BOARD | |
321 | default y | |
322 | ||
323 | config MEM_MT48LC64M4A2FB_7E | |
324 | bool | |
325 | depends on (BFIN533_STAMP) | |
326 | default y | |
327 | ||
328 | config MEM_MT48LC16M16A2TG_75 | |
329 | bool | |
330 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
60584344 HK |
331 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
332 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ | |
333 | || BFIN527_BLUETECHNIX_CM) | |
1394f032 BW |
334 | default y |
335 | ||
336 | config MEM_MT48LC32M8A2_75 | |
337 | bool | |
dc26aec2 | 338 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
339 | default y |
340 | ||
341 | config MEM_MT48LC8M32B2B5_7 | |
342 | bool | |
343 | depends on (BFIN561_BLUETECHNIX_CM) | |
344 | default y | |
345 | ||
59003145 MH |
346 | config MEM_MT48LC32M16A2TG_75 |
347 | bool | |
ee48efb5 | 348 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP) |
59003145 MH |
349 | default y |
350 | ||
4934540d SZ |
351 | config MEM_MT48LC32M8A2_75 |
352 | bool | |
353 | depends on (BFIN518F_EZBRD) | |
354 | default y | |
355 | ||
ee48efb5 GY |
356 | config MEM_MT48H32M16LFCJ_75 |
357 | bool | |
358 | depends on (BFIN526_EZBRD) | |
359 | default y | |
360 | ||
2f6f4bcd | 361 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 362 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
363 | source "arch/blackfin/mach-bf533/Kconfig" |
364 | source "arch/blackfin/mach-bf561/Kconfig" | |
365 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 366 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 367 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
368 | |
369 | menu "Board customizations" | |
370 | ||
371 | config CMDLINE_BOOL | |
372 | bool "Default bootloader kernel arguments" | |
373 | ||
374 | config CMDLINE | |
375 | string "Initial kernel command string" | |
376 | depends on CMDLINE_BOOL | |
377 | default "console=ttyBF0,57600" | |
378 | help | |
379 | If you don't have a boot loader capable of passing a command line string | |
380 | to the kernel, you may specify one here. As a minimum, you should specify | |
381 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
382 | ||
5f004c20 MF |
383 | config BOOT_LOAD |
384 | hex "Kernel load address for booting" | |
385 | default "0x1000" | |
386 | range 0x1000 0x20000000 | |
387 | help | |
388 | This option allows you to set the load address of the kernel. | |
389 | This can be useful if you are on a board which has a small amount | |
390 | of memory or you wish to reserve some memory at the beginning of | |
391 | the address space. | |
392 | ||
393 | Note that you need to keep this value above 4k (0x1000) as this | |
394 | memory region is used to capture NULL pointer references as well | |
395 | as some core kernel functions. | |
396 | ||
8cc7117e MH |
397 | config ROM_BASE |
398 | hex "Kernel ROM Base" | |
86249911 | 399 | depends on ROMKERNEL |
8cc7117e MH |
400 | default "0x20040000" |
401 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
402 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
403 | help | |
404 | ||
f16295e7 | 405 | comment "Clock/PLL Setup" |
1394f032 BW |
406 | |
407 | config CLKIN_HZ | |
2fb6cb41 | 408 | int "Frequency of the crystal on the board in Hz" |
d0cb9b4e | 409 | default "10000000" if BFIN532_IP0X |
1394f032 | 410 | default "11059200" if BFIN533_STAMP |
d0cb9b4e MF |
411 | default "24576000" if PNAV10 |
412 | default "25000000" # most people use this | |
1394f032 | 413 | default "27000000" if BFIN533_EZKIT |
1394f032 | 414 | default "30000000" if BFIN561_EZKIT |
1394f032 BW |
415 | help |
416 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
417 | Warning: This value should match the crystal on the board. Otherwise, |
418 | peripherals won't work properly. | |
1394f032 | 419 | |
f16295e7 RG |
420 | config BFIN_KERNEL_CLOCK |
421 | bool "Re-program Clocks while Kernel boots?" | |
422 | default n | |
423 | help | |
424 | This option decides if kernel clocks are re-programed from the | |
425 | bootloader settings. If the clocks are not set, the SDRAM settings | |
426 | are also not changed, and the Bootloader does 100% of the hardware | |
427 | configuration. | |
428 | ||
429 | config PLL_BYPASS | |
e4e9a7ad MF |
430 | bool "Bypass PLL" |
431 | depends on BFIN_KERNEL_CLOCK | |
432 | default n | |
f16295e7 RG |
433 | |
434 | config CLKIN_HALF | |
435 | bool "Half Clock In" | |
436 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
437 | default n | |
438 | help | |
439 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
440 | ||
441 | config VCO_MULT | |
442 | int "VCO Multiplier" | |
443 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
444 | range 1 64 | |
445 | default "22" if BFIN533_EZKIT | |
446 | default "45" if BFIN533_STAMP | |
dc26aec2 | 447 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 448 | default "22" if BFIN533_BLUETECHNIX_CM |
60584344 | 449 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 450 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 451 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
f16295e7 RG |
452 | help |
453 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
454 | PLL Frequency = (Crystal Frequency) * (this setting) | |
455 | ||
456 | choice | |
457 | prompt "Core Clock Divider" | |
458 | depends on BFIN_KERNEL_CLOCK | |
459 | default CCLK_DIV_1 | |
460 | help | |
461 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
462 | Core Frequency = (PLL frequency) / (this setting) | |
463 | ||
464 | config CCLK_DIV_1 | |
465 | bool "1" | |
466 | ||
467 | config CCLK_DIV_2 | |
468 | bool "2" | |
469 | ||
470 | config CCLK_DIV_4 | |
471 | bool "4" | |
472 | ||
473 | config CCLK_DIV_8 | |
474 | bool "8" | |
475 | endchoice | |
476 | ||
477 | config SCLK_DIV | |
478 | int "System Clock Divider" | |
479 | depends on BFIN_KERNEL_CLOCK | |
480 | range 1 15 | |
5f004c20 | 481 | default 5 |
f16295e7 RG |
482 | help |
483 | This sets the frequency of the system clock (including SDRAM or DDR). | |
484 | This can be between 1 and 15 | |
485 | System Clock = (PLL frequency) / (this setting) | |
486 | ||
5f004c20 MF |
487 | choice |
488 | prompt "DDR SDRAM Chip Type" | |
489 | depends on BFIN_KERNEL_CLOCK | |
490 | depends on BF54x | |
491 | default MEM_MT46V32M16_5B | |
492 | ||
493 | config MEM_MT46V32M16_6T | |
494 | bool "MT46V32M16_6T" | |
495 | ||
496 | config MEM_MT46V32M16_5B | |
497 | bool "MT46V32M16_5B" | |
498 | endchoice | |
499 | ||
73feb5c0 MH |
500 | choice |
501 | prompt "DDR/SDRAM Timing" | |
502 | depends on BFIN_KERNEL_CLOCK | |
503 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
504 | help | |
505 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
506 | The calculated SDRAM timing parameters may not be 100% | |
507 | accurate - This option is therefore marked experimental. | |
508 | ||
509 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
510 | bool "Calculate Timings (EXPERIMENTAL)" | |
511 | depends on EXPERIMENTAL | |
512 | ||
513 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
514 | bool "Provide accurate Timings based on target SCLK" | |
515 | help | |
516 | Please consult the Blackfin Hardware Reference Manuals as well | |
517 | as the memory device datasheet. | |
518 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
519 | endchoice | |
520 | ||
521 | menu "Memory Init Control" | |
522 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
523 | ||
524 | config MEM_DDRCTL0 | |
525 | depends on BF54x | |
526 | hex "DDRCTL0" | |
527 | default 0x0 | |
528 | ||
529 | config MEM_DDRCTL1 | |
530 | depends on BF54x | |
531 | hex "DDRCTL1" | |
532 | default 0x0 | |
533 | ||
534 | config MEM_DDRCTL2 | |
535 | depends on BF54x | |
536 | hex "DDRCTL2" | |
537 | default 0x0 | |
538 | ||
539 | config MEM_EBIU_DDRQUE | |
540 | depends on BF54x | |
541 | hex "DDRQUE" | |
542 | default 0x0 | |
543 | ||
544 | config MEM_SDRRC | |
545 | depends on !BF54x | |
546 | hex "SDRRC" | |
547 | default 0x0 | |
548 | ||
549 | config MEM_SDGCTL | |
550 | depends on !BF54x | |
551 | hex "SDGCTL" | |
552 | default 0x0 | |
553 | endmenu | |
554 | ||
f16295e7 RG |
555 | # |
556 | # Max & Min Speeds for various Chips | |
557 | # | |
558 | config MAX_VCO_HZ | |
559 | int | |
2f6f4bcd BW |
560 | default 400000000 if BF512 |
561 | default 400000000 if BF514 | |
562 | default 400000000 if BF516 | |
563 | default 400000000 if BF518 | |
7b06263b MF |
564 | default 400000000 if BF522 |
565 | default 600000000 if BF523 | |
1545a111 | 566 | default 400000000 if BF524 |
f16295e7 | 567 | default 600000000 if BF525 |
1545a111 | 568 | default 400000000 if BF526 |
f16295e7 RG |
569 | default 600000000 if BF527 |
570 | default 400000000 if BF531 | |
571 | default 400000000 if BF532 | |
572 | default 750000000 if BF533 | |
573 | default 500000000 if BF534 | |
574 | default 400000000 if BF536 | |
575 | default 600000000 if BF537 | |
f72eecb9 RG |
576 | default 533333333 if BF538 |
577 | default 533333333 if BF539 | |
f16295e7 | 578 | default 600000000 if BF542 |
f72eecb9 | 579 | default 533333333 if BF544 |
1545a111 MF |
580 | default 600000000 if BF547 |
581 | default 600000000 if BF548 | |
f72eecb9 | 582 | default 533333333 if BF549 |
f16295e7 RG |
583 | default 600000000 if BF561 |
584 | ||
585 | config MIN_VCO_HZ | |
586 | int | |
587 | default 50000000 | |
588 | ||
589 | config MAX_SCLK_HZ | |
590 | int | |
f72eecb9 | 591 | default 133333333 |
f16295e7 RG |
592 | |
593 | config MIN_SCLK_HZ | |
594 | int | |
595 | default 27000000 | |
596 | ||
597 | comment "Kernel Timer/Scheduler" | |
598 | ||
599 | source kernel/Kconfig.hz | |
600 | ||
8b5f79f9 | 601 | config GENERIC_TIME |
10f03f1a | 602 | def_bool y |
8b5f79f9 VM |
603 | |
604 | config GENERIC_CLOCKEVENTS | |
605 | bool "Generic clock events" | |
8b5f79f9 VM |
606 | default y |
607 | ||
1fa9be72 GY |
608 | choice |
609 | prompt "Kernel Tick Source" | |
610 | depends on GENERIC_CLOCKEVENTS | |
611 | default TICKSOURCE_CORETMR | |
612 | ||
613 | config TICKSOURCE_GPTMR0 | |
614 | bool "Gptimer0 (SCLK domain)" | |
615 | select BFIN_GPTIMERS | |
1fa9be72 GY |
616 | |
617 | config TICKSOURCE_CORETMR | |
618 | bool "Core timer (CCLK domain)" | |
619 | ||
620 | endchoice | |
621 | ||
8b5f79f9 | 622 | config CYCLES_CLOCKSOURCE |
1fa9be72 | 623 | bool "Use 'CYCLES' as a clocksource" |
8b5f79f9 VM |
624 | depends on GENERIC_CLOCKEVENTS |
625 | depends on !BFIN_SCRATCH_REG_CYCLES | |
1fa9be72 | 626 | depends on !SMP |
8b5f79f9 VM |
627 | help |
628 | If you say Y here, you will enable support for using the 'cycles' | |
629 | registers as a clock source. Doing so means you will be unable to | |
630 | safely write to the 'cycles' register during runtime. You will | |
631 | still be able to read it (such as for performance monitoring), but | |
632 | writing the registers will most likely crash the kernel. | |
633 | ||
1fa9be72 | 634 | config GPTMR0_CLOCKSOURCE |
e78feaae | 635 | bool "Use GPTimer0 as a clocksource" |
3aca47c0 | 636 | select BFIN_GPTIMERS |
1fa9be72 GY |
637 | depends on GENERIC_CLOCKEVENTS |
638 | depends on !TICKSOURCE_GPTMR0 | |
639 | ||
10f03f1a | 640 | config ARCH_USES_GETTIMEOFFSET |
641 | depends on !GENERIC_CLOCKEVENTS | |
642 | def_bool y | |
643 | ||
8b5f79f9 VM |
644 | source kernel/time/Kconfig |
645 | ||
5f004c20 | 646 | comment "Misc" |
971d5bc4 | 647 | |
f0b5d12f MF |
648 | choice |
649 | prompt "Blackfin Exception Scratch Register" | |
650 | default BFIN_SCRATCH_REG_RETN | |
651 | help | |
652 | Select the resource to reserve for the Exception handler: | |
653 | - RETN: Non-Maskable Interrupt (NMI) | |
654 | - RETE: Exception Return (JTAG/ICE) | |
655 | - CYCLES: Performance counter | |
656 | ||
657 | If you are unsure, please select "RETN". | |
658 | ||
659 | config BFIN_SCRATCH_REG_RETN | |
660 | bool "RETN" | |
661 | help | |
662 | Use the RETN register in the Blackfin exception handler | |
663 | as a stack scratch register. This means you cannot | |
664 | safely use NMI on the Blackfin while running Linux, but | |
665 | you can debug the system with a JTAG ICE and use the | |
666 | CYCLES performance registers. | |
667 | ||
668 | If you are unsure, please select "RETN". | |
669 | ||
670 | config BFIN_SCRATCH_REG_RETE | |
671 | bool "RETE" | |
672 | help | |
673 | Use the RETE register in the Blackfin exception handler | |
674 | as a stack scratch register. This means you cannot | |
675 | safely use a JTAG ICE while debugging a Blackfin board, | |
676 | but you can safely use the CYCLES performance registers | |
677 | and the NMI. | |
678 | ||
679 | If you are unsure, please select "RETN". | |
680 | ||
681 | config BFIN_SCRATCH_REG_CYCLES | |
682 | bool "CYCLES" | |
683 | help | |
684 | Use the CYCLES register in the Blackfin exception handler | |
685 | as a stack scratch register. This means you cannot | |
686 | safely use the CYCLES performance registers on a Blackfin | |
687 | board at anytime, but you can debug the system with a JTAG | |
688 | ICE and use the NMI. | |
689 | ||
690 | If you are unsure, please select "RETN". | |
691 | ||
692 | endchoice | |
693 | ||
1394f032 BW |
694 | endmenu |
695 | ||
696 | ||
697 | menu "Blackfin Kernel Optimizations" | |
46fa5eec | 698 | depends on !SMP |
1394f032 | 699 | |
1394f032 BW |
700 | comment "Memory Optimizations" |
701 | ||
702 | config I_ENTRY_L1 | |
703 | bool "Locate interrupt entry code in L1 Memory" | |
704 | default y | |
705 | help | |
01dd2fbf ML |
706 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
707 | into L1 instruction memory. (less latency) | |
1394f032 BW |
708 | |
709 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 710 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
711 | default y |
712 | help | |
01dd2fbf | 713 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 714 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 715 | (less latency) |
1394f032 BW |
716 | |
717 | config DO_IRQ_L1 | |
718 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
719 | default y | |
720 | help | |
01dd2fbf ML |
721 | If enabled, the frequently called do_irq dispatcher function is linked |
722 | into L1 instruction memory. (less latency) | |
1394f032 BW |
723 | |
724 | config CORE_TIMER_IRQ_L1 | |
725 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
726 | default y | |
727 | help | |
01dd2fbf ML |
728 | If enabled, the frequently called timer_interrupt() function is linked |
729 | into L1 instruction memory. (less latency) | |
1394f032 BW |
730 | |
731 | config IDLE_L1 | |
732 | bool "Locate frequently idle function in L1 Memory" | |
733 | default y | |
734 | help | |
01dd2fbf ML |
735 | If enabled, the frequently called idle function is linked |
736 | into L1 instruction memory. (less latency) | |
1394f032 BW |
737 | |
738 | config SCHEDULE_L1 | |
739 | bool "Locate kernel schedule function in L1 Memory" | |
740 | default y | |
741 | help | |
01dd2fbf ML |
742 | If enabled, the frequently called kernel schedule is linked |
743 | into L1 instruction memory. (less latency) | |
1394f032 BW |
744 | |
745 | config ARITHMETIC_OPS_L1 | |
746 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
747 | default y | |
748 | help | |
01dd2fbf ML |
749 | If enabled, arithmetic functions are linked |
750 | into L1 instruction memory. (less latency) | |
1394f032 BW |
751 | |
752 | config ACCESS_OK_L1 | |
753 | bool "Locate access_ok function in L1 Memory" | |
754 | default y | |
755 | help | |
01dd2fbf ML |
756 | If enabled, the access_ok function is linked |
757 | into L1 instruction memory. (less latency) | |
1394f032 BW |
758 | |
759 | config MEMSET_L1 | |
760 | bool "Locate memset function in L1 Memory" | |
761 | default y | |
762 | help | |
01dd2fbf ML |
763 | If enabled, the memset function is linked |
764 | into L1 instruction memory. (less latency) | |
1394f032 BW |
765 | |
766 | config MEMCPY_L1 | |
767 | bool "Locate memcpy function in L1 Memory" | |
768 | default y | |
769 | help | |
01dd2fbf ML |
770 | If enabled, the memcpy function is linked |
771 | into L1 instruction memory. (less latency) | |
1394f032 BW |
772 | |
773 | config SYS_BFIN_SPINLOCK_L1 | |
774 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
775 | default y | |
776 | help | |
01dd2fbf ML |
777 | If enabled, sys_bfin_spinlock function is linked |
778 | into L1 instruction memory. (less latency) | |
1394f032 BW |
779 | |
780 | config IP_CHECKSUM_L1 | |
781 | bool "Locate IP Checksum function in L1 Memory" | |
782 | default n | |
783 | help | |
01dd2fbf ML |
784 | If enabled, the IP Checksum function is linked |
785 | into L1 instruction memory. (less latency) | |
1394f032 BW |
786 | |
787 | config CACHELINE_ALIGNED_L1 | |
788 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
789 | default y if !BF54x |
790 | default n if BF54x | |
1394f032 BW |
791 | depends on !BF531 |
792 | help | |
692105b8 | 793 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 794 | into L1 data memory. (less latency) |
1394f032 BW |
795 | |
796 | config SYSCALL_TAB_L1 | |
797 | bool "Locate Syscall Table L1 Data Memory" | |
798 | default n | |
799 | depends on !BF531 | |
800 | help | |
01dd2fbf ML |
801 | If enabled, the Syscall LUT is linked |
802 | into L1 data memory. (less latency) | |
1394f032 BW |
803 | |
804 | config CPLB_SWITCH_TAB_L1 | |
805 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
806 | default n | |
807 | depends on !BF531 | |
808 | help | |
01dd2fbf ML |
809 | If enabled, the CPLB Switch Tables are linked |
810 | into L1 data memory. (less latency) | |
1394f032 | 811 | |
ca87b7ad GY |
812 | config APP_STACK_L1 |
813 | bool "Support locating application stack in L1 Scratch Memory" | |
814 | default y | |
815 | help | |
816 | If enabled the application stack can be located in L1 | |
817 | scratch memory (less latency). | |
818 | ||
819 | Currently only works with FLAT binaries. | |
820 | ||
6ad2b84c MF |
821 | config EXCEPTION_L1_SCRATCH |
822 | bool "Locate exception stack in L1 Scratch Memory" | |
823 | default n | |
f82e0a0c | 824 | depends on !APP_STACK_L1 |
6ad2b84c MF |
825 | help |
826 | Whenever an exception occurs, use the L1 Scratch memory for | |
827 | stack storage. You cannot place the stacks of FLAT binaries | |
828 | in L1 when using this option. | |
829 | ||
830 | If you don't use L1 Scratch, then you should say Y here. | |
831 | ||
251383c7 RG |
832 | comment "Speed Optimizations" |
833 | config BFIN_INS_LOWOVERHEAD | |
834 | bool "ins[bwl] low overhead, higher interrupt latency" | |
835 | default y | |
836 | help | |
837 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
838 | they can be interrupted at any time (even after they have been issued | |
839 | on to the external bus), and re-issued after the interrupt occurs. | |
840 | For memory - this is not a big deal, since memory does not change if | |
841 | it sees a read. | |
842 | ||
843 | If a FIFO is sitting on the end of the read, it will see two reads, | |
844 | when the core only sees one since the FIFO receives both the read | |
845 | which is cancelled (and not delivered to the core) and the one which | |
846 | is re-issued (which is delivered to the core). | |
847 | ||
848 | To solve this, interrupts are turned off before reads occur to | |
849 | I/O space. This option controls which the overhead/latency of | |
850 | controlling interrupts during this time | |
851 | "n" turns interrupts off every read | |
852 | (higher overhead, but lower interrupt latency) | |
853 | "y" turns interrupts off every loop | |
854 | (low overhead, but longer interrupt latency) | |
855 | ||
856 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
857 | interrupt latency issues, it is safe and OK to turn this off. | |
858 | ||
1394f032 BW |
859 | endmenu |
860 | ||
1394f032 BW |
861 | choice |
862 | prompt "Kernel executes from" | |
863 | help | |
864 | Choose the memory type that the kernel will be running in. | |
865 | ||
866 | config RAMKERNEL | |
867 | bool "RAM" | |
868 | help | |
869 | The kernel will be resident in RAM when running. | |
870 | ||
871 | config ROMKERNEL | |
872 | bool "ROM" | |
873 | help | |
874 | The kernel will be resident in FLASH/ROM when running. | |
875 | ||
876 | endchoice | |
877 | ||
878 | source "mm/Kconfig" | |
879 | ||
780431e3 MF |
880 | config BFIN_GPTIMERS |
881 | tristate "Enable Blackfin General Purpose Timers API" | |
882 | default n | |
883 | help | |
884 | Enable support for the General Purpose Timers API. If you | |
885 | are unsure, say N. | |
886 | ||
887 | To compile this driver as a module, choose M here: the module | |
4737f097 | 888 | will be called gptimers. |
780431e3 | 889 | |
1394f032 | 890 | choice |
d292b000 | 891 | prompt "Uncached DMA region" |
1394f032 | 892 | default DMA_UNCACHED_1M |
86ad7932 CC |
893 | config DMA_UNCACHED_4M |
894 | bool "Enable 4M DMA region" | |
1394f032 BW |
895 | config DMA_UNCACHED_2M |
896 | bool "Enable 2M DMA region" | |
897 | config DMA_UNCACHED_1M | |
898 | bool "Enable 1M DMA region" | |
899 | config DMA_UNCACHED_NONE | |
900 | bool "Disable DMA region" | |
901 | endchoice | |
902 | ||
903 | ||
904 | comment "Cache Support" | |
41ba653f | 905 | |
3bebca2d | 906 | config BFIN_ICACHE |
1394f032 | 907 | bool "Enable ICACHE" |
41ba653f | 908 | default y |
41ba653f JZ |
909 | config BFIN_EXTMEM_ICACHEABLE |
910 | bool "Enable ICACHE for external memory" | |
911 | depends on BFIN_ICACHE | |
912 | default y | |
913 | config BFIN_L2_ICACHEABLE | |
914 | bool "Enable ICACHE for L2 SRAM" | |
915 | depends on BFIN_ICACHE | |
916 | depends on BF54x || BF561 | |
917 | default n | |
918 | ||
3bebca2d | 919 | config BFIN_DCACHE |
1394f032 | 920 | bool "Enable DCACHE" |
41ba653f | 921 | default y |
3bebca2d | 922 | config BFIN_DCACHE_BANKA |
1394f032 | 923 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 924 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 925 | default n |
41ba653f JZ |
926 | config BFIN_EXTMEM_DCACHEABLE |
927 | bool "Enable DCACHE for external memory" | |
3bebca2d | 928 | depends on BFIN_DCACHE |
41ba653f JZ |
929 | default y |
930 | choice | |
931 | prompt "External memory DCACHE policy" | |
932 | depends on BFIN_EXTMEM_DCACHEABLE | |
933 | default BFIN_EXTMEM_WRITEBACK if !SMP | |
934 | default BFIN_EXTMEM_WRITETHROUGH if SMP | |
935 | config BFIN_EXTMEM_WRITEBACK | |
1394f032 | 936 | bool "Write back" |
46fa5eec | 937 | depends on !SMP |
1394f032 BW |
938 | help |
939 | Write Back Policy: | |
940 | Cached data will be written back to SDRAM only when needed. | |
941 | This can give a nice increase in performance, but beware of | |
942 | broken drivers that do not properly invalidate/flush their | |
943 | cache. | |
944 | ||
945 | Write Through Policy: | |
946 | Cached data will always be written back to SDRAM when the | |
947 | cache is updated. This is a completely safe setting, but | |
948 | performance is worse than Write Back. | |
949 | ||
950 | If you are unsure of the options and you want to be safe, | |
951 | then go with Write Through. | |
952 | ||
41ba653f | 953 | config BFIN_EXTMEM_WRITETHROUGH |
1394f032 BW |
954 | bool "Write through" |
955 | help | |
956 | Write Back Policy: | |
957 | Cached data will be written back to SDRAM only when needed. | |
958 | This can give a nice increase in performance, but beware of | |
959 | broken drivers that do not properly invalidate/flush their | |
960 | cache. | |
961 | ||
962 | Write Through Policy: | |
963 | Cached data will always be written back to SDRAM when the | |
964 | cache is updated. This is a completely safe setting, but | |
965 | performance is worse than Write Back. | |
966 | ||
967 | If you are unsure of the options and you want to be safe, | |
968 | then go with Write Through. | |
969 | ||
970 | endchoice | |
971 | ||
41ba653f JZ |
972 | config BFIN_L2_DCACHEABLE |
973 | bool "Enable DCACHE for L2 SRAM" | |
974 | depends on BFIN_DCACHE | |
9c954f89 | 975 | depends on (BF54x || BF561) && !SMP |
41ba653f | 976 | default n |
5ba76675 | 977 | choice |
41ba653f JZ |
978 | prompt "L2 SRAM DCACHE policy" |
979 | depends on BFIN_L2_DCACHEABLE | |
980 | default BFIN_L2_WRITEBACK | |
981 | config BFIN_L2_WRITEBACK | |
5ba76675 | 982 | bool "Write back" |
5ba76675 | 983 | |
41ba653f | 984 | config BFIN_L2_WRITETHROUGH |
5ba76675 | 985 | bool "Write through" |
5ba76675 | 986 | endchoice |
f099f39a | 987 | |
41ba653f JZ |
988 | |
989 | comment "Memory Protection Unit" | |
b97b8a99 BS |
990 | config MPU |
991 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
992 | default n | |
993 | help | |
994 | Use the processor's MPU to protect applications from accessing | |
995 | memory they do not own. This comes at a performance penalty | |
996 | and is recommended only for debugging. | |
997 | ||
692105b8 | 998 | comment "Asynchronous Memory Configuration" |
1394f032 | 999 | |
ddf416b2 | 1000 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
1001 | config C_AMCKEN |
1002 | bool "Enable CLKOUT" | |
1003 | default y | |
1004 | ||
1005 | config C_CDPRIO | |
1006 | bool "DMA has priority over core for ext. accesses" | |
1007 | default n | |
1008 | ||
1009 | config C_B0PEN | |
1010 | depends on BF561 | |
1011 | bool "Bank 0 16 bit packing enable" | |
1012 | default y | |
1013 | ||
1014 | config C_B1PEN | |
1015 | depends on BF561 | |
1016 | bool "Bank 1 16 bit packing enable" | |
1017 | default y | |
1018 | ||
1019 | config C_B2PEN | |
1020 | depends on BF561 | |
1021 | bool "Bank 2 16 bit packing enable" | |
1022 | default y | |
1023 | ||
1024 | config C_B3PEN | |
1025 | depends on BF561 | |
1026 | bool "Bank 3 16 bit packing enable" | |
1027 | default n | |
1028 | ||
1029 | choice | |
692105b8 | 1030 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1031 | default C_AMBEN_ALL |
1032 | ||
1033 | config C_AMBEN | |
1034 | bool "Disable All Banks" | |
1035 | ||
1036 | config C_AMBEN_B0 | |
1037 | bool "Enable Bank 0" | |
1038 | ||
1039 | config C_AMBEN_B0_B1 | |
1040 | bool "Enable Bank 0 & 1" | |
1041 | ||
1042 | config C_AMBEN_B0_B1_B2 | |
1043 | bool "Enable Bank 0 & 1 & 2" | |
1044 | ||
1045 | config C_AMBEN_ALL | |
1046 | bool "Enable All Banks" | |
1047 | endchoice | |
1048 | endmenu | |
1049 | ||
1050 | menu "EBIU_AMBCTL Control" | |
1051 | config BANK_0 | |
c8342f87 | 1052 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1053 | default 0x7BB0 |
c8342f87 MF |
1054 | help |
1055 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1056 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1057 | |
1058 | config BANK_1 | |
c8342f87 | 1059 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1060 | default 0x7BB0 |
197fba56 | 1061 | default 0x5558 if BF54x |
c8342f87 MF |
1062 | help |
1063 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1064 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1065 | |
1066 | config BANK_2 | |
c8342f87 | 1067 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1068 | default 0x7BB0 |
c8342f87 MF |
1069 | help |
1070 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1071 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1072 | |
1073 | config BANK_3 | |
c8342f87 | 1074 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1075 | default 0x99B3 |
c8342f87 MF |
1076 | help |
1077 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1078 | used to control the Asynchronous Memory Bank 3 settings. | |
1079 | ||
1394f032 BW |
1080 | endmenu |
1081 | ||
e40540b3 SZ |
1082 | config EBIU_MBSCTLVAL |
1083 | hex "EBIU Bank Select Control Register" | |
1084 | depends on BF54x | |
1085 | default 0 | |
1086 | ||
1087 | config EBIU_MODEVAL | |
1088 | hex "Flash Memory Mode Control Register" | |
1089 | depends on BF54x | |
1090 | default 1 | |
1091 | ||
1092 | config EBIU_FCTLVAL | |
1093 | hex "Flash Memory Bank Control Register" | |
1094 | depends on BF54x | |
1095 | default 6 | |
1394f032 BW |
1096 | endmenu |
1097 | ||
1098 | ############################################################################# | |
1099 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1100 | ||
1101 | config PCI | |
1102 | bool "PCI support" | |
a95ca3b2 | 1103 | depends on BROKEN |
1394f032 BW |
1104 | help |
1105 | Support for PCI bus. | |
1106 | ||
1107 | source "drivers/pci/Kconfig" | |
1108 | ||
1109 | config HOTPLUG | |
1110 | bool "Support for hot-pluggable device" | |
1111 | help | |
1112 | Say Y here if you want to plug devices into your computer while | |
1113 | the system is running, and be able to use them quickly. In many | |
1114 | cases, the devices can likewise be unplugged at any time too. | |
1115 | ||
1116 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
1117 | size devices such as network cards, modems or hard drives which are | |
1118 | plugged into slots found on all modern laptop computers. Another | |
1119 | example, used on modern desktops as well as laptops, is USB. | |
1120 | ||
a81792f6 JB |
1121 | Enable HOTPLUG and build a modular kernel. Get agent software |
1122 | (from <http://linux-hotplug.sourceforge.net/>) and install it. | |
1394f032 BW |
1123 | Then your kernel will automatically call out to a user mode "policy |
1124 | agent" (/sbin/hotplug) to load modules and set up software needed | |
1125 | to use devices as you hotplug them. | |
1126 | ||
1127 | source "drivers/pcmcia/Kconfig" | |
1128 | ||
1129 | source "drivers/pci/hotplug/Kconfig" | |
1130 | ||
1131 | endmenu | |
1132 | ||
1133 | menu "Executable file formats" | |
1134 | ||
1135 | source "fs/Kconfig.binfmt" | |
1136 | ||
1137 | endmenu | |
1138 | ||
1139 | menu "Power management options" | |
ad46163a GY |
1140 | depends on !SMP |
1141 | ||
1394f032 BW |
1142 | source "kernel/power/Kconfig" |
1143 | ||
f4cb5700 JB |
1144 | config ARCH_SUSPEND_POSSIBLE |
1145 | def_bool y | |
f4cb5700 | 1146 | |
1394f032 | 1147 | choice |
1efc80b5 | 1148 | prompt "Standby Power Saving Mode" |
1394f032 | 1149 | depends on PM |
cfefe3c6 MH |
1150 | default PM_BFIN_SLEEP_DEEPER |
1151 | config PM_BFIN_SLEEP_DEEPER | |
1152 | bool "Sleep Deeper" | |
1153 | help | |
1154 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1155 | power dissipation by disabling the clock to the processor core (CCLK). | |
1156 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1157 | to 0.85 V to provide the greatest power savings, while preserving the | |
1158 | processor state. | |
1159 | The PLL and system clock (SCLK) continue to operate at a very low | |
1160 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1161 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1162 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1163 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1164 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1165 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1166 | ||
1efc80b5 MH |
1167 | If unsure, select "Sleep Deeper". |
1168 | ||
cfefe3c6 MH |
1169 | config PM_BFIN_SLEEP |
1170 | bool "Sleep" | |
1171 | help | |
1172 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1173 | dissipation by disabling the clock to the processor core (CCLK). | |
1174 | The PLL and system clock (SCLK), however, continue to operate in | |
1175 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1176 | up the processor. When in the sleep mode, system DMA access to L1 |
1177 | memory is not supported. | |
1178 | ||
1179 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1180 | endchoice |
1394f032 | 1181 | |
1394f032 | 1182 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 1183 | bool "Allow Wakeup from Standby by GPIO" |
ff19fed4 | 1184 | depends on PM && !BF54x |
1394f032 BW |
1185 | |
1186 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 1187 | int "GPIO number" |
1394f032 BW |
1188 | range 0 47 |
1189 | depends on PM_WAKEUP_BY_GPIO | |
d1a3336e | 1190 | default 2 |
1394f032 BW |
1191 | |
1192 | choice | |
1193 | prompt "GPIO Polarity" | |
1194 | depends on PM_WAKEUP_BY_GPIO | |
1195 | default PM_WAKEUP_GPIO_POLAR_H | |
1196 | config PM_WAKEUP_GPIO_POLAR_H | |
1197 | bool "Active High" | |
1198 | config PM_WAKEUP_GPIO_POLAR_L | |
1199 | bool "Active Low" | |
1200 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
1201 | bool "Falling EDGE" | |
1202 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
1203 | bool "Rising EDGE" | |
1204 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
1205 | bool "Both EDGE" | |
1206 | endchoice | |
1207 | ||
1efc80b5 MH |
1208 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1209 | depends on PM | |
1210 | ||
1efc80b5 MH |
1211 | config PM_BFIN_WAKE_PH6 |
1212 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1213 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1214 | default n |
1215 | help | |
1216 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1217 | ||
1efc80b5 MH |
1218 | config PM_BFIN_WAKE_GP |
1219 | bool "Allow Wake-Up from GPIOs" | |
1220 | depends on PM && BF54x | |
1221 | default n | |
1222 | help | |
1223 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1224 | (all processors, except ADSP-BF549). This option sets |
1225 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1226 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
1227 | On ADSP-BF549 this option enables the the same functionality on the | |
1228 | /MRXON pin also PH7. | |
1229 | ||
1394f032 BW |
1230 | endmenu |
1231 | ||
1394f032 | 1232 | menu "CPU Frequency scaling" |
ad46163a | 1233 | depends on !SMP |
1394f032 BW |
1234 | |
1235 | source "drivers/cpufreq/Kconfig" | |
1236 | ||
5ad2ca5f MH |
1237 | config BFIN_CPU_FREQ |
1238 | bool | |
1239 | depends on CPU_FREQ | |
1240 | select CPU_FREQ_TABLE | |
1241 | default y | |
1242 | ||
14b03204 MH |
1243 | config CPU_VOLTAGE |
1244 | bool "CPU Voltage scaling" | |
73feb5c0 | 1245 | depends on EXPERIMENTAL |
14b03204 MH |
1246 | depends on CPU_FREQ |
1247 | default n | |
1248 | help | |
1249 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1250 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1251 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1252 | the PLL may unlock. |
1253 | ||
1394f032 BW |
1254 | endmenu |
1255 | ||
1394f032 BW |
1256 | source "net/Kconfig" |
1257 | ||
1258 | source "drivers/Kconfig" | |
1259 | ||
872d024b MF |
1260 | source "drivers/firmware/Kconfig" |
1261 | ||
1394f032 BW |
1262 | source "fs/Kconfig" |
1263 | ||
74ce8322 | 1264 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1265 | |
1266 | source "security/Kconfig" | |
1267 | ||
1268 | source "crypto/Kconfig" | |
1269 | ||
1270 | source "lib/Kconfig" |