Commit | Line | Data |
---|---|---|
9e1b9b80 AJ |
1 | config SYMBOL_PREFIX |
2 | string | |
3 | default "_" | |
4 | ||
1394f032 | 5 | config MMU |
bac7d89e | 6 | def_bool n |
1394f032 BW |
7 | |
8 | config FPU | |
bac7d89e | 9 | def_bool n |
1394f032 BW |
10 | |
11 | config RWSEM_GENERIC_SPINLOCK | |
bac7d89e | 12 | def_bool y |
1394f032 BW |
13 | |
14 | config RWSEM_XCHGADD_ALGORITHM | |
bac7d89e | 15 | def_bool n |
1394f032 BW |
16 | |
17 | config BLACKFIN | |
bac7d89e | 18 | def_bool y |
652afdc3 | 19 | select HAVE_ARCH_KGDB |
e8f263df | 20 | select HAVE_ARCH_TRACEHOOK |
f5074429 MF |
21 | select HAVE_DYNAMIC_FTRACE |
22 | select HAVE_FTRACE_MCOUNT_RECORD | |
1ee76d7e | 23 | select HAVE_FUNCTION_GRAPH_TRACER |
1c873be7 | 24 | select HAVE_FUNCTION_TRACER |
aebfef03 | 25 | select HAVE_FUNCTION_TRACE_MCOUNT_TEST |
ec7748b5 | 26 | select HAVE_IDE |
7db79172 | 27 | select HAVE_IRQ_WORK |
d86bfb16 BS |
28 | select HAVE_KERNEL_GZIP if RAMKERNEL |
29 | select HAVE_KERNEL_BZIP2 if RAMKERNEL | |
30 | select HAVE_KERNEL_LZMA if RAMKERNEL | |
67df6cc6 | 31 | select HAVE_KERNEL_LZO if RAMKERNEL |
42d4b839 | 32 | select HAVE_OPROFILE |
7db79172 | 33 | select HAVE_PERF_EVENTS |
7563bbf8 | 34 | select ARCH_HAVE_CUSTOM_GPIO_H |
a4f0b32c | 35 | select ARCH_WANT_OPTIONAL_GPIOLIB |
7b028863 | 36 | select HAVE_GENERIC_HARDIRQS |
bee18beb | 37 | select GENERIC_ATOMIC64 |
7b028863 TG |
38 | select GENERIC_IRQ_PROBE |
39 | select IRQ_PER_CPU if SMP | |
d314d74c | 40 | select HAVE_NMI_WATCHDOG if NMI_WATCHDOG |
1394f032 | 41 | |
ddf9ddac MF |
42 | config GENERIC_CSUM |
43 | def_bool y | |
44 | ||
70f12567 MF |
45 | config GENERIC_BUG |
46 | def_bool y | |
47 | depends on BUG | |
48 | ||
e3defffe | 49 | config ZONE_DMA |
bac7d89e | 50 | def_bool y |
e3defffe | 51 | |
b2d1583f | 52 | config GENERIC_GPIO |
bac7d89e | 53 | def_bool y |
1394f032 BW |
54 | |
55 | config FORCE_MAX_ZONEORDER | |
56 | int | |
57 | default "14" | |
58 | ||
59 | config GENERIC_CALIBRATE_DELAY | |
bac7d89e | 60 | def_bool y |
1394f032 | 61 | |
6fa68e7a MF |
62 | config LOCKDEP_SUPPORT |
63 | def_bool y | |
64 | ||
c7b412f4 MF |
65 | config STACKTRACE_SUPPORT |
66 | def_bool y | |
67 | ||
8f86001f MF |
68 | config TRACE_IRQFLAGS_SUPPORT |
69 | def_bool y | |
1394f032 | 70 | |
1394f032 | 71 | source "init/Kconfig" |
dc52ddc0 | 72 | |
1394f032 BW |
73 | source "kernel/Kconfig.preempt" |
74 | ||
dc52ddc0 MH |
75 | source "kernel/Kconfig.freezer" |
76 | ||
1394f032 BW |
77 | menu "Blackfin Processor Options" |
78 | ||
79 | comment "Processor and Board Settings" | |
80 | ||
81 | choice | |
82 | prompt "CPU" | |
83 | default BF533 | |
84 | ||
2f6f4bcd BW |
85 | config BF512 |
86 | bool "BF512" | |
87 | help | |
88 | BF512 Processor Support. | |
89 | ||
90 | config BF514 | |
91 | bool "BF514" | |
92 | help | |
93 | BF514 Processor Support. | |
94 | ||
95 | config BF516 | |
96 | bool "BF516" | |
97 | help | |
98 | BF516 Processor Support. | |
99 | ||
100 | config BF518 | |
101 | bool "BF518" | |
102 | help | |
103 | BF518 Processor Support. | |
104 | ||
59003145 MH |
105 | config BF522 |
106 | bool "BF522" | |
107 | help | |
108 | BF522 Processor Support. | |
109 | ||
1545a111 MF |
110 | config BF523 |
111 | bool "BF523" | |
112 | help | |
113 | BF523 Processor Support. | |
114 | ||
115 | config BF524 | |
116 | bool "BF524" | |
117 | help | |
118 | BF524 Processor Support. | |
119 | ||
59003145 MH |
120 | config BF525 |
121 | bool "BF525" | |
122 | help | |
123 | BF525 Processor Support. | |
124 | ||
1545a111 MF |
125 | config BF526 |
126 | bool "BF526" | |
127 | help | |
128 | BF526 Processor Support. | |
129 | ||
59003145 MH |
130 | config BF527 |
131 | bool "BF527" | |
132 | help | |
133 | BF527 Processor Support. | |
134 | ||
1394f032 BW |
135 | config BF531 |
136 | bool "BF531" | |
137 | help | |
138 | BF531 Processor Support. | |
139 | ||
140 | config BF532 | |
141 | bool "BF532" | |
142 | help | |
143 | BF532 Processor Support. | |
144 | ||
145 | config BF533 | |
146 | bool "BF533" | |
147 | help | |
148 | BF533 Processor Support. | |
149 | ||
150 | config BF534 | |
151 | bool "BF534" | |
152 | help | |
153 | BF534 Processor Support. | |
154 | ||
155 | config BF536 | |
156 | bool "BF536" | |
157 | help | |
158 | BF536 Processor Support. | |
159 | ||
160 | config BF537 | |
161 | bool "BF537" | |
162 | help | |
163 | BF537 Processor Support. | |
164 | ||
dc26aec2 MH |
165 | config BF538 |
166 | bool "BF538" | |
167 | help | |
168 | BF538 Processor Support. | |
169 | ||
170 | config BF539 | |
171 | bool "BF539" | |
172 | help | |
173 | BF539 Processor Support. | |
174 | ||
5df326ac | 175 | config BF542_std |
24a07a12 RH |
176 | bool "BF542" |
177 | help | |
178 | BF542 Processor Support. | |
179 | ||
2f89c063 MF |
180 | config BF542M |
181 | bool "BF542m" | |
182 | help | |
183 | BF542 Processor Support. | |
184 | ||
5df326ac | 185 | config BF544_std |
24a07a12 RH |
186 | bool "BF544" |
187 | help | |
188 | BF544 Processor Support. | |
189 | ||
2f89c063 MF |
190 | config BF544M |
191 | bool "BF544m" | |
192 | help | |
193 | BF544 Processor Support. | |
194 | ||
5df326ac | 195 | config BF547_std |
7c7fd170 MF |
196 | bool "BF547" |
197 | help | |
198 | BF547 Processor Support. | |
199 | ||
2f89c063 MF |
200 | config BF547M |
201 | bool "BF547m" | |
202 | help | |
203 | BF547 Processor Support. | |
204 | ||
5df326ac | 205 | config BF548_std |
24a07a12 RH |
206 | bool "BF548" |
207 | help | |
208 | BF548 Processor Support. | |
209 | ||
2f89c063 MF |
210 | config BF548M |
211 | bool "BF548m" | |
212 | help | |
213 | BF548 Processor Support. | |
214 | ||
5df326ac | 215 | config BF549_std |
24a07a12 RH |
216 | bool "BF549" |
217 | help | |
218 | BF549 Processor Support. | |
219 | ||
2f89c063 MF |
220 | config BF549M |
221 | bool "BF549m" | |
222 | help | |
223 | BF549 Processor Support. | |
224 | ||
1394f032 BW |
225 | config BF561 |
226 | bool "BF561" | |
227 | help | |
cd88b4dc | 228 | BF561 Processor Support. |
1394f032 BW |
229 | |
230 | endchoice | |
231 | ||
46fa5eec GY |
232 | config SMP |
233 | depends on BF561 | |
0d152c27 | 234 | select TICKSOURCE_CORETMR |
46fa5eec GY |
235 | bool "Symmetric multi-processing support" |
236 | ---help--- | |
237 | This enables support for systems with more than one CPU, | |
238 | like the dual core BF561. If you have a system with only one | |
239 | CPU, say N. If you have a system with more than one CPU, say Y. | |
240 | ||
241 | If you don't know what to do here, say N. | |
242 | ||
243 | config NR_CPUS | |
244 | int | |
245 | depends on SMP | |
246 | default 2 if BF561 | |
247 | ||
0b39db28 GY |
248 | config HOTPLUG_CPU |
249 | bool "Support for hot-pluggable CPUs" | |
250 | depends on SMP && HOTPLUG | |
251 | default y | |
252 | ||
0c0497c2 MF |
253 | config BF_REV_MIN |
254 | int | |
2f89c063 | 255 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
0c0497c2 | 256 | default 2 if (BF537 || BF536 || BF534) |
2f89c063 | 257 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
2f6f4bcd | 258 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
259 | |
260 | config BF_REV_MAX | |
261 | int | |
2f89c063 MF |
262 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
263 | default 3 if (BF537 || BF536 || BF534 || BF54xM) | |
2f6f4bcd | 264 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
265 | default 6 if (BF533 || BF532 || BF531) |
266 | ||
1394f032 BW |
267 | choice |
268 | prompt "Silicon Rev" | |
f8b55651 MF |
269 | default BF_REV_0_0 if (BF51x || BF52x) |
270 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) | |
2f89c063 | 271 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
24a07a12 RH |
272 | |
273 | config BF_REV_0_0 | |
274 | bool "0.0" | |
2f89c063 | 275 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
59003145 MH |
276 | |
277 | config BF_REV_0_1 | |
d07f4380 | 278 | bool "0.1" |
3d15f302 | 279 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
1394f032 BW |
280 | |
281 | config BF_REV_0_2 | |
282 | bool "0.2" | |
8060bb6f | 283 | depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
1394f032 BW |
284 | |
285 | config BF_REV_0_3 | |
286 | bool "0.3" | |
2f89c063 | 287 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
1394f032 BW |
288 | |
289 | config BF_REV_0_4 | |
290 | bool "0.4" | |
dc26aec2 | 291 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
292 | |
293 | config BF_REV_0_5 | |
294 | bool "0.5" | |
dc26aec2 | 295 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 296 | |
49f7253c MF |
297 | config BF_REV_0_6 |
298 | bool "0.6" | |
299 | depends on (BF533 || BF532 || BF531) | |
300 | ||
de3025f4 JZ |
301 | config BF_REV_ANY |
302 | bool "any" | |
303 | ||
304 | config BF_REV_NONE | |
305 | bool "none" | |
306 | ||
1394f032 BW |
307 | endchoice |
308 | ||
24a07a12 RH |
309 | config BF53x |
310 | bool | |
311 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
312 | default y | |
313 | ||
1394f032 BW |
314 | config MEM_MT48LC64M4A2FB_7E |
315 | bool | |
316 | depends on (BFIN533_STAMP) | |
317 | default y | |
318 | ||
319 | config MEM_MT48LC16M16A2TG_75 | |
320 | bool | |
321 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
60584344 HK |
322 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ |
323 | || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ | |
324 | || BFIN527_BLUETECHNIX_CM) | |
1394f032 BW |
325 | default y |
326 | ||
327 | config MEM_MT48LC32M8A2_75 | |
328 | bool | |
084f9ebf | 329 | depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
330 | default y |
331 | ||
332 | config MEM_MT48LC8M32B2B5_7 | |
333 | bool | |
334 | depends on (BFIN561_BLUETECHNIX_CM) | |
335 | default y | |
336 | ||
59003145 MH |
337 | config MEM_MT48LC32M16A2TG_75 |
338 | bool | |
8effc4a6 | 339 | depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) |
59003145 MH |
340 | default y |
341 | ||
ee48efb5 GY |
342 | config MEM_MT48H32M16LFCJ_75 |
343 | bool | |
344 | depends on (BFIN526_EZBRD) | |
345 | default y | |
346 | ||
2f6f4bcd | 347 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 348 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
349 | source "arch/blackfin/mach-bf533/Kconfig" |
350 | source "arch/blackfin/mach-bf561/Kconfig" | |
351 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 352 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 353 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
354 | |
355 | menu "Board customizations" | |
356 | ||
357 | config CMDLINE_BOOL | |
358 | bool "Default bootloader kernel arguments" | |
359 | ||
360 | config CMDLINE | |
361 | string "Initial kernel command string" | |
362 | depends on CMDLINE_BOOL | |
363 | default "console=ttyBF0,57600" | |
364 | help | |
365 | If you don't have a boot loader capable of passing a command line string | |
366 | to the kernel, you may specify one here. As a minimum, you should specify | |
367 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
368 | ||
5f004c20 MF |
369 | config BOOT_LOAD |
370 | hex "Kernel load address for booting" | |
371 | default "0x1000" | |
372 | range 0x1000 0x20000000 | |
373 | help | |
374 | This option allows you to set the load address of the kernel. | |
375 | This can be useful if you are on a board which has a small amount | |
376 | of memory or you wish to reserve some memory at the beginning of | |
377 | the address space. | |
378 | ||
379 | Note that you need to keep this value above 4k (0x1000) as this | |
380 | memory region is used to capture NULL pointer references as well | |
381 | as some core kernel functions. | |
382 | ||
8cc7117e MH |
383 | config ROM_BASE |
384 | hex "Kernel ROM Base" | |
86249911 | 385 | depends on ROMKERNEL |
d86bfb16 | 386 | default "0x20040040" |
8cc7117e MH |
387 | range 0x20000000 0x20400000 if !(BF54x || BF561) |
388 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
389 | help | |
d86bfb16 BS |
390 | Make sure your ROM base does not include any file-header |
391 | information that is prepended to the kernel. | |
392 | ||
393 | For example, the bootable U-Boot format (created with | |
394 | mkimage) has a 64 byte header (0x40). So while the image | |
395 | you write to flash might start at say 0x20080000, you have | |
396 | to add 0x40 to get the kernel's ROM base as it will come | |
397 | after the header. | |
8cc7117e | 398 | |
f16295e7 | 399 | comment "Clock/PLL Setup" |
1394f032 BW |
400 | |
401 | config CLKIN_HZ | |
2fb6cb41 | 402 | int "Frequency of the crystal on the board in Hz" |
d0cb9b4e | 403 | default "10000000" if BFIN532_IP0X |
1394f032 | 404 | default "11059200" if BFIN533_STAMP |
d0cb9b4e MF |
405 | default "24576000" if PNAV10 |
406 | default "25000000" # most people use this | |
1394f032 | 407 | default "27000000" if BFIN533_EZKIT |
1394f032 | 408 | default "30000000" if BFIN561_EZKIT |
8effc4a6 | 409 | default "24000000" if BFIN527_AD7160EVAL |
1394f032 BW |
410 | help |
411 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
412 | Warning: This value should match the crystal on the board. Otherwise, |
413 | peripherals won't work properly. | |
1394f032 | 414 | |
f16295e7 RG |
415 | config BFIN_KERNEL_CLOCK |
416 | bool "Re-program Clocks while Kernel boots?" | |
417 | default n | |
418 | help | |
419 | This option decides if kernel clocks are re-programed from the | |
420 | bootloader settings. If the clocks are not set, the SDRAM settings | |
421 | are also not changed, and the Bootloader does 100% of the hardware | |
422 | configuration. | |
423 | ||
424 | config PLL_BYPASS | |
e4e9a7ad MF |
425 | bool "Bypass PLL" |
426 | depends on BFIN_KERNEL_CLOCK | |
427 | default n | |
f16295e7 RG |
428 | |
429 | config CLKIN_HALF | |
430 | bool "Half Clock In" | |
431 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
432 | default n | |
433 | help | |
434 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
435 | ||
436 | config VCO_MULT | |
437 | int "VCO Multiplier" | |
438 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
439 | range 1 64 | |
440 | default "22" if BFIN533_EZKIT | |
441 | default "45" if BFIN533_STAMP | |
6924dfb0 | 442 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 443 | default "22" if BFIN533_BLUETECHNIX_CM |
60584344 | 444 | default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 445 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 446 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
8effc4a6 | 447 | default "25" if BFIN527_AD7160EVAL |
f16295e7 RG |
448 | help |
449 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
450 | PLL Frequency = (Crystal Frequency) * (this setting) | |
451 | ||
452 | choice | |
453 | prompt "Core Clock Divider" | |
454 | depends on BFIN_KERNEL_CLOCK | |
455 | default CCLK_DIV_1 | |
456 | help | |
457 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
458 | Core Frequency = (PLL frequency) / (this setting) | |
459 | ||
460 | config CCLK_DIV_1 | |
461 | bool "1" | |
462 | ||
463 | config CCLK_DIV_2 | |
464 | bool "2" | |
465 | ||
466 | config CCLK_DIV_4 | |
467 | bool "4" | |
468 | ||
469 | config CCLK_DIV_8 | |
470 | bool "8" | |
471 | endchoice | |
472 | ||
473 | config SCLK_DIV | |
474 | int "System Clock Divider" | |
475 | depends on BFIN_KERNEL_CLOCK | |
476 | range 1 15 | |
5f004c20 | 477 | default 5 |
f16295e7 RG |
478 | help |
479 | This sets the frequency of the system clock (including SDRAM or DDR). | |
480 | This can be between 1 and 15 | |
481 | System Clock = (PLL frequency) / (this setting) | |
482 | ||
5f004c20 MF |
483 | choice |
484 | prompt "DDR SDRAM Chip Type" | |
485 | depends on BFIN_KERNEL_CLOCK | |
486 | depends on BF54x | |
487 | default MEM_MT46V32M16_5B | |
488 | ||
489 | config MEM_MT46V32M16_6T | |
490 | bool "MT46V32M16_6T" | |
491 | ||
492 | config MEM_MT46V32M16_5B | |
493 | bool "MT46V32M16_5B" | |
494 | endchoice | |
495 | ||
73feb5c0 MH |
496 | choice |
497 | prompt "DDR/SDRAM Timing" | |
498 | depends on BFIN_KERNEL_CLOCK | |
499 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
500 | help | |
501 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
502 | The calculated SDRAM timing parameters may not be 100% | |
503 | accurate - This option is therefore marked experimental. | |
504 | ||
505 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
506 | bool "Calculate Timings (EXPERIMENTAL)" | |
507 | depends on EXPERIMENTAL | |
508 | ||
509 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
510 | bool "Provide accurate Timings based on target SCLK" | |
511 | help | |
512 | Please consult the Blackfin Hardware Reference Manuals as well | |
513 | as the memory device datasheet. | |
514 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
515 | endchoice | |
516 | ||
517 | menu "Memory Init Control" | |
518 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
519 | ||
520 | config MEM_DDRCTL0 | |
521 | depends on BF54x | |
522 | hex "DDRCTL0" | |
523 | default 0x0 | |
524 | ||
525 | config MEM_DDRCTL1 | |
526 | depends on BF54x | |
527 | hex "DDRCTL1" | |
528 | default 0x0 | |
529 | ||
530 | config MEM_DDRCTL2 | |
531 | depends on BF54x | |
532 | hex "DDRCTL2" | |
533 | default 0x0 | |
534 | ||
535 | config MEM_EBIU_DDRQUE | |
536 | depends on BF54x | |
537 | hex "DDRQUE" | |
538 | default 0x0 | |
539 | ||
540 | config MEM_SDRRC | |
541 | depends on !BF54x | |
542 | hex "SDRRC" | |
543 | default 0x0 | |
544 | ||
545 | config MEM_SDGCTL | |
546 | depends on !BF54x | |
547 | hex "SDGCTL" | |
548 | default 0x0 | |
549 | endmenu | |
550 | ||
f16295e7 RG |
551 | # |
552 | # Max & Min Speeds for various Chips | |
553 | # | |
554 | config MAX_VCO_HZ | |
555 | int | |
2f6f4bcd BW |
556 | default 400000000 if BF512 |
557 | default 400000000 if BF514 | |
558 | default 400000000 if BF516 | |
559 | default 400000000 if BF518 | |
7b06263b MF |
560 | default 400000000 if BF522 |
561 | default 600000000 if BF523 | |
1545a111 | 562 | default 400000000 if BF524 |
f16295e7 | 563 | default 600000000 if BF525 |
1545a111 | 564 | default 400000000 if BF526 |
f16295e7 RG |
565 | default 600000000 if BF527 |
566 | default 400000000 if BF531 | |
567 | default 400000000 if BF532 | |
568 | default 750000000 if BF533 | |
569 | default 500000000 if BF534 | |
570 | default 400000000 if BF536 | |
571 | default 600000000 if BF537 | |
f72eecb9 RG |
572 | default 533333333 if BF538 |
573 | default 533333333 if BF539 | |
f16295e7 | 574 | default 600000000 if BF542 |
f72eecb9 | 575 | default 533333333 if BF544 |
1545a111 MF |
576 | default 600000000 if BF547 |
577 | default 600000000 if BF548 | |
f72eecb9 | 578 | default 533333333 if BF549 |
f16295e7 RG |
579 | default 600000000 if BF561 |
580 | ||
581 | config MIN_VCO_HZ | |
582 | int | |
583 | default 50000000 | |
584 | ||
585 | config MAX_SCLK_HZ | |
586 | int | |
f72eecb9 | 587 | default 133333333 |
f16295e7 RG |
588 | |
589 | config MIN_SCLK_HZ | |
590 | int | |
591 | default 27000000 | |
592 | ||
593 | comment "Kernel Timer/Scheduler" | |
594 | ||
595 | source kernel/Kconfig.hz | |
596 | ||
8b5f79f9 VM |
597 | config GENERIC_CLOCKEVENTS |
598 | bool "Generic clock events" | |
8b5f79f9 VM |
599 | default y |
600 | ||
0d152c27 | 601 | menu "Clock event device" |
1fa9be72 | 602 | depends on GENERIC_CLOCKEVENTS |
1fa9be72 | 603 | config TICKSOURCE_GPTMR0 |
0d152c27 YL |
604 | bool "GPTimer0" |
605 | depends on !SMP | |
1fa9be72 | 606 | select BFIN_GPTIMERS |
1fa9be72 GY |
607 | |
608 | config TICKSOURCE_CORETMR | |
0d152c27 YL |
609 | bool "Core timer" |
610 | default y | |
611 | endmenu | |
1fa9be72 | 612 | |
0d152c27 | 613 | menu "Clock souce" |
8b5f79f9 | 614 | depends on GENERIC_CLOCKEVENTS |
0d152c27 YL |
615 | config CYCLES_CLOCKSOURCE |
616 | bool "CYCLES" | |
617 | default y | |
8b5f79f9 | 618 | depends on !BFIN_SCRATCH_REG_CYCLES |
1fa9be72 | 619 | depends on !SMP |
8b5f79f9 VM |
620 | help |
621 | If you say Y here, you will enable support for using the 'cycles' | |
622 | registers as a clock source. Doing so means you will be unable to | |
623 | safely write to the 'cycles' register during runtime. You will | |
624 | still be able to read it (such as for performance monitoring), but | |
625 | writing the registers will most likely crash the kernel. | |
626 | ||
1fa9be72 | 627 | config GPTMR0_CLOCKSOURCE |
0d152c27 | 628 | bool "GPTimer0" |
3aca47c0 | 629 | select BFIN_GPTIMERS |
1fa9be72 | 630 | depends on !TICKSOURCE_GPTMR0 |
0d152c27 | 631 | endmenu |
1fa9be72 | 632 | |
10f03f1a | 633 | config ARCH_USES_GETTIMEOFFSET |
634 | depends on !GENERIC_CLOCKEVENTS | |
635 | def_bool y | |
636 | ||
8b5f79f9 VM |
637 | source kernel/time/Kconfig |
638 | ||
5f004c20 | 639 | comment "Misc" |
971d5bc4 | 640 | |
f0b5d12f MF |
641 | choice |
642 | prompt "Blackfin Exception Scratch Register" | |
643 | default BFIN_SCRATCH_REG_RETN | |
644 | help | |
645 | Select the resource to reserve for the Exception handler: | |
646 | - RETN: Non-Maskable Interrupt (NMI) | |
647 | - RETE: Exception Return (JTAG/ICE) | |
648 | - CYCLES: Performance counter | |
649 | ||
650 | If you are unsure, please select "RETN". | |
651 | ||
652 | config BFIN_SCRATCH_REG_RETN | |
653 | bool "RETN" | |
654 | help | |
655 | Use the RETN register in the Blackfin exception handler | |
656 | as a stack scratch register. This means you cannot | |
657 | safely use NMI on the Blackfin while running Linux, but | |
658 | you can debug the system with a JTAG ICE and use the | |
659 | CYCLES performance registers. | |
660 | ||
661 | If you are unsure, please select "RETN". | |
662 | ||
663 | config BFIN_SCRATCH_REG_RETE | |
664 | bool "RETE" | |
665 | help | |
666 | Use the RETE register in the Blackfin exception handler | |
667 | as a stack scratch register. This means you cannot | |
668 | safely use a JTAG ICE while debugging a Blackfin board, | |
669 | but you can safely use the CYCLES performance registers | |
670 | and the NMI. | |
671 | ||
672 | If you are unsure, please select "RETN". | |
673 | ||
674 | config BFIN_SCRATCH_REG_CYCLES | |
675 | bool "CYCLES" | |
676 | help | |
677 | Use the CYCLES register in the Blackfin exception handler | |
678 | as a stack scratch register. This means you cannot | |
679 | safely use the CYCLES performance registers on a Blackfin | |
680 | board at anytime, but you can debug the system with a JTAG | |
681 | ICE and use the NMI. | |
682 | ||
683 | If you are unsure, please select "RETN". | |
684 | ||
685 | endchoice | |
686 | ||
1394f032 BW |
687 | endmenu |
688 | ||
689 | ||
690 | menu "Blackfin Kernel Optimizations" | |
691 | ||
1394f032 BW |
692 | comment "Memory Optimizations" |
693 | ||
694 | config I_ENTRY_L1 | |
695 | bool "Locate interrupt entry code in L1 Memory" | |
696 | default y | |
820b127d | 697 | depends on !SMP |
1394f032 | 698 | help |
01dd2fbf ML |
699 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
700 | into L1 instruction memory. (less latency) | |
1394f032 BW |
701 | |
702 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 703 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 | 704 | default y |
820b127d | 705 | depends on !SMP |
1394f032 | 706 | help |
01dd2fbf | 707 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 708 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 709 | (less latency) |
1394f032 BW |
710 | |
711 | config DO_IRQ_L1 | |
712 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
713 | default y | |
820b127d | 714 | depends on !SMP |
1394f032 | 715 | help |
01dd2fbf ML |
716 | If enabled, the frequently called do_irq dispatcher function is linked |
717 | into L1 instruction memory. (less latency) | |
1394f032 BW |
718 | |
719 | config CORE_TIMER_IRQ_L1 | |
720 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
721 | default y | |
820b127d | 722 | depends on !SMP |
1394f032 | 723 | help |
01dd2fbf ML |
724 | If enabled, the frequently called timer_interrupt() function is linked |
725 | into L1 instruction memory. (less latency) | |
1394f032 BW |
726 | |
727 | config IDLE_L1 | |
728 | bool "Locate frequently idle function in L1 Memory" | |
729 | default y | |
820b127d | 730 | depends on !SMP |
1394f032 | 731 | help |
01dd2fbf ML |
732 | If enabled, the frequently called idle function is linked |
733 | into L1 instruction memory. (less latency) | |
1394f032 BW |
734 | |
735 | config SCHEDULE_L1 | |
736 | bool "Locate kernel schedule function in L1 Memory" | |
737 | default y | |
820b127d | 738 | depends on !SMP |
1394f032 | 739 | help |
01dd2fbf ML |
740 | If enabled, the frequently called kernel schedule is linked |
741 | into L1 instruction memory. (less latency) | |
1394f032 BW |
742 | |
743 | config ARITHMETIC_OPS_L1 | |
744 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
745 | default y | |
820b127d | 746 | depends on !SMP |
1394f032 | 747 | help |
01dd2fbf ML |
748 | If enabled, arithmetic functions are linked |
749 | into L1 instruction memory. (less latency) | |
1394f032 BW |
750 | |
751 | config ACCESS_OK_L1 | |
752 | bool "Locate access_ok function in L1 Memory" | |
753 | default y | |
820b127d | 754 | depends on !SMP |
1394f032 | 755 | help |
01dd2fbf ML |
756 | If enabled, the access_ok function is linked |
757 | into L1 instruction memory. (less latency) | |
1394f032 BW |
758 | |
759 | config MEMSET_L1 | |
760 | bool "Locate memset function in L1 Memory" | |
761 | default y | |
820b127d | 762 | depends on !SMP |
1394f032 | 763 | help |
01dd2fbf ML |
764 | If enabled, the memset function is linked |
765 | into L1 instruction memory. (less latency) | |
1394f032 BW |
766 | |
767 | config MEMCPY_L1 | |
768 | bool "Locate memcpy function in L1 Memory" | |
769 | default y | |
820b127d | 770 | depends on !SMP |
1394f032 | 771 | help |
01dd2fbf ML |
772 | If enabled, the memcpy function is linked |
773 | into L1 instruction memory. (less latency) | |
1394f032 | 774 | |
479ba603 RG |
775 | config STRCMP_L1 |
776 | bool "locate strcmp function in L1 Memory" | |
777 | default y | |
820b127d | 778 | depends on !SMP |
479ba603 RG |
779 | help |
780 | If enabled, the strcmp function is linked | |
781 | into L1 instruction memory (less latency). | |
782 | ||
783 | config STRNCMP_L1 | |
784 | bool "locate strncmp function in L1 Memory" | |
785 | default y | |
820b127d | 786 | depends on !SMP |
479ba603 RG |
787 | help |
788 | If enabled, the strncmp function is linked | |
789 | into L1 instruction memory (less latency). | |
790 | ||
791 | config STRCPY_L1 | |
792 | bool "locate strcpy function in L1 Memory" | |
793 | default y | |
820b127d | 794 | depends on !SMP |
479ba603 RG |
795 | help |
796 | If enabled, the strcpy function is linked | |
797 | into L1 instruction memory (less latency). | |
798 | ||
799 | config STRNCPY_L1 | |
800 | bool "locate strncpy function in L1 Memory" | |
801 | default y | |
820b127d | 802 | depends on !SMP |
479ba603 RG |
803 | help |
804 | If enabled, the strncpy function is linked | |
805 | into L1 instruction memory (less latency). | |
806 | ||
1394f032 BW |
807 | config SYS_BFIN_SPINLOCK_L1 |
808 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
809 | default y | |
820b127d | 810 | depends on !SMP |
1394f032 | 811 | help |
01dd2fbf ML |
812 | If enabled, sys_bfin_spinlock function is linked |
813 | into L1 instruction memory. (less latency) | |
1394f032 BW |
814 | |
815 | config IP_CHECKSUM_L1 | |
816 | bool "Locate IP Checksum function in L1 Memory" | |
817 | default n | |
820b127d | 818 | depends on !SMP |
1394f032 | 819 | help |
01dd2fbf ML |
820 | If enabled, the IP Checksum function is linked |
821 | into L1 instruction memory. (less latency) | |
1394f032 BW |
822 | |
823 | config CACHELINE_ALIGNED_L1 | |
824 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
825 | default y if !BF54x |
826 | default n if BF54x | |
95fc2d8f | 827 | depends on !SMP && !BF531 && !CRC32 |
1394f032 | 828 | help |
692105b8 | 829 | If enabled, cacheline_aligned data is linked |
01dd2fbf | 830 | into L1 data memory. (less latency) |
1394f032 BW |
831 | |
832 | config SYSCALL_TAB_L1 | |
833 | bool "Locate Syscall Table L1 Data Memory" | |
834 | default n | |
820b127d | 835 | depends on !SMP && !BF531 |
1394f032 | 836 | help |
01dd2fbf ML |
837 | If enabled, the Syscall LUT is linked |
838 | into L1 data memory. (less latency) | |
1394f032 BW |
839 | |
840 | config CPLB_SWITCH_TAB_L1 | |
841 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
842 | default n | |
820b127d | 843 | depends on !SMP && !BF531 |
1394f032 | 844 | help |
01dd2fbf ML |
845 | If enabled, the CPLB Switch Tables are linked |
846 | into L1 data memory. (less latency) | |
1394f032 | 847 | |
820b127d MF |
848 | config ICACHE_FLUSH_L1 |
849 | bool "Locate icache flush funcs in L1 Inst Memory" | |
74181295 MF |
850 | default y |
851 | help | |
820b127d | 852 | If enabled, the Blackfin icache flushing functions are linked |
74181295 MF |
853 | into L1 instruction memory. |
854 | ||
855 | Note that this might be required to address anomalies, but | |
856 | these functions are pretty small, so it shouldn't be too bad. | |
857 | If you are using a processor affected by an anomaly, the build | |
858 | system will double check for you and prevent it. | |
859 | ||
820b127d MF |
860 | config DCACHE_FLUSH_L1 |
861 | bool "Locate dcache flush funcs in L1 Inst Memory" | |
862 | default y | |
863 | depends on !SMP | |
864 | help | |
865 | If enabled, the Blackfin dcache flushing functions are linked | |
866 | into L1 instruction memory. | |
867 | ||
ca87b7ad GY |
868 | config APP_STACK_L1 |
869 | bool "Support locating application stack in L1 Scratch Memory" | |
870 | default y | |
820b127d | 871 | depends on !SMP |
ca87b7ad GY |
872 | help |
873 | If enabled the application stack can be located in L1 | |
874 | scratch memory (less latency). | |
875 | ||
876 | Currently only works with FLAT binaries. | |
877 | ||
6ad2b84c MF |
878 | config EXCEPTION_L1_SCRATCH |
879 | bool "Locate exception stack in L1 Scratch Memory" | |
880 | default n | |
820b127d | 881 | depends on !SMP && !APP_STACK_L1 |
6ad2b84c MF |
882 | help |
883 | Whenever an exception occurs, use the L1 Scratch memory for | |
884 | stack storage. You cannot place the stacks of FLAT binaries | |
885 | in L1 when using this option. | |
886 | ||
887 | If you don't use L1 Scratch, then you should say Y here. | |
888 | ||
251383c7 RG |
889 | comment "Speed Optimizations" |
890 | config BFIN_INS_LOWOVERHEAD | |
891 | bool "ins[bwl] low overhead, higher interrupt latency" | |
892 | default y | |
820b127d | 893 | depends on !SMP |
251383c7 RG |
894 | help |
895 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
896 | they can be interrupted at any time (even after they have been issued | |
897 | on to the external bus), and re-issued after the interrupt occurs. | |
898 | For memory - this is not a big deal, since memory does not change if | |
899 | it sees a read. | |
900 | ||
901 | If a FIFO is sitting on the end of the read, it will see two reads, | |
902 | when the core only sees one since the FIFO receives both the read | |
903 | which is cancelled (and not delivered to the core) and the one which | |
904 | is re-issued (which is delivered to the core). | |
905 | ||
906 | To solve this, interrupts are turned off before reads occur to | |
907 | I/O space. This option controls which the overhead/latency of | |
908 | controlling interrupts during this time | |
909 | "n" turns interrupts off every read | |
910 | (higher overhead, but lower interrupt latency) | |
911 | "y" turns interrupts off every loop | |
912 | (low overhead, but longer interrupt latency) | |
913 | ||
914 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
915 | interrupt latency issues, it is safe and OK to turn this off. | |
916 | ||
1394f032 BW |
917 | endmenu |
918 | ||
1394f032 BW |
919 | choice |
920 | prompt "Kernel executes from" | |
921 | help | |
922 | Choose the memory type that the kernel will be running in. | |
923 | ||
924 | config RAMKERNEL | |
925 | bool "RAM" | |
926 | help | |
927 | The kernel will be resident in RAM when running. | |
928 | ||
929 | config ROMKERNEL | |
930 | bool "ROM" | |
931 | help | |
932 | The kernel will be resident in FLASH/ROM when running. | |
933 | ||
934 | endchoice | |
935 | ||
56b4f07a MF |
936 | # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both |
937 | config XIP_KERNEL | |
938 | bool | |
939 | default y | |
940 | depends on ROMKERNEL | |
941 | ||
1394f032 BW |
942 | source "mm/Kconfig" |
943 | ||
780431e3 MF |
944 | config BFIN_GPTIMERS |
945 | tristate "Enable Blackfin General Purpose Timers API" | |
946 | default n | |
947 | help | |
948 | Enable support for the General Purpose Timers API. If you | |
949 | are unsure, say N. | |
950 | ||
951 | To compile this driver as a module, choose M here: the module | |
4737f097 | 952 | will be called gptimers. |
780431e3 | 953 | |
006669ec MF |
954 | config HAVE_PWM |
955 | tristate "Enable PWM API support" | |
956 | depends on BFIN_GPTIMERS | |
957 | help | |
958 | Enable support for the Pulse Width Modulation framework (as | |
959 | found in linux/pwm.h). | |
960 | ||
961 | To compile this driver as a module, choose M here: the module | |
962 | will be called pwm. | |
963 | ||
1394f032 | 964 | choice |
d292b000 | 965 | prompt "Uncached DMA region" |
1394f032 | 966 | default DMA_UNCACHED_1M |
86ad7932 CC |
967 | config DMA_UNCACHED_4M |
968 | bool "Enable 4M DMA region" | |
1394f032 BW |
969 | config DMA_UNCACHED_2M |
970 | bool "Enable 2M DMA region" | |
971 | config DMA_UNCACHED_1M | |
972 | bool "Enable 1M DMA region" | |
c45c0659 BS |
973 | config DMA_UNCACHED_512K |
974 | bool "Enable 512K DMA region" | |
975 | config DMA_UNCACHED_256K | |
976 | bool "Enable 256K DMA region" | |
977 | config DMA_UNCACHED_128K | |
978 | bool "Enable 128K DMA region" | |
1394f032 BW |
979 | config DMA_UNCACHED_NONE |
980 | bool "Disable DMA region" | |
981 | endchoice | |
982 | ||
983 | ||
984 | comment "Cache Support" | |
41ba653f | 985 | |
3bebca2d | 986 | config BFIN_ICACHE |
1394f032 | 987 | bool "Enable ICACHE" |
41ba653f | 988 | default y |
41ba653f JZ |
989 | config BFIN_EXTMEM_ICACHEABLE |
990 | bool "Enable ICACHE for external memory" | |
991 | depends on BFIN_ICACHE | |
992 | default y | |
993 | config BFIN_L2_ICACHEABLE | |
994 | bool "Enable ICACHE for L2 SRAM" | |
995 | depends on BFIN_ICACHE | |
996 | depends on BF54x || BF561 | |
997 | default n | |
998 | ||
3bebca2d | 999 | config BFIN_DCACHE |
1394f032 | 1000 | bool "Enable DCACHE" |
41ba653f | 1001 | default y |
3bebca2d | 1002 | config BFIN_DCACHE_BANKA |
1394f032 | 1003 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 1004 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 1005 | default n |
41ba653f JZ |
1006 | config BFIN_EXTMEM_DCACHEABLE |
1007 | bool "Enable DCACHE for external memory" | |
3bebca2d | 1008 | depends on BFIN_DCACHE |
41ba653f JZ |
1009 | default y |
1010 | choice | |
1011 | prompt "External memory DCACHE policy" | |
1012 | depends on BFIN_EXTMEM_DCACHEABLE | |
1013 | default BFIN_EXTMEM_WRITEBACK if !SMP | |
1014 | default BFIN_EXTMEM_WRITETHROUGH if SMP | |
1015 | config BFIN_EXTMEM_WRITEBACK | |
1394f032 | 1016 | bool "Write back" |
46fa5eec | 1017 | depends on !SMP |
1394f032 BW |
1018 | help |
1019 | Write Back Policy: | |
1020 | Cached data will be written back to SDRAM only when needed. | |
1021 | This can give a nice increase in performance, but beware of | |
1022 | broken drivers that do not properly invalidate/flush their | |
1023 | cache. | |
1024 | ||
1025 | Write Through Policy: | |
1026 | Cached data will always be written back to SDRAM when the | |
1027 | cache is updated. This is a completely safe setting, but | |
1028 | performance is worse than Write Back. | |
1029 | ||
1030 | If you are unsure of the options and you want to be safe, | |
1031 | then go with Write Through. | |
1032 | ||
41ba653f | 1033 | config BFIN_EXTMEM_WRITETHROUGH |
1394f032 BW |
1034 | bool "Write through" |
1035 | help | |
1036 | Write Back Policy: | |
1037 | Cached data will be written back to SDRAM only when needed. | |
1038 | This can give a nice increase in performance, but beware of | |
1039 | broken drivers that do not properly invalidate/flush their | |
1040 | cache. | |
1041 | ||
1042 | Write Through Policy: | |
1043 | Cached data will always be written back to SDRAM when the | |
1044 | cache is updated. This is a completely safe setting, but | |
1045 | performance is worse than Write Back. | |
1046 | ||
1047 | If you are unsure of the options and you want to be safe, | |
1048 | then go with Write Through. | |
1049 | ||
1050 | endchoice | |
1051 | ||
41ba653f JZ |
1052 | config BFIN_L2_DCACHEABLE |
1053 | bool "Enable DCACHE for L2 SRAM" | |
1054 | depends on BFIN_DCACHE | |
9c954f89 | 1055 | depends on (BF54x || BF561) && !SMP |
41ba653f | 1056 | default n |
5ba76675 | 1057 | choice |
41ba653f JZ |
1058 | prompt "L2 SRAM DCACHE policy" |
1059 | depends on BFIN_L2_DCACHEABLE | |
1060 | default BFIN_L2_WRITEBACK | |
1061 | config BFIN_L2_WRITEBACK | |
5ba76675 | 1062 | bool "Write back" |
5ba76675 | 1063 | |
41ba653f | 1064 | config BFIN_L2_WRITETHROUGH |
5ba76675 | 1065 | bool "Write through" |
5ba76675 | 1066 | endchoice |
f099f39a | 1067 | |
41ba653f JZ |
1068 | |
1069 | comment "Memory Protection Unit" | |
b97b8a99 BS |
1070 | config MPU |
1071 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
1072 | default n | |
1073 | help | |
1074 | Use the processor's MPU to protect applications from accessing | |
1075 | memory they do not own. This comes at a performance penalty | |
1076 | and is recommended only for debugging. | |
1077 | ||
692105b8 | 1078 | comment "Asynchronous Memory Configuration" |
1394f032 | 1079 | |
ddf416b2 | 1080 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
1081 | config C_AMCKEN |
1082 | bool "Enable CLKOUT" | |
1083 | default y | |
1084 | ||
1085 | config C_CDPRIO | |
1086 | bool "DMA has priority over core for ext. accesses" | |
1087 | default n | |
1088 | ||
1089 | config C_B0PEN | |
1090 | depends on BF561 | |
1091 | bool "Bank 0 16 bit packing enable" | |
1092 | default y | |
1093 | ||
1094 | config C_B1PEN | |
1095 | depends on BF561 | |
1096 | bool "Bank 1 16 bit packing enable" | |
1097 | default y | |
1098 | ||
1099 | config C_B2PEN | |
1100 | depends on BF561 | |
1101 | bool "Bank 2 16 bit packing enable" | |
1102 | default y | |
1103 | ||
1104 | config C_B3PEN | |
1105 | depends on BF561 | |
1106 | bool "Bank 3 16 bit packing enable" | |
1107 | default n | |
1108 | ||
1109 | choice | |
692105b8 | 1110 | prompt "Enable Asynchronous Memory Banks" |
1394f032 BW |
1111 | default C_AMBEN_ALL |
1112 | ||
1113 | config C_AMBEN | |
1114 | bool "Disable All Banks" | |
1115 | ||
1116 | config C_AMBEN_B0 | |
1117 | bool "Enable Bank 0" | |
1118 | ||
1119 | config C_AMBEN_B0_B1 | |
1120 | bool "Enable Bank 0 & 1" | |
1121 | ||
1122 | config C_AMBEN_B0_B1_B2 | |
1123 | bool "Enable Bank 0 & 1 & 2" | |
1124 | ||
1125 | config C_AMBEN_ALL | |
1126 | bool "Enable All Banks" | |
1127 | endchoice | |
1128 | endmenu | |
1129 | ||
1130 | menu "EBIU_AMBCTL Control" | |
1131 | config BANK_0 | |
c8342f87 | 1132 | hex "Bank 0 (AMBCTL0.L)" |
1394f032 | 1133 | default 0x7BB0 |
c8342f87 MF |
1134 | help |
1135 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are | |
1136 | used to control the Asynchronous Memory Bank 0 settings. | |
1394f032 BW |
1137 | |
1138 | config BANK_1 | |
c8342f87 | 1139 | hex "Bank 1 (AMBCTL0.H)" |
1394f032 | 1140 | default 0x7BB0 |
197fba56 | 1141 | default 0x5558 if BF54x |
c8342f87 MF |
1142 | help |
1143 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are | |
1144 | used to control the Asynchronous Memory Bank 1 settings. | |
1394f032 BW |
1145 | |
1146 | config BANK_2 | |
c8342f87 | 1147 | hex "Bank 2 (AMBCTL1.L)" |
1394f032 | 1148 | default 0x7BB0 |
c8342f87 MF |
1149 | help |
1150 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are | |
1151 | used to control the Asynchronous Memory Bank 2 settings. | |
1394f032 BW |
1152 | |
1153 | config BANK_3 | |
c8342f87 | 1154 | hex "Bank 3 (AMBCTL1.H)" |
1394f032 | 1155 | default 0x99B3 |
c8342f87 MF |
1156 | help |
1157 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are | |
1158 | used to control the Asynchronous Memory Bank 3 settings. | |
1159 | ||
1394f032 BW |
1160 | endmenu |
1161 | ||
e40540b3 SZ |
1162 | config EBIU_MBSCTLVAL |
1163 | hex "EBIU Bank Select Control Register" | |
1164 | depends on BF54x | |
1165 | default 0 | |
1166 | ||
1167 | config EBIU_MODEVAL | |
1168 | hex "Flash Memory Mode Control Register" | |
1169 | depends on BF54x | |
1170 | default 1 | |
1171 | ||
1172 | config EBIU_FCTLVAL | |
1173 | hex "Flash Memory Bank Control Register" | |
1174 | depends on BF54x | |
1175 | default 6 | |
1394f032 BW |
1176 | endmenu |
1177 | ||
1178 | ############################################################################# | |
1179 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1180 | ||
1181 | config PCI | |
1182 | bool "PCI support" | |
a95ca3b2 | 1183 | depends on BROKEN |
1394f032 BW |
1184 | help |
1185 | Support for PCI bus. | |
1186 | ||
1187 | source "drivers/pci/Kconfig" | |
1188 | ||
1394f032 BW |
1189 | source "drivers/pcmcia/Kconfig" |
1190 | ||
1191 | source "drivers/pci/hotplug/Kconfig" | |
1192 | ||
1193 | endmenu | |
1194 | ||
1195 | menu "Executable file formats" | |
1196 | ||
1197 | source "fs/Kconfig.binfmt" | |
1198 | ||
1199 | endmenu | |
1200 | ||
1201 | menu "Power management options" | |
ad46163a | 1202 | |
1394f032 BW |
1203 | source "kernel/power/Kconfig" |
1204 | ||
f4cb5700 JB |
1205 | config ARCH_SUSPEND_POSSIBLE |
1206 | def_bool y | |
f4cb5700 | 1207 | |
1394f032 | 1208 | choice |
1efc80b5 | 1209 | prompt "Standby Power Saving Mode" |
1394f032 | 1210 | depends on PM |
cfefe3c6 MH |
1211 | default PM_BFIN_SLEEP_DEEPER |
1212 | config PM_BFIN_SLEEP_DEEPER | |
1213 | bool "Sleep Deeper" | |
1214 | help | |
1215 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1216 | power dissipation by disabling the clock to the processor core (CCLK). | |
1217 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1218 | to 0.85 V to provide the greatest power savings, while preserving the | |
1219 | processor state. | |
1220 | The PLL and system clock (SCLK) continue to operate at a very low | |
1221 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1222 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1223 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1224 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1225 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1226 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1227 | ||
1efc80b5 MH |
1228 | If unsure, select "Sleep Deeper". |
1229 | ||
cfefe3c6 MH |
1230 | config PM_BFIN_SLEEP |
1231 | bool "Sleep" | |
1232 | help | |
1233 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1234 | dissipation by disabling the clock to the processor core (CCLK). | |
1235 | The PLL and system clock (SCLK), however, continue to operate in | |
1236 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1237 | up the processor. When in the sleep mode, system DMA access to L1 |
1238 | memory is not supported. | |
1239 | ||
1240 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1241 | endchoice |
1394f032 | 1242 | |
1efc80b5 MH |
1243 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1244 | depends on PM | |
1245 | ||
1efc80b5 MH |
1246 | config PM_BFIN_WAKE_PH6 |
1247 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1248 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1249 | default n |
1250 | help | |
1251 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1252 | ||
1efc80b5 MH |
1253 | config PM_BFIN_WAKE_GP |
1254 | bool "Allow Wake-Up from GPIOs" | |
1255 | depends on PM && BF54x | |
1256 | default n | |
1257 | help | |
1258 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
19986289 MH |
1259 | (all processors, except ADSP-BF549). This option sets |
1260 | the general-purpose wake-up enable (GPWE) control bit to enable | |
1261 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | |
1262 | On ADSP-BF549 this option enables the the same functionality on the | |
1263 | /MRXON pin also PH7. | |
1264 | ||
1394f032 BW |
1265 | endmenu |
1266 | ||
1394f032 BW |
1267 | menu "CPU Frequency scaling" |
1268 | ||
1269 | source "drivers/cpufreq/Kconfig" | |
1270 | ||
5ad2ca5f MH |
1271 | config BFIN_CPU_FREQ |
1272 | bool | |
1273 | depends on CPU_FREQ | |
1274 | select CPU_FREQ_TABLE | |
1275 | default y | |
1276 | ||
14b03204 MH |
1277 | config CPU_VOLTAGE |
1278 | bool "CPU Voltage scaling" | |
73feb5c0 | 1279 | depends on EXPERIMENTAL |
14b03204 MH |
1280 | depends on CPU_FREQ |
1281 | default n | |
1282 | help | |
1283 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1284 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1285 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1286 | the PLL may unlock. |
1287 | ||
1394f032 BW |
1288 | endmenu |
1289 | ||
1394f032 BW |
1290 | source "net/Kconfig" |
1291 | ||
1292 | source "drivers/Kconfig" | |
1293 | ||
872d024b MF |
1294 | source "drivers/firmware/Kconfig" |
1295 | ||
1394f032 BW |
1296 | source "fs/Kconfig" |
1297 | ||
74ce8322 | 1298 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1299 | |
1300 | source "security/Kconfig" | |
1301 | ||
1302 | source "crypto/Kconfig" | |
1303 | ||
1304 | source "lib/Kconfig" |