[deliverable/linux.git] / arch / blackfin / Kconfig

config SYMBOL_PREFIX
	string
	default "_"

config MMU
	def_bool n

config FPU
	def_bool n

config RWSEM_GENERIC_SPINLOCK
	def_bool y

config RWSEM_XCHGADD_ALGORITHM
	def_bool n

config BLACKFIN
	def_bool y
	select HAVE_ARCH_KGDB
	select HAVE_ARCH_TRACEHOOK
	select HAVE_DYNAMIC_FTRACE
	select HAVE_FTRACE_MCOUNT_RECORD
	select HAVE_FUNCTION_GRAPH_TRACER
	select HAVE_FUNCTION_TRACER
	select HAVE_FUNCTION_TRACE_MCOUNT_TEST
	select HAVE_IDE
	select HAVE_IRQ_WORK
	select HAVE_KERNEL_GZIP if RAMKERNEL
	select HAVE_KERNEL_BZIP2 if RAMKERNEL
	select HAVE_KERNEL_LZMA if RAMKERNEL
	select HAVE_KERNEL_LZO if RAMKERNEL
	select HAVE_OPROFILE
	select HAVE_PERF_EVENTS
	select ARCH_HAVE_CUSTOM_GPIO_H
	select ARCH_WANT_OPTIONAL_GPIOLIB
	select HAVE_UID16
	select ARCH_WANT_IPC_PARSE_VERSION
	select HAVE_GENERIC_HARDIRQS
	select GENERIC_ATOMIC64
	select GENERIC_IRQ_PROBE
	select IRQ_PER_CPU if SMP
	select USE_GENERIC_SMP_HELPERS if SMP
	select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
	select GENERIC_SMP_IDLE_THREAD
	select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
	select HAVE_MOD_ARCH_SPECIFIC
	select MODULES_USE_ELF_RELA

config GENERIC_CSUM
	def_bool y

config GENERIC_BUG
	def_bool y
	depends on BUG

config ZONE_DMA
	def_bool y

config GENERIC_GPIO
	def_bool y

config FORCE_MAX_ZONEORDER
	int
	default "14"

config GENERIC_CALIBRATE_DELAY
	def_bool y

config LOCKDEP_SUPPORT
	def_bool y

config STACKTRACE_SUPPORT
	def_bool y

config TRACE_IRQFLAGS_SUPPORT
	def_bool y

source "init/Kconfig"

source "kernel/Kconfig.preempt"

source "kernel/Kconfig.freezer"

menu "Blackfin Processor Options"

comment "Processor and Board Settings"

choice
	prompt "CPU"
	default BF533

config BF512
	bool "BF512"
	help
	  BF512 Processor Support.

config BF514
	bool "BF514"
	help
	  BF514 Processor Support.

config BF516
	bool "BF516"
	help
	  BF516 Processor Support.

config BF518
	bool "BF518"
	help
	  BF518 Processor Support.

config BF522
	bool "BF522"
	help
	  BF522 Processor Support.

config BF523
	bool "BF523"
	help
	  BF523 Processor Support.

config BF524
	bool "BF524"
	help
	  BF524 Processor Support.

config BF525
	bool "BF525"
	help
	  BF525 Processor Support.

config BF526
	bool "BF526"
	help
	  BF526 Processor Support.

config BF527
	bool "BF527"
	help
	  BF527 Processor Support.

config BF531
	bool "BF531"
	help
	  BF531 Processor Support.

config BF532
	bool "BF532"
	help
	  BF532 Processor Support.

config BF533
	bool "BF533"
	help
	  BF533 Processor Support.

config BF534
	bool "BF534"
	help
	  BF534 Processor Support.

config BF536
	bool "BF536"
	help
	  BF536 Processor Support.

config BF537
	bool "BF537"
	help
	  BF537 Processor Support.

config BF538
	bool "BF538"
	help
	  BF538 Processor Support.

config BF539
	bool "BF539"
	help
	  BF539 Processor Support.

config BF542_std
	bool "BF542"
	help
	  BF542 Processor Support.

config BF542M
	bool "BF542m"
	help
	  BF542 Processor Support.

config BF544_std
	bool "BF544"
	help
	  BF544 Processor Support.

config BF544M
	bool "BF544m"
	help
	  BF544 Processor Support.

config BF547_std
	bool "BF547"
	help
	  BF547 Processor Support.

config BF547M
	bool "BF547m"
	help
	  BF547 Processor Support.

config BF548_std
	bool "BF548"
	help
	  BF548 Processor Support.

config BF548M
	bool "BF548m"
	help
	  BF548 Processor Support.

config BF549_std
	bool "BF549"
	help
	  BF549 Processor Support.

config BF549M
	bool "BF549m"
	help
	  BF549 Processor Support.

config BF561
	bool "BF561"
	help
	  BF561 Processor Support.

config BF609
	bool "BF609"
	select CLKDEV_LOOKUP
	help
	  BF609 Processor Support.

endchoice

config SMP
	depends on BF561
	select TICKSOURCE_CORETMR
	bool "Symmetric multi-processing support"
	---help---
	  This enables support for systems with more than one CPU,
	  like the dual core BF561. If you have a system with only one
	  CPU, say N. If you have a system with more than one CPU, say Y.

	  If you don't know what to do here, say N.

config NR_CPUS
	int
	depends on SMP
	default 2 if BF561

config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs"
	depends on SMP && HOTPLUG
	default y

config BF_REV_MIN
	int
	default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
	default 2 if (BF537 || BF536 || BF534)
	default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
	default 4 if (BF538 || BF539)

config BF_REV_MAX
	int
	default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
	default 3 if (BF537 || BF536 || BF534 || BF54xM)
	default 5 if (BF561 || BF538 || BF539)
	default 6 if (BF533 || BF532 || BF531)

choice
	prompt "Silicon Rev"
	default BF_REV_0_0 if (BF51x || BF52x || BF60x)
	default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
	default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)

config BF_REV_0_0
	bool "0.0"
	depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)

config BF_REV_0_1
	bool "0.1"
	depends on (BF51x || BF52x || (BF54x && !BF54xM))

config BF_REV_0_2
	bool "0.2"
	depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))

config BF_REV_0_3
	bool "0.3"
	depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)

config BF_REV_0_4
	bool "0.4"
	depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)

config BF_REV_0_5
	bool "0.5"
	depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)

config BF_REV_0_6
	bool "0.6"
	depends on (BF533 || BF532 || BF531)

config BF_REV_ANY
	bool "any"

config BF_REV_NONE
	bool "none"

endchoice

config BF53x
	bool
	depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
	default y

config MEM_MT48LC64M4A2FB_7E
	bool
	depends on (BFIN533_STAMP)
	default y

config MEM_MT48LC16M16A2TG_75
	bool
	depends on (BFIN533_EZKIT || BFIN561_EZKIT \
		|| BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
		|| BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
		|| BFIN527_BLUETECHNIX_CM)
	default y

config MEM_MT48LC32M8A2_75
	bool
	depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
	default y

config MEM_MT48LC8M32B2B5_7
	bool
	depends on (BFIN561_BLUETECHNIX_CM)
	default y

config MEM_MT48LC32M16A2TG_75
	bool
	depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
	default y

config MEM_MT48H32M16LFCJ_75
	bool
	depends on (BFIN526_EZBRD)
	default y

config MEM_MT47H64M16
	bool
	depends on (BFIN609_EZKIT)
	default y

source "arch/blackfin/mach-bf518/Kconfig"
source "arch/blackfin/mach-bf527/Kconfig"
source "arch/blackfin/mach-bf533/Kconfig"
source "arch/blackfin/mach-bf561/Kconfig"
source "arch/blackfin/mach-bf537/Kconfig"
source "arch/blackfin/mach-bf538/Kconfig"
source "arch/blackfin/mach-bf548/Kconfig"
source "arch/blackfin/mach-bf609/Kconfig"

menu "Board customizations"

config CMDLINE_BOOL
	bool "Default bootloader kernel arguments"

config CMDLINE
	string "Initial kernel command string"
	depends on CMDLINE_BOOL
	default "console=ttyBF0,57600"
	help
	  If you don't have a boot loader capable of passing a command line string
	  to the kernel, you may specify one here. As a minimum, you should specify
	  the memory size and the root device (e.g., mem=8M, root=/dev/nfs).

config BOOT_LOAD
	hex "Kernel load address for booting"
	default "0x1000"
	range 0x1000 0x20000000
	help
	  This option allows you to set the load address of the kernel.
	  This can be useful if you are on a board which has a small amount
	  of memory or you wish to reserve some memory at the beginning of
	  the address space.

	  Note that you need to keep this value above 4k (0x1000) as this
	  memory region is used to capture NULL pointer references as well
	  as some core kernel functions.

config PHY_RAM_BASE_ADDRESS
	hex "Physical RAM Base"
	default 0x0
	help
	  set BF609 FPGA physical SRAM base address

config ROM_BASE
	hex "Kernel ROM Base"
	depends on ROMKERNEL
	default "0x20040040"
	range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
	range 0x20000000 0x30000000 if (BF54x || BF561)
	range 0xB0000000 0xC0000000 if (BF60x)
	help
	  Make sure your ROM base does not include any file-header
	  information that is prepended to the kernel.

	  For example, the bootable U-Boot format (created with
	  mkimage) has a 64 byte header (0x40).  So while the image
	  you write to flash might start at say 0x20080000, you have
	  to add 0x40 to get the kernel's ROM base as it will come
	  after the header.

comment "Clock/PLL Setup"

config CLKIN_HZ
	int "Frequency of the crystal on the board in Hz"
	default "10000000" if BFIN532_IP0X
	default "11059200" if BFIN533_STAMP
	default "24576000" if PNAV10
	default "25000000" # most people use this
	default "27000000" if BFIN533_EZKIT
	default "30000000" if BFIN561_EZKIT
	default "24000000" if BFIN527_AD7160EVAL
	help
	  The frequency of CLKIN crystal oscillator on the board in Hz.
	  Warning: This value should match the crystal on the board. Otherwise,
	  peripherals won't work properly.

config BFIN_KERNEL_CLOCK
	bool "Re-program Clocks while Kernel boots?"
	default n
	help
	  This option decides if kernel clocks are re-programed from the
	  bootloader settings. If the clocks are not set, the SDRAM settings
	  are also not changed, and the Bootloader does 100% of the hardware
	  configuration.

config PLL_BYPASS
	bool "Bypass PLL"
	depends on BFIN_KERNEL_CLOCK && (!BF60x)
	default n

config CLKIN_HALF
	bool "Half Clock In"
	depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
	default n
	help
	  If this is set the clock will be divided by 2, before it goes to the PLL.

config VCO_MULT
	int "VCO Multiplier"
	depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
	range 1 64
	default "22" if BFIN533_EZKIT
	default "45" if BFIN533_STAMP
	default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
	default "22" if BFIN533_BLUETECHNIX_CM
	default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
	default "20" if (BFIN561_EZKIT || BF609)
	default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
	default "25" if BFIN527_AD7160EVAL
	help
	  This controls the frequency of the on-chip PLL. This can be between 1 and 64.
	  PLL Frequency = (Crystal Frequency) * (this setting)

choice
	prompt "Core Clock Divider"
	depends on BFIN_KERNEL_CLOCK
	default CCLK_DIV_1
	help
	  This sets the frequency of the core. It can be 1, 2, 4 or 8
	  Core Frequency = (PLL frequency) / (this setting)

config CCLK_DIV_1
	bool "1"

config CCLK_DIV_2
	bool "2"

config CCLK_DIV_4
	bool "4"

config CCLK_DIV_8
	bool "8"
endchoice

config SCLK_DIV
	int "System Clock Divider"
	depends on BFIN_KERNEL_CLOCK
	range 1 15
	default 4
	help
	  This sets the frequency of the system clock (including SDRAM or DDR) on
	  !BF60x else it set the clock for system buses and provides the
	  source from which SCLK0 and SCLK1 are derived.
	  This can be between 1 and 15
	  System Clock = (PLL frequency) / (this setting)

config SCLK0_DIV
	int "System Clock0 Divider"
	depends on BFIN_KERNEL_CLOCK && BF60x
	range 1 15
	default 1
	help
	  This sets the frequency of the system clock0 for PVP and all other
	  peripherals not clocked by SCLK1.
	  This can be between 1 and 15
	  System Clock0 = (System Clock) / (this setting)

config SCLK1_DIV
	int "System Clock1 Divider"
	depends on BFIN_KERNEL_CLOCK && BF60x
	range 1 15
	default 1
	help
	  This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
	  This can be between 1 and 15
	  System Clock1 = (System Clock) / (this setting)

config DCLK_DIV
	int "DDR Clock Divider"
	depends on BFIN_KERNEL_CLOCK && BF60x
	range 1 15
	default 2
	help
	  This sets the frequency of the DDR memory.
	  This can be between 1 and 15
	  DDR Clock = (PLL frequency) / (this setting)

choice
	prompt "DDR SDRAM Chip Type"
	depends on BFIN_KERNEL_CLOCK
	depends on BF54x
	default MEM_MT46V32M16_5B

config MEM_MT46V32M16_6T
	bool "MT46V32M16_6T"

config MEM_MT46V32M16_5B
	bool "MT46V32M16_5B"
endchoice

choice
	prompt "DDR/SDRAM Timing"
	depends on BFIN_KERNEL_CLOCK && !BF60x
	default BFIN_KERNEL_CLOCK_MEMINIT_CALC
	help
	  This option allows you to specify Blackfin SDRAM/DDR Timing parameters
	  The calculated SDRAM timing parameters may not be 100%
	  accurate - This option is therefore marked experimental.

config BFIN_KERNEL_CLOCK_MEMINIT_CALC
	bool "Calculate Timings (EXPERIMENTAL)"
	depends on EXPERIMENTAL

config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
	bool "Provide accurate Timings based on target SCLK"
	help
	  Please consult the Blackfin Hardware Reference Manuals as well
	  as the memory device datasheet.
	  http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
endchoice

menu "Memory Init Control"
	depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC

config MEM_DDRCTL0
	depends on BF54x
	hex "DDRCTL0"
	default 0x0

config MEM_DDRCTL1
	depends on BF54x
	hex "DDRCTL1"
	default 0x0

config MEM_DDRCTL2
	depends on BF54x
	hex "DDRCTL2"
	default 0x0

config MEM_EBIU_DDRQUE
	depends on BF54x
	hex "DDRQUE"
	default 0x0

config MEM_SDRRC
	depends on !BF54x
	hex "SDRRC"
	default 0x0

config MEM_SDGCTL
	depends on !BF54x
	hex "SDGCTL"
	default 0x0
endmenu

#
# Max & Min Speeds for various Chips
#
config MAX_VCO_HZ
	int
	default 400000000 if BF512
	default 400000000 if BF514
	default 400000000 if BF516
	default 400000000 if BF518
	default 400000000 if BF522
	default 600000000 if BF523
	default 400000000 if BF524
	default 600000000 if BF525
	default 400000000 if BF526
	default 600000000 if BF527
	default 400000000 if BF531
	default 400000000 if BF532
	default 750000000 if BF533
	default 500000000 if BF534
	default 400000000 if BF536
	default 600000000 if BF537
	default 533333333 if BF538
	default 533333333 if BF539
	default 600000000 if BF542
	default 533333333 if BF544
	default 600000000 if BF547
	default 600000000 if BF548
	default 533333333 if BF549
	default 600000000 if BF561
	default 800000000 if BF609

config MIN_VCO_HZ
	int
	default 50000000

config MAX_SCLK_HZ
	int
	default 200000000 if BF609
	default 133333333

config MIN_SCLK_HZ
	int
	default 27000000

comment "Kernel Timer/Scheduler"

source kernel/Kconfig.hz

config SET_GENERIC_CLOCKEVENTS
	bool "Generic clock events"
	default y
	select GENERIC_CLOCKEVENTS

menu "Clock event device"
	depends on GENERIC_CLOCKEVENTS
config TICKSOURCE_GPTMR0
	bool "GPTimer0"
	depends on !SMP
	select BFIN_GPTIMERS

config TICKSOURCE_CORETMR
	bool "Core timer"
	default y
endmenu

menu "Clock souce"
	depends on GENERIC_CLOCKEVENTS
config CYCLES_CLOCKSOURCE
	bool "CYCLES"
	default y
	depends on !BFIN_SCRATCH_REG_CYCLES
	depends on !SMP
	help
	  If you say Y here, you will enable support for using the 'cycles'
	  registers as a clock source.  Doing so means you will be unable to
	  safely write to the 'cycles' register during runtime.  You will
	  still be able to read it (such as for performance monitoring), but
	  writing the registers will most likely crash the kernel.

config GPTMR0_CLOCKSOURCE
	bool "GPTimer0"
	select BFIN_GPTIMERS
	depends on !TICKSOURCE_GPTMR0
endmenu

comment "Misc"

choice
	prompt "Blackfin Exception Scratch Register"
	default BFIN_SCRATCH_REG_RETN
	help
	  Select the resource to reserve for the Exception handler:
	    - RETN: Non-Maskable Interrupt (NMI)
	    - RETE: Exception Return (JTAG/ICE)
	    - CYCLES: Performance counter

	  If you are unsure, please select "RETN".

config BFIN_SCRATCH_REG_RETN
	bool "RETN"
	help
	  Use the RETN register in the Blackfin exception handler
	  as a stack scratch register.  This means you cannot
	  safely use NMI on the Blackfin while running Linux, but
	  you can debug the system with a JTAG ICE and use the
	  CYCLES performance registers.

	  If you are unsure, please select "RETN".

config BFIN_SCRATCH_REG_RETE
	bool "RETE"
	help
	  Use the RETE register in the Blackfin exception handler
	  as a stack scratch register.  This means you cannot
	  safely use a JTAG ICE while debugging a Blackfin board,
	  but you can safely use the CYCLES performance registers
	  and the NMI.

	  If you are unsure, please select "RETN".

config BFIN_SCRATCH_REG_CYCLES
	bool "CYCLES"
	help
	  Use the CYCLES register in the Blackfin exception handler
	  as a stack scratch register.  This means you cannot
	  safely use the CYCLES performance registers on a Blackfin
	  board at anytime, but you can debug the system with a JTAG
	  ICE and use the NMI.

	  If you are unsure, please select "RETN".

endchoice

endmenu


menu "Blackfin Kernel Optimizations"

comment "Memory Optimizations"

config I_ENTRY_L1
	bool "Locate interrupt entry code in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
	  into L1 instruction memory. (less latency)

config EXCPT_IRQ_SYSC_L1
	bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, the entire ASM lowlevel exception and interrupt entry code
	  (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
	  (less latency)

config DO_IRQ_L1
	bool "Locate frequently called do_irq dispatcher function in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, the frequently called do_irq dispatcher function is linked
	  into L1 instruction memory. (less latency)

config CORE_TIMER_IRQ_L1
	bool "Locate frequently called timer_interrupt() function in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, the frequently called timer_interrupt() function is linked
	  into L1 instruction memory. (less latency)

config IDLE_L1
	bool "Locate frequently idle function in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, the frequently called idle function is linked
	  into L1 instruction memory. (less latency)

config SCHEDULE_L1
	bool "Locate kernel schedule function in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, the frequently called kernel schedule is linked
	  into L1 instruction memory. (less latency)

config ARITHMETIC_OPS_L1
	bool "Locate kernel owned arithmetic functions in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, arithmetic functions are linked
	  into L1 instruction memory. (less latency)

config ACCESS_OK_L1
	bool "Locate access_ok function in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, the access_ok function is linked
	  into L1 instruction memory. (less latency)

config MEMSET_L1
	bool "Locate memset function in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, the memset function is linked
	  into L1 instruction memory. (less latency)

config MEMCPY_L1
	bool "Locate memcpy function in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, the memcpy function is linked
	  into L1 instruction memory. (less latency)

config STRCMP_L1
	bool "locate strcmp function in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, the strcmp function is linked
	  into L1 instruction memory (less latency).

config STRNCMP_L1
	bool "locate strncmp function in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, the strncmp function is linked
	  into L1 instruction memory (less latency).

config STRCPY_L1
	bool "locate strcpy function in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, the strcpy function is linked
	  into L1 instruction memory (less latency).

config STRNCPY_L1
	bool "locate strncpy function in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, the strncpy function is linked
	  into L1 instruction memory (less latency).

config SYS_BFIN_SPINLOCK_L1
	bool "Locate sys_bfin_spinlock function in L1 Memory"
	default y
	depends on !SMP
	help
	  If enabled, sys_bfin_spinlock function is linked
	  into L1 instruction memory. (less latency)

config IP_CHECKSUM_L1
	bool "Locate IP Checksum function in L1 Memory"
	default n
	depends on !SMP
	help
	  If enabled, the IP Checksum function is linked
	  into L1 instruction memory. (less latency)

config CACHELINE_ALIGNED_L1
	bool "Locate cacheline_aligned data to L1 Data Memory"
	default y if !BF54x
	default n if BF54x
	depends on !SMP && !BF531 && !CRC32
	help
	  If enabled, cacheline_aligned data is linked
	  into L1 data memory. (less latency)

config SYSCALL_TAB_L1
	bool "Locate Syscall Table L1 Data Memory"
	default n
	depends on !SMP && !BF531
	help
	  If enabled, the Syscall LUT is linked
	  into L1 data memory. (less latency)

config CPLB_SWITCH_TAB_L1
	bool "Locate CPLB Switch Tables L1 Data Memory"
	default n
	depends on !SMP && !BF531
	help
	  If enabled, the CPLB Switch Tables are linked
	  into L1 data memory. (less latency)

config ICACHE_FLUSH_L1
	bool "Locate icache flush funcs in L1 Inst Memory"
	default y
	help
	  If enabled, the Blackfin icache flushing functions are linked
	  into L1 instruction memory.

	  Note that this might be required to address anomalies, but
	  these functions are pretty small, so it shouldn't be too bad.
	  If you are using a processor affected by an anomaly, the build
	  system will double check for you and prevent it.

config DCACHE_FLUSH_L1
	bool "Locate dcache flush funcs in L1 Inst Memory"
	default y
	depends on !SMP
	help
	  If enabled, the Blackfin dcache flushing functions are linked
	  into L1 instruction memory.

config APP_STACK_L1
	bool "Support locating application stack in L1 Scratch Memory"
	default y
	depends on !SMP
	help
	  If enabled the application stack can be located in L1
	  scratch memory (less latency).

	  Currently only works with FLAT binaries.

config EXCEPTION_L1_SCRATCH
	bool "Locate exception stack in L1 Scratch Memory"
	default n
	depends on !SMP && !APP_STACK_L1
	help
	  Whenever an exception occurs, use the L1 Scratch memory for
	  stack storage.  You cannot place the stacks of FLAT binaries
	  in L1 when using this option.

	  If you don't use L1 Scratch, then you should say Y here.

comment "Speed Optimizations"
config BFIN_INS_LOWOVERHEAD
	bool "ins[bwl] low overhead, higher interrupt latency"
	default y
	depends on !SMP
	help
	  Reads on the Blackfin are speculative. In Blackfin terms, this means
	  they can be interrupted at any time (even after they have been issued
	  on to the external bus), and re-issued after the interrupt occurs.
	  For memory - this is not a big deal, since memory does not change if
	  it sees a read.

	  If a FIFO is sitting on the end of the read, it will see two reads,
	  when the core only sees one since the FIFO receives both the read
	  which is cancelled (and not delivered to the core) and the one which
	  is re-issued (which is delivered to the core).

	  To solve this, interrupts are turned off before reads occur to
	  I/O space. This option controls which the overhead/latency of
	  controlling interrupts during this time
	   "n" turns interrupts off every read
		(higher overhead, but lower interrupt latency)
	   "y" turns interrupts off every loop
		(low overhead, but longer interrupt latency)

	  default behavior is to leave this set to on (type "Y"). If you are experiencing
	  interrupt latency issues, it is safe and OK to turn this off.

endmenu

choice
	prompt "Kernel executes from"
	help
	  Choose the memory type that the kernel will be running in.

config RAMKERNEL
	bool "RAM"
	help
	  The kernel will be resident in RAM when running.

config ROMKERNEL
	bool "ROM"
	help
	  The kernel will be resident in FLASH/ROM when running.

endchoice

# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
config XIP_KERNEL
	bool
	default y
	depends on ROMKERNEL

source "mm/Kconfig"

config BFIN_GPTIMERS
	tristate "Enable Blackfin General Purpose Timers API"
	default n
	help
	  Enable support for the General Purpose Timers API.  If you
	  are unsure, say N.

	  To compile this driver as a module, choose M here: the module
	  will be called gptimers.

choice
	prompt "Uncached DMA region"
	default DMA_UNCACHED_1M
config DMA_UNCACHED_32M
	bool "Enable 32M DMA region"
config DMA_UNCACHED_16M
	bool "Enable 16M DMA region"
config DMA_UNCACHED_8M
	bool "Enable 8M DMA region"
config DMA_UNCACHED_4M
	bool "Enable 4M DMA region"
config DMA_UNCACHED_2M
	bool "Enable 2M DMA region"
config DMA_UNCACHED_1M
	bool "Enable 1M DMA region"
config DMA_UNCACHED_512K
	bool "Enable 512K DMA region"
config DMA_UNCACHED_256K
	bool "Enable 256K DMA region"
config DMA_UNCACHED_128K
	bool "Enable 128K DMA region"
config DMA_UNCACHED_NONE
	bool "Disable DMA region"
endchoice


comment "Cache Support"

config BFIN_ICACHE
	bool "Enable ICACHE"
	default y
config BFIN_EXTMEM_ICACHEABLE
	bool "Enable ICACHE for external memory"
	depends on BFIN_ICACHE
	default y
config BFIN_L2_ICACHEABLE
	bool "Enable ICACHE for L2 SRAM"
	depends on BFIN_ICACHE
	depends on (BF54x || BF561 || BF60x) && !SMP
	default n

config BFIN_DCACHE
	bool "Enable DCACHE"
	default y
config BFIN_DCACHE_BANKA
	bool "Enable only 16k BankA DCACHE - BankB is SRAM"
	depends on BFIN_DCACHE && !BF531
	default n
config BFIN_EXTMEM_DCACHEABLE
	bool "Enable DCACHE for external memory"
	depends on BFIN_DCACHE
	default y
choice
	prompt "External memory DCACHE policy"
	depends on BFIN_EXTMEM_DCACHEABLE
	default BFIN_EXTMEM_WRITEBACK if !SMP
	default BFIN_EXTMEM_WRITETHROUGH if SMP
config BFIN_EXTMEM_WRITEBACK
	bool "Write back"
	depends on !SMP
	help
	  Write Back Policy:
	    Cached data will be written back to SDRAM only when needed.
	    This can give a nice increase in performance, but beware of
	    broken drivers that do not properly invalidate/flush their
	    cache.

	  Write Through Policy:
	    Cached data will always be written back to SDRAM when the
	    cache is updated.  This is a completely safe setting, but
	    performance is worse than Write Back.

	  If you are unsure of the options and you want to be safe,
	  then go with Write Through.

config BFIN_EXTMEM_WRITETHROUGH
	bool "Write through"
	help
	  Write Back Policy:
	    Cached data will be written back to SDRAM only when needed.
	    This can give a nice increase in performance, but beware of
	    broken drivers that do not properly invalidate/flush their
	    cache.

	  Write Through Policy:
	    Cached data will always be written back to SDRAM when the
	    cache is updated.  This is a completely safe setting, but
	    performance is worse than Write Back.

	  If you are unsure of the options and you want to be safe,
	  then go with Write Through.

endchoice

config BFIN_L2_DCACHEABLE
	bool "Enable DCACHE for L2 SRAM"
	depends on BFIN_DCACHE
	depends on (BF54x || BF561 || BF60x) && !SMP
	default n
choice
	prompt "L2 SRAM DCACHE policy"
	depends on BFIN_L2_DCACHEABLE
	default BFIN_L2_WRITEBACK
config BFIN_L2_WRITEBACK
	bool "Write back"

config BFIN_L2_WRITETHROUGH
	bool "Write through"
endchoice


comment "Memory Protection Unit"
config MPU
	bool "Enable the memory protection unit (EXPERIMENTAL)"
	default n
	help
	  Use the processor's MPU to protect applications from accessing
	  memory they do not own.  This comes at a performance penalty
	  and is recommended only for debugging.

comment "Asynchronous Memory Configuration"

menu "EBIU_AMGCTL Global Control"
	depends on !BF60x
config C_AMCKEN
	bool "Enable CLKOUT"
	default y

config C_CDPRIO
	bool "DMA has priority over core for ext. accesses"
	default n

config C_B0PEN
	depends on BF561
	bool "Bank 0 16 bit packing enable"
	default y

config C_B1PEN
	depends on BF561
	bool "Bank 1 16 bit packing enable"
	default y

config C_B2PEN
	depends on BF561
	bool "Bank 2 16 bit packing enable"
	default y

config C_B3PEN
	depends on BF561
	bool "Bank 3 16 bit packing enable"
	default n

choice
	prompt "Enable Asynchronous Memory Banks"
	default C_AMBEN_ALL

config C_AMBEN
	bool "Disable All Banks"

config C_AMBEN_B0
	bool "Enable Bank 0"

config C_AMBEN_B0_B1
	bool "Enable Bank 0 & 1"

config C_AMBEN_B0_B1_B2
	bool "Enable Bank 0 & 1 & 2"

config C_AMBEN_ALL
	bool "Enable All Banks"
endchoice
endmenu

menu "EBIU_AMBCTL Control"
	depends on !BF60x
config BANK_0
	hex "Bank 0 (AMBCTL0.L)"
	default 0x7BB0
	help
	  These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
	  used to control the Asynchronous Memory Bank 0 settings.

config BANK_1
	hex "Bank 1 (AMBCTL0.H)"
	default 0x7BB0
	default 0x5558 if BF54x
	help
	  These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
	  used to control the Asynchronous Memory Bank 1 settings.

config BANK_2
	hex "Bank 2 (AMBCTL1.L)"
	default 0x7BB0
	help
	  These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
	  used to control the Asynchronous Memory Bank 2 settings.

config BANK_3
	hex "Bank 3 (AMBCTL1.H)"
	default 0x99B3
	help
	  These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
	  used to control the Asynchronous Memory Bank 3 settings.

endmenu

config EBIU_MBSCTLVAL
	hex "EBIU Bank Select Control Register"
	depends on BF54x
	default 0

config EBIU_MODEVAL
	hex "Flash Memory Mode Control Register"
	depends on BF54x
	default 1

config EBIU_FCTLVAL
	hex "Flash Memory Bank Control Register"
	depends on BF54x
	default 6
endmenu

#############################################################################
menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"

config PCI
	bool "PCI support"
	depends on BROKEN
	help
	  Support for PCI bus.

source "drivers/pci/Kconfig"

source "drivers/pcmcia/Kconfig"

source "drivers/pci/hotplug/Kconfig"

endmenu

menu "Executable file formats"

source "fs/Kconfig.binfmt"

endmenu

menu "Power management options"

source "kernel/power/Kconfig"

config ARCH_SUSPEND_POSSIBLE
	def_bool y

choice
	prompt "Standby Power Saving Mode"
	depends on PM && !BF60x
	default PM_BFIN_SLEEP_DEEPER
config  PM_BFIN_SLEEP_DEEPER
	bool "Sleep Deeper"
	help
	  Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
	  power dissipation by disabling the clock to the processor core (CCLK).
	  Furthermore, Standby sets the internal power supply voltage (VDDINT)
	  to 0.85 V to provide the greatest power savings, while preserving the
	  processor state.
	  The PLL and system clock (SCLK) continue to operate at a very low
	  frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
	  the SDRAM is put into Self Refresh Mode. Typically an external event
	  such as GPIO interrupt or RTC activity wakes up the processor.
	  Various Peripherals such as UART, SPORT, PPI may not function as
	  normal during Sleep Deeper, due to the reduced SCLK frequency.
	  When in the sleep mode, system DMA access to L1 memory is not supported.

	  If unsure, select "Sleep Deeper".

config  PM_BFIN_SLEEP
	bool "Sleep"
	help
	  Sleep Mode (High Power Savings) - The sleep mode reduces power
	  dissipation by disabling the clock to the processor core (CCLK).
	  The PLL and system clock (SCLK), however, continue to operate in
	  this mode. Typically an external event or RTC activity will wake
	  up the processor. When in the sleep mode, system DMA access to L1
	  memory is not supported.

	  If unsure, select "Sleep Deeper".
endchoice

comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
	depends on PM

config PM_BFIN_WAKE_PH6
	bool "Allow Wake-Up from on-chip PHY or PH6 GP"
	depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
	default n
	help
	  Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)

config PM_BFIN_WAKE_GP
	bool "Allow Wake-Up from GPIOs"
	depends on PM && BF54x
	default n
	help
	  Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
	  (all processors, except ADSP-BF549). This option sets
	  the general-purpose wake-up enable (GPWE) control bit to enable
	  wake-up upon detection of an active low signal on the /GPW (PH7) pin.
	  On ADSP-BF549 this option enables the same functionality on the
	  /MRXON pin also PH7.

config PM_BFIN_WAKE_PA15
	bool "Allow Wake-Up from PA15"
	depends on PM && BF60x
	default n
	help
	  Enable PA15 Wake-Up

config PM_BFIN_WAKE_PA15_POL
	int "Wake-up priority"
	depends on PM_BFIN_WAKE_PA15
	default 0
	help
	  Wake-Up priority 0(low) 1(high)

config PM_BFIN_WAKE_PB15
	bool "Allow Wake-Up from PB15"
	depends on PM && BF60x
	default n
	help
	  Enable PB15 Wake-Up

config PM_BFIN_WAKE_PB15_POL
	int "Wake-up priority"
	depends on PM_BFIN_WAKE_PB15
	default 0
	help
	  Wake-Up priority 0(low) 1(high)

config PM_BFIN_WAKE_PC15
	bool "Allow Wake-Up from PC15"
	depends on PM && BF60x
	default n
	help
	  Enable PC15 Wake-Up

config PM_BFIN_WAKE_PC15_POL
	int "Wake-up priority"
	depends on PM_BFIN_WAKE_PC15
	default 0
	help
	  Wake-Up priority 0(low) 1(high)

config PM_BFIN_WAKE_PD06
	bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
	depends on PM && BF60x
	default n
	help
	  Enable PD06(ETH0_PHYINT) Wake-up

config PM_BFIN_WAKE_PD06_POL
	int "Wake-up priority"
	depends on PM_BFIN_WAKE_PD06
	default 0
	help
	  Wake-Up priority 0(low) 1(high)

config PM_BFIN_WAKE_PE12
	bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
	depends on PM && BF60x
	default n
	help
	  Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up

config PM_BFIN_WAKE_PE12_POL
	int "Wake-up priority"
	depends on PM_BFIN_WAKE_PE12
	default 0
	help
	  Wake-Up priority 0(low) 1(high)

config PM_BFIN_WAKE_PG04
	bool "Allow Wake-Up from PG04(CAN0_RX)"
	depends on PM && BF60x
	default n
	help
	  Enable PG04(CAN0_RX) Wake-up

config PM_BFIN_WAKE_PG04_POL
	int "Wake-up priority"
	depends on PM_BFIN_WAKE_PG04
	default 0
	help
	  Wake-Up priority 0(low) 1(high)

config PM_BFIN_WAKE_PG13
	bool "Allow Wake-Up from PG13"
	depends on PM && BF60x
	default n
	help
	  Enable PG13 Wake-Up

config PM_BFIN_WAKE_PG13_POL
	int "Wake-up priority"
	depends on PM_BFIN_WAKE_PG13
	default 0
	help
	  Wake-Up priority 0(low) 1(high)

config PM_BFIN_WAKE_USB
	bool "Allow Wake-Up from (USB)"
	depends on PM && BF60x
	default n
	help
	  Enable (USB) Wake-up

config PM_BFIN_WAKE_USB_POL
	int "Wake-up priority"
	depends on PM_BFIN_WAKE_USB
	default 0
	help
	  Wake-Up priority 0(low) 1(high)

endmenu

menu "CPU Frequency scaling"

source "drivers/cpufreq/Kconfig"

config BFIN_CPU_FREQ
	bool
	depends on CPU_FREQ
	select CPU_FREQ_TABLE
	default y

config CPU_VOLTAGE
	bool "CPU Voltage scaling"
	depends on EXPERIMENTAL
	depends on CPU_FREQ
	default n
	help
	  Say Y here if you want CPU voltage scaling according to the CPU frequency.
	  This option violates the PLL BYPASS recommendation in the Blackfin Processor
	  manuals. There is a theoretical risk that during VDDINT transitions
	  the PLL may unlock.

endmenu

source "net/Kconfig"

source "drivers/Kconfig"

source "drivers/firmware/Kconfig"

source "fs/Kconfig"

source "arch/blackfin/Kconfig.debug"

source "security/Kconfig"

source "crypto/Kconfig"

source "lib/Kconfig"