[deliverable/linux.git] / arch / blackfin / include / asm / cplb.h

/*
 * File:         include/asm-blackfin/cplb.h
 * Based on:     include/asm-blackfin/mach-bf537/bf537.h
 * Author:       Robin Getz <rgetz@blackfin.uclinux.org>
 *
 * Created:      2000
 * Description:  Common CPLB definitions for CPLB init
 *
 * Modified:
 *               Copyright 2004-2007 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#ifndef _CPLB_H
#define _CPLB_H

#include <mach/anomaly.h>

#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)

#if ANOMALY_05000158
#define ANOMALY_05000158_WORKAROUND             0x200
#else
#define ANOMALY_05000158_WORKAROUND             0x0
#endif

#define CPLB_COMMON	(CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)

#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_COMMON)
#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_COMMON)
#else
#define SDRAM_DGENERIC   (CPLB_COMMON)
#endif

#define SDRAM_DNON_CHBL  (CPLB_COMMON)
#define SDRAM_EBIU       (CPLB_COMMON)
#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)

#define L1_DMEMORY       (CPLB_LOCK | CPLB_COMMON)

#ifdef CONFIG_SMP
#define L2_ATTR          (INITIAL_T | I_CPLB | D_CPLB)
#define L2_IMEMORY       (CPLB_COMMON | PAGE_SIZE_1MB)
#define L2_DMEMORY       (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)

#else
#define L2_ATTR          (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
# if defined(CONFIG_BFIN_L2_ICACHEABLE)
# define L2_IMEMORY      (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
# else
# define L2_IMEMORY      (               CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
# endif

# if defined(CONFIG_BFIN_L2_WRITEBACK)
# define L2_DMEMORY      (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
# elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
# define L2_DMEMORY      (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
# else
# define L2_DMEMORY      (CPLB_COMMON | PAGE_SIZE_1MB)
# endif
#endif /* CONFIG_SMP */

#define SIZE_1K 0x00000400      /* 1K */
#define SIZE_4K 0x00001000      /* 4K */
#define SIZE_1M 0x00100000      /* 1M */
#define SIZE_4M 0x00400000      /* 4M */

#define MAX_CPLBS 16

#define CPLB_ENABLE_ICACHE_P	0
#define CPLB_ENABLE_DCACHE_P	1
#define CPLB_ENABLE_DCACHE2_P	2
#define CPLB_ENABLE_CPLBS_P	3	/* Deprecated! */
#define CPLB_ENABLE_ICPLBS_P	4
#define CPLB_ENABLE_DCPLBS_P	5

#define CPLB_ENABLE_ICACHE	(1<<CPLB_ENABLE_ICACHE_P)
#define CPLB_ENABLE_DCACHE	(1<<CPLB_ENABLE_DCACHE_P)
#define CPLB_ENABLE_DCACHE2	(1<<CPLB_ENABLE_DCACHE2_P)
#define CPLB_ENABLE_CPLBS	(1<<CPLB_ENABLE_CPLBS_P)
#define CPLB_ENABLE_ICPLBS	(1<<CPLB_ENABLE_ICPLBS_P)
#define CPLB_ENABLE_DCPLBS	(1<<CPLB_ENABLE_DCPLBS_P)
#define CPLB_ENABLE_ANY_CPLBS	CPLB_ENABLE_CPLBS | \
				CPLB_ENABLE_ICPLBS | \
				CPLB_ENABLE_DCPLBS

#define CPLB_RELOADED		0x0000
#define CPLB_NO_UNLOCKED	0x0001
#define CPLB_NO_ADDR_MATCH	0x0002
#define CPLB_PROT_VIOL		0x0003
#define CPLB_UNKNOWN_ERR	0x0004

#define CPLB_DEF_CACHE		CPLB_L1_CHBL | CPLB_WT
#define CPLB_CACHE_ENABLED	CPLB_L1_CHBL | CPLB_DIRTY

#define CPLB_I_PAGE_MGMT	CPLB_LOCK | CPLB_VALID
#define CPLB_D_PAGE_MGMT	CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
#define CPLB_DNOCACHE		CPLB_ALL_ACCESS | CPLB_VALID
#define CPLB_DDOCACHE		CPLB_DNOCACHE | CPLB_DEF_CACHE
#define CPLB_INOCACHE   	CPLB_USER_RD | CPLB_VALID
#define CPLB_IDOCACHE   	CPLB_INOCACHE | CPLB_L1_CHBL

#define FAULT_RW        (1 << 16)
#define FAULT_USERSUPV  (1 << 17)
#define FAULT_CPLBBITS  0x0000ffff

#endif				/* _CPLB_H */
Commit	Line	Data
3bebca2d RG	1	/*
	2	* File: include/asm-blackfin/cplb.h
	3	* Based on: include/asm-blackfin/mach-bf537/bf537.h
	4	* Author: Robin Getz <rgetz@blackfin.uclinux.org>
1394f032	5	*
3bebca2d RG	6	* Created: 2000
3bebca2d RG	7	* Description: Common CPLB definitions for CPLB init
1394f032	8	*
3bebca2d RG	9	* Modified:
3bebca2d RG	10	* Copyright 2004-2007 Analog Devices Inc.
1394f032	11	*
3bebca2d RG	12	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, see the file COPYING, or write
	26	* to the Free Software Foundation, Inc.,
	27	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	28	*/
1394f032 BW	29
	30	#ifndef _CPLB_H
	31	#define _CPLB_H
	32
639f6571	33	#include <mach/anomaly.h>
1394f032	34
3bebca2d RG	35	#define SDRAM_IGENERIC (CPLB_L1_CHBL \| CPLB_USER_RD \| CPLB_VALID \| CPLB_PORTPRIO)
	36	#define SDRAM_IKERNEL (SDRAM_IGENERIC \| CPLB_LOCK)
	37	#define L1_IMEMORY ( CPLB_USER_RD \| CPLB_VALID \| CPLB_LOCK)
	38	#define SDRAM_INON_CHBL ( CPLB_USER_RD \| CPLB_VALID)
	39
3bebca2d RG	40	#if ANOMALY_05000158
	41	#define ANOMALY_05000158_WORKAROUND 0x200
	42	#else
	43	#define ANOMALY_05000158_WORKAROUND 0x0
	44	#endif
	45
	46	#define CPLB_COMMON (CPLB_DIRTY \| CPLB_SUPV_WR \| CPLB_USER_WR \| CPLB_USER_RD \| CPLB_VALID \| ANOMALY_05000158_WORKAROUND)
	47
41ba653f	48	#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
3bebca2d	49	#define SDRAM_DGENERIC (CPLB_L1_CHBL \| CPLB_COMMON)
41ba653f	50	#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
3bebca2d	51	#define SDRAM_DGENERIC (CPLB_L1_CHBL \| CPLB_WT \| CPLB_L1_AOW \| CPLB_COMMON)
41ba653f JZ	52	#else
41ba653f JZ	53	#define SDRAM_DGENERIC (CPLB_COMMON)
3bebca2d RG	54	#endif
3bebca2d RG	55
5ba76675 GY	56	#define SDRAM_DNON_CHBL (CPLB_COMMON)
	57	#define SDRAM_EBIU (CPLB_COMMON)
	58	#define SDRAM_OOPS (CPLB_VALID \| ANOMALY_05000158_WORKAROUND \| CPLB_LOCK \| CPLB_DIRTY)
	59
3bebca2d	60	#define L1_DMEMORY (CPLB_LOCK \| CPLB_COMMON)
b8a98989 GY	61
b8a98989 GY	62	#ifdef CONFIG_SMP
5ba76675	63	#define L2_ATTR (INITIAL_T \| I_CPLB \| D_CPLB)
41ba653f JZ	64	#define L2_IMEMORY (CPLB_COMMON \| PAGE_SIZE_1MB)
41ba653f JZ	65	#define L2_DMEMORY (CPLB_LOCK \| CPLB_COMMON \| PAGE_SIZE_1MB)
b8a98989 GY	66
b8a98989 GY	67	#else
5ba76675	68	#define L2_ATTR (INITIAL_T \| SWITCH_T \| I_CPLB \| D_CPLB)
41ba653f JZ	69	# if defined(CONFIG_BFIN_L2_ICACHEABLE)
	70	# define L2_IMEMORY (CPLB_L1_CHBL \| CPLB_USER_RD \| CPLB_VALID \| PAGE_SIZE_1MB)
	71	# else
	72	# define L2_IMEMORY ( CPLB_USER_RD \| CPLB_VALID \| PAGE_SIZE_1MB)
	73	# endif
5ba76675	74
41ba653f JZ	75	# if defined(CONFIG_BFIN_L2_WRITEBACK)
	76	# define L2_DMEMORY (CPLB_L1_CHBL \| CPLB_COMMON \| PAGE_SIZE_1MB)
	77	# elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
	78	# define L2_DMEMORY (CPLB_L1_CHBL \| CPLB_WT \| CPLB_L1_AOW \| CPLB_COMMON \| PAGE_SIZE_1MB)
5ba76675	79	# else
41ba653f	80	# define L2_DMEMORY (CPLB_COMMON \| PAGE_SIZE_1MB)
5ba76675	81	# endif
b8a98989 GY	82	#endif /* CONFIG_SMP */
b8a98989 GY	83
3bebca2d RG	84	#define SIZE_1K 0x00000400 /* 1K */
	85	#define SIZE_4K 0x00001000 /* 4K */
	86	#define SIZE_1M 0x00100000 /* 1M */
	87	#define SIZE_4M 0x00400000 /* 4M */
	88
b97b8a99	89	#define MAX_CPLBS 16
07bdda02	90
1394f032 BW	91	#define CPLB_ENABLE_ICACHE_P 0
	92	#define CPLB_ENABLE_DCACHE_P 1
	93	#define CPLB_ENABLE_DCACHE2_P 2
	94	#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
	95	#define CPLB_ENABLE_ICPLBS_P 4
	96	#define CPLB_ENABLE_DCPLBS_P 5
	97
	98	#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
	99	#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
	100	#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
	101	#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
	102	#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
	103	#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
	104	#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS \| \
	105	CPLB_ENABLE_ICPLBS \| \
	106	CPLB_ENABLE_DCPLBS
	107
	108	#define CPLB_RELOADED 0x0000
	109	#define CPLB_NO_UNLOCKED 0x0001
	110	#define CPLB_NO_ADDR_MATCH 0x0002
	111	#define CPLB_PROT_VIOL 0x0003
	112	#define CPLB_UNKNOWN_ERR 0x0004
	113
	114	#define CPLB_DEF_CACHE CPLB_L1_CHBL \| CPLB_WT
	115	#define CPLB_CACHE_ENABLED CPLB_L1_CHBL \| CPLB_DIRTY
	116
1394f032 BW	117	#define CPLB_I_PAGE_MGMT CPLB_LOCK \| CPLB_VALID
	118	#define CPLB_D_PAGE_MGMT CPLB_LOCK \| CPLB_ALL_ACCESS \| CPLB_VALID
	119	#define CPLB_DNOCACHE CPLB_ALL_ACCESS \| CPLB_VALID
	120	#define CPLB_DDOCACHE CPLB_DNOCACHE \| CPLB_DEF_CACHE
	121	#define CPLB_INOCACHE CPLB_USER_RD \| CPLB_VALID
	122	#define CPLB_IDOCACHE CPLB_INOCACHE \| CPLB_L1_CHBL
	123
dbdf20db BS	124	#define FAULT_RW (1 << 16)
	125	#define FAULT_USERSUPV (1 << 17)
	126	#define FAULT_CPLBBITS 0x0000ffff
	127
1394f032	128	#endif /* _CPLB_H */